ARM: virt: Update documentation for hyp mode entry support

Document the possibility of the kernel being entered in HYP mode. Signed-off-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

ARM: virt: Update documentation for hyp mode entry support
Document the possibility of the kernel being entered in HYP mode. Signed-off-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Dave Martin · Marc Zyngier
1 parent 424e5994e6
Showing 1 changed file with 21 additions and 1 deletions Side-by-side Diff
Documentation/arm/Booting
@@ -154,12 +154,32 @@
  
 - CPU mode
   All forms of interrupts must be disabled (IRQs and FIQs)
-  The CPU must be in SVC mode.  (A special exception exists for Angel)
  
+  For CPUs which do not include the ARM virtualization extensions, the
+  CPU must be in SVC mode.  (A special exception exists for Angel)
+
+  CPUs which include support for the virtualization extensions can be
+  entered in HYP mode in order to enable the kernel to make full use of
+  these extensions.  This is the recommended boot method for such CPUs,
+  unless the virtualisations are already in use by a pre-installed
+  hypervisor.
+
+  If the kernel is not entered in HYP mode for any reason, it must be
+  entered in SVC mode.
+
 - Caches, MMUs
   The MMU must be off.
   Instruction cache may be on or off.
   Data cache must be off.
+
+  If the kernel is entered in HYP mode, the above requirements apply to
+  the HYP mode configuration in addition to the ordinary PL1 (privileged
+  kernel modes) configuration.  In addition, all traps into the
+  hypervisor must be disabled, and PL1 access must be granted for all
+  peripherals and CPU resources for which this is architecturally
+  possible.  Except for entering in HYP mode, the system configuration
+  should be such that a kernel which does not include support for the
+  virtualization extensions can boot correctly without extra help.
  
 - The boot loader is expected to call the kernel image by jumping
   directly to the first instruction of the kernel image.
...	...	@@ -154,12 +154,32 @@
154	154
155	155	- CPU mode
156	156	All forms of interrupts must be disabled (IRQs and FIQs)
157		- The CPU must be in SVC mode. (A special exception exists for Angel)
158	157
	158	+ For CPUs which do not include the ARM virtualization extensions, the
	159	+ CPU must be in SVC mode. (A special exception exists for Angel)
	160	+
	161	+ CPUs which include support for the virtualization extensions can be
	162	+ entered in HYP mode in order to enable the kernel to make full use of
	163	+ these extensions. This is the recommended boot method for such CPUs,
	164	+ unless the virtualisations are already in use by a pre-installed
	165	+ hypervisor.
	166	+
	167	+ If the kernel is not entered in HYP mode for any reason, it must be
	168	+ entered in SVC mode.
	169	+
159	170	- Caches, MMUs
160	171	The MMU must be off.
161	172	Instruction cache may be on or off.
162	173	Data cache must be off.
	174	+
	175	+ If the kernel is entered in HYP mode, the above requirements apply to
	176	+ the HYP mode configuration in addition to the ordinary PL1 (privileged
	177	+ kernel modes) configuration. In addition, all traps into the
	178	+ hypervisor must be disabled, and PL1 access must be granted for all
	179	+ peripherals and CPU resources for which this is architecturally
	180	+ possible. Except for entering in HYP mode, the system configuration
	181	+ should be such that a kernel which does not include support for the
	182	+ virtualization extensions can boot correctly without extra help.
163	183
164	184	- The boot loader is expected to call the kernel image by jumping
165	185	directly to the first instruction of the kernel image.