Commit 6b3ad9432a345bcea1fad2eab578db6cf4cbe76d
Committed by
Greg Kroah-Hartman
1 parent
3bbf1685d4
Exists in
ti-linux-3.14.y
and in
2 other branches
PCI: designware: Fix iATU programming for cfg1, io and mem viewport
commit 017fcdc30cdae18c0946eef1ece1f14b4c7897ba upstream. This patch corrects iATU programming for cfg1, io and mem viewport. Enable ATU only after configuring it. Signed-off-by: Mohit Kumar <mohit.kumar@st.com> Signed-off-by: Ajay Khandelwal <ajay.khandelwal@st.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Showing 1 changed file with 3 additions and 3 deletions Inline Diff
drivers/pci/host/pcie-designware.c
1 | /* | 1 | /* |
2 | * Synopsys Designware PCIe host controller driver | 2 | * Synopsys Designware PCIe host controller driver |
3 | * | 3 | * |
4 | * Copyright (C) 2013 Samsung Electronics Co., Ltd. | 4 | * Copyright (C) 2013 Samsung Electronics Co., Ltd. |
5 | * http://www.samsung.com | 5 | * http://www.samsung.com |
6 | * | 6 | * |
7 | * Author: Jingoo Han <jg1.han@samsung.com> | 7 | * Author: Jingoo Han <jg1.han@samsung.com> |
8 | * | 8 | * |
9 | * This program is free software; you can redistribute it and/or modify | 9 | * This program is free software; you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 as | 10 | * it under the terms of the GNU General Public License version 2 as |
11 | * published by the Free Software Foundation. | 11 | * published by the Free Software Foundation. |
12 | */ | 12 | */ |
13 | 13 | ||
14 | #include <linux/irq.h> | 14 | #include <linux/irq.h> |
15 | #include <linux/irqdomain.h> | 15 | #include <linux/irqdomain.h> |
16 | #include <linux/kernel.h> | 16 | #include <linux/kernel.h> |
17 | #include <linux/module.h> | 17 | #include <linux/module.h> |
18 | #include <linux/msi.h> | 18 | #include <linux/msi.h> |
19 | #include <linux/of_address.h> | 19 | #include <linux/of_address.h> |
20 | #include <linux/pci.h> | 20 | #include <linux/pci.h> |
21 | #include <linux/pci_regs.h> | 21 | #include <linux/pci_regs.h> |
22 | #include <linux/types.h> | 22 | #include <linux/types.h> |
23 | 23 | ||
24 | #include "pcie-designware.h" | 24 | #include "pcie-designware.h" |
25 | 25 | ||
26 | /* Synopsis specific PCIE configuration registers */ | 26 | /* Synopsis specific PCIE configuration registers */ |
27 | #define PCIE_PORT_LINK_CONTROL 0x710 | 27 | #define PCIE_PORT_LINK_CONTROL 0x710 |
28 | #define PORT_LINK_MODE_MASK (0x3f << 16) | 28 | #define PORT_LINK_MODE_MASK (0x3f << 16) |
29 | #define PORT_LINK_MODE_1_LANES (0x1 << 16) | 29 | #define PORT_LINK_MODE_1_LANES (0x1 << 16) |
30 | #define PORT_LINK_MODE_2_LANES (0x3 << 16) | 30 | #define PORT_LINK_MODE_2_LANES (0x3 << 16) |
31 | #define PORT_LINK_MODE_4_LANES (0x7 << 16) | 31 | #define PORT_LINK_MODE_4_LANES (0x7 << 16) |
32 | 32 | ||
33 | #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C | 33 | #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C |
34 | #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) | 34 | #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) |
35 | #define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8) | 35 | #define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8) |
36 | #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) | 36 | #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) |
37 | #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8) | 37 | #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8) |
38 | #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) | 38 | #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) |
39 | 39 | ||
40 | #define PCIE_MSI_ADDR_LO 0x820 | 40 | #define PCIE_MSI_ADDR_LO 0x820 |
41 | #define PCIE_MSI_ADDR_HI 0x824 | 41 | #define PCIE_MSI_ADDR_HI 0x824 |
42 | #define PCIE_MSI_INTR0_ENABLE 0x828 | 42 | #define PCIE_MSI_INTR0_ENABLE 0x828 |
43 | #define PCIE_MSI_INTR0_MASK 0x82C | 43 | #define PCIE_MSI_INTR0_MASK 0x82C |
44 | #define PCIE_MSI_INTR0_STATUS 0x830 | 44 | #define PCIE_MSI_INTR0_STATUS 0x830 |
45 | 45 | ||
46 | #define PCIE_ATU_VIEWPORT 0x900 | 46 | #define PCIE_ATU_VIEWPORT 0x900 |
47 | #define PCIE_ATU_REGION_INBOUND (0x1 << 31) | 47 | #define PCIE_ATU_REGION_INBOUND (0x1 << 31) |
48 | #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) | 48 | #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) |
49 | #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) | 49 | #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) |
50 | #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) | 50 | #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) |
51 | #define PCIE_ATU_CR1 0x904 | 51 | #define PCIE_ATU_CR1 0x904 |
52 | #define PCIE_ATU_TYPE_MEM (0x0 << 0) | 52 | #define PCIE_ATU_TYPE_MEM (0x0 << 0) |
53 | #define PCIE_ATU_TYPE_IO (0x2 << 0) | 53 | #define PCIE_ATU_TYPE_IO (0x2 << 0) |
54 | #define PCIE_ATU_TYPE_CFG0 (0x4 << 0) | 54 | #define PCIE_ATU_TYPE_CFG0 (0x4 << 0) |
55 | #define PCIE_ATU_TYPE_CFG1 (0x5 << 0) | 55 | #define PCIE_ATU_TYPE_CFG1 (0x5 << 0) |
56 | #define PCIE_ATU_CR2 0x908 | 56 | #define PCIE_ATU_CR2 0x908 |
57 | #define PCIE_ATU_ENABLE (0x1 << 31) | 57 | #define PCIE_ATU_ENABLE (0x1 << 31) |
58 | #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) | 58 | #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) |
59 | #define PCIE_ATU_LOWER_BASE 0x90C | 59 | #define PCIE_ATU_LOWER_BASE 0x90C |
60 | #define PCIE_ATU_UPPER_BASE 0x910 | 60 | #define PCIE_ATU_UPPER_BASE 0x910 |
61 | #define PCIE_ATU_LIMIT 0x914 | 61 | #define PCIE_ATU_LIMIT 0x914 |
62 | #define PCIE_ATU_LOWER_TARGET 0x918 | 62 | #define PCIE_ATU_LOWER_TARGET 0x918 |
63 | #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) | 63 | #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) |
64 | #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) | 64 | #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) |
65 | #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) | 65 | #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) |
66 | #define PCIE_ATU_UPPER_TARGET 0x91C | 66 | #define PCIE_ATU_UPPER_TARGET 0x91C |
67 | 67 | ||
68 | static struct hw_pci dw_pci; | 68 | static struct hw_pci dw_pci; |
69 | 69 | ||
70 | static unsigned long global_io_offset; | 70 | static unsigned long global_io_offset; |
71 | 71 | ||
72 | static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys) | 72 | static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys) |
73 | { | 73 | { |
74 | return sys->private_data; | 74 | return sys->private_data; |
75 | } | 75 | } |
76 | 76 | ||
77 | int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val) | 77 | int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val) |
78 | { | 78 | { |
79 | *val = readl(addr); | 79 | *val = readl(addr); |
80 | 80 | ||
81 | if (size == 1) | 81 | if (size == 1) |
82 | *val = (*val >> (8 * (where & 3))) & 0xff; | 82 | *val = (*val >> (8 * (where & 3))) & 0xff; |
83 | else if (size == 2) | 83 | else if (size == 2) |
84 | *val = (*val >> (8 * (where & 3))) & 0xffff; | 84 | *val = (*val >> (8 * (where & 3))) & 0xffff; |
85 | else if (size != 4) | 85 | else if (size != 4) |
86 | return PCIBIOS_BAD_REGISTER_NUMBER; | 86 | return PCIBIOS_BAD_REGISTER_NUMBER; |
87 | 87 | ||
88 | return PCIBIOS_SUCCESSFUL; | 88 | return PCIBIOS_SUCCESSFUL; |
89 | } | 89 | } |
90 | 90 | ||
91 | int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val) | 91 | int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val) |
92 | { | 92 | { |
93 | if (size == 4) | 93 | if (size == 4) |
94 | writel(val, addr); | 94 | writel(val, addr); |
95 | else if (size == 2) | 95 | else if (size == 2) |
96 | writew(val, addr + (where & 2)); | 96 | writew(val, addr + (where & 2)); |
97 | else if (size == 1) | 97 | else if (size == 1) |
98 | writeb(val, addr + (where & 3)); | 98 | writeb(val, addr + (where & 3)); |
99 | else | 99 | else |
100 | return PCIBIOS_BAD_REGISTER_NUMBER; | 100 | return PCIBIOS_BAD_REGISTER_NUMBER; |
101 | 101 | ||
102 | return PCIBIOS_SUCCESSFUL; | 102 | return PCIBIOS_SUCCESSFUL; |
103 | } | 103 | } |
104 | 104 | ||
105 | static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val) | 105 | static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val) |
106 | { | 106 | { |
107 | if (pp->ops->readl_rc) | 107 | if (pp->ops->readl_rc) |
108 | pp->ops->readl_rc(pp, pp->dbi_base + reg, val); | 108 | pp->ops->readl_rc(pp, pp->dbi_base + reg, val); |
109 | else | 109 | else |
110 | *val = readl(pp->dbi_base + reg); | 110 | *val = readl(pp->dbi_base + reg); |
111 | } | 111 | } |
112 | 112 | ||
113 | static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg) | 113 | static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg) |
114 | { | 114 | { |
115 | if (pp->ops->writel_rc) | 115 | if (pp->ops->writel_rc) |
116 | pp->ops->writel_rc(pp, val, pp->dbi_base + reg); | 116 | pp->ops->writel_rc(pp, val, pp->dbi_base + reg); |
117 | else | 117 | else |
118 | writel(val, pp->dbi_base + reg); | 118 | writel(val, pp->dbi_base + reg); |
119 | } | 119 | } |
120 | 120 | ||
121 | static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, | 121 | static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, |
122 | u32 *val) | 122 | u32 *val) |
123 | { | 123 | { |
124 | int ret; | 124 | int ret; |
125 | 125 | ||
126 | if (pp->ops->rd_own_conf) | 126 | if (pp->ops->rd_own_conf) |
127 | ret = pp->ops->rd_own_conf(pp, where, size, val); | 127 | ret = pp->ops->rd_own_conf(pp, where, size, val); |
128 | else | 128 | else |
129 | ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, | 129 | ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, |
130 | size, val); | 130 | size, val); |
131 | 131 | ||
132 | return ret; | 132 | return ret; |
133 | } | 133 | } |
134 | 134 | ||
135 | static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, | 135 | static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, |
136 | u32 val) | 136 | u32 val) |
137 | { | 137 | { |
138 | int ret; | 138 | int ret; |
139 | 139 | ||
140 | if (pp->ops->wr_own_conf) | 140 | if (pp->ops->wr_own_conf) |
141 | ret = pp->ops->wr_own_conf(pp, where, size, val); | 141 | ret = pp->ops->wr_own_conf(pp, where, size, val); |
142 | else | 142 | else |
143 | ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where, | 143 | ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where, |
144 | size, val); | 144 | size, val); |
145 | 145 | ||
146 | return ret; | 146 | return ret; |
147 | } | 147 | } |
148 | 148 | ||
149 | static struct irq_chip dw_msi_irq_chip = { | 149 | static struct irq_chip dw_msi_irq_chip = { |
150 | .name = "PCI-MSI", | 150 | .name = "PCI-MSI", |
151 | .irq_enable = unmask_msi_irq, | 151 | .irq_enable = unmask_msi_irq, |
152 | .irq_disable = mask_msi_irq, | 152 | .irq_disable = mask_msi_irq, |
153 | .irq_mask = mask_msi_irq, | 153 | .irq_mask = mask_msi_irq, |
154 | .irq_unmask = unmask_msi_irq, | 154 | .irq_unmask = unmask_msi_irq, |
155 | }; | 155 | }; |
156 | 156 | ||
157 | /* MSI int handler */ | 157 | /* MSI int handler */ |
158 | void dw_handle_msi_irq(struct pcie_port *pp) | 158 | void dw_handle_msi_irq(struct pcie_port *pp) |
159 | { | 159 | { |
160 | unsigned long val; | 160 | unsigned long val; |
161 | int i, pos, irq; | 161 | int i, pos, irq; |
162 | 162 | ||
163 | for (i = 0; i < MAX_MSI_CTRLS; i++) { | 163 | for (i = 0; i < MAX_MSI_CTRLS; i++) { |
164 | dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4, | 164 | dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4, |
165 | (u32 *)&val); | 165 | (u32 *)&val); |
166 | if (val) { | 166 | if (val) { |
167 | pos = 0; | 167 | pos = 0; |
168 | while ((pos = find_next_bit(&val, 32, pos)) != 32) { | 168 | while ((pos = find_next_bit(&val, 32, pos)) != 32) { |
169 | irq = irq_find_mapping(pp->irq_domain, | 169 | irq = irq_find_mapping(pp->irq_domain, |
170 | i * 32 + pos); | 170 | i * 32 + pos); |
171 | dw_pcie_wr_own_conf(pp, | 171 | dw_pcie_wr_own_conf(pp, |
172 | PCIE_MSI_INTR0_STATUS + i * 12, | 172 | PCIE_MSI_INTR0_STATUS + i * 12, |
173 | 4, 1 << pos); | 173 | 4, 1 << pos); |
174 | generic_handle_irq(irq); | 174 | generic_handle_irq(irq); |
175 | pos++; | 175 | pos++; |
176 | } | 176 | } |
177 | } | 177 | } |
178 | } | 178 | } |
179 | } | 179 | } |
180 | 180 | ||
181 | void dw_pcie_msi_init(struct pcie_port *pp) | 181 | void dw_pcie_msi_init(struct pcie_port *pp) |
182 | { | 182 | { |
183 | pp->msi_data = __get_free_pages(GFP_KERNEL, 0); | 183 | pp->msi_data = __get_free_pages(GFP_KERNEL, 0); |
184 | 184 | ||
185 | /* program the msi_data */ | 185 | /* program the msi_data */ |
186 | dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4, | 186 | dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4, |
187 | virt_to_phys((void *)pp->msi_data)); | 187 | virt_to_phys((void *)pp->msi_data)); |
188 | dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0); | 188 | dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0); |
189 | } | 189 | } |
190 | 190 | ||
191 | static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0) | 191 | static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0) |
192 | { | 192 | { |
193 | int flag = 1; | 193 | int flag = 1; |
194 | 194 | ||
195 | do { | 195 | do { |
196 | pos = find_next_zero_bit(pp->msi_irq_in_use, | 196 | pos = find_next_zero_bit(pp->msi_irq_in_use, |
197 | MAX_MSI_IRQS, pos); | 197 | MAX_MSI_IRQS, pos); |
198 | /*if you have reached to the end then get out from here.*/ | 198 | /*if you have reached to the end then get out from here.*/ |
199 | if (pos == MAX_MSI_IRQS) | 199 | if (pos == MAX_MSI_IRQS) |
200 | return -ENOSPC; | 200 | return -ENOSPC; |
201 | /* | 201 | /* |
202 | * Check if this position is at correct offset.nvec is always a | 202 | * Check if this position is at correct offset.nvec is always a |
203 | * power of two. pos0 must be nvec bit aligned. | 203 | * power of two. pos0 must be nvec bit aligned. |
204 | */ | 204 | */ |
205 | if (pos % msgvec) | 205 | if (pos % msgvec) |
206 | pos += msgvec - (pos % msgvec); | 206 | pos += msgvec - (pos % msgvec); |
207 | else | 207 | else |
208 | flag = 0; | 208 | flag = 0; |
209 | } while (flag); | 209 | } while (flag); |
210 | 210 | ||
211 | *pos0 = pos; | 211 | *pos0 = pos; |
212 | return 0; | 212 | return 0; |
213 | } | 213 | } |
214 | 214 | ||
215 | static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base, | 215 | static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base, |
216 | unsigned int nvec, unsigned int pos) | 216 | unsigned int nvec, unsigned int pos) |
217 | { | 217 | { |
218 | unsigned int i, res, bit, val; | 218 | unsigned int i, res, bit, val; |
219 | 219 | ||
220 | for (i = 0; i < nvec; i++) { | 220 | for (i = 0; i < nvec; i++) { |
221 | irq_set_msi_desc_off(irq_base, i, NULL); | 221 | irq_set_msi_desc_off(irq_base, i, NULL); |
222 | clear_bit(pos + i, pp->msi_irq_in_use); | 222 | clear_bit(pos + i, pp->msi_irq_in_use); |
223 | /* Disable corresponding interrupt on MSI controller */ | 223 | /* Disable corresponding interrupt on MSI controller */ |
224 | res = ((pos + i) / 32) * 12; | 224 | res = ((pos + i) / 32) * 12; |
225 | bit = (pos + i) % 32; | 225 | bit = (pos + i) % 32; |
226 | dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); | 226 | dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); |
227 | val &= ~(1 << bit); | 227 | val &= ~(1 << bit); |
228 | dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val); | 228 | dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val); |
229 | } | 229 | } |
230 | } | 230 | } |
231 | 231 | ||
232 | static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos) | 232 | static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos) |
233 | { | 233 | { |
234 | int res, bit, irq, pos0, pos1, i; | 234 | int res, bit, irq, pos0, pos1, i; |
235 | u32 val; | 235 | u32 val; |
236 | struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata); | 236 | struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata); |
237 | 237 | ||
238 | if (!pp) { | 238 | if (!pp) { |
239 | BUG(); | 239 | BUG(); |
240 | return -EINVAL; | 240 | return -EINVAL; |
241 | } | 241 | } |
242 | 242 | ||
243 | pos0 = find_first_zero_bit(pp->msi_irq_in_use, | 243 | pos0 = find_first_zero_bit(pp->msi_irq_in_use, |
244 | MAX_MSI_IRQS); | 244 | MAX_MSI_IRQS); |
245 | if (pos0 % no_irqs) { | 245 | if (pos0 % no_irqs) { |
246 | if (find_valid_pos0(pp, no_irqs, pos0, &pos0)) | 246 | if (find_valid_pos0(pp, no_irqs, pos0, &pos0)) |
247 | goto no_valid_irq; | 247 | goto no_valid_irq; |
248 | } | 248 | } |
249 | if (no_irqs > 1) { | 249 | if (no_irqs > 1) { |
250 | pos1 = find_next_bit(pp->msi_irq_in_use, | 250 | pos1 = find_next_bit(pp->msi_irq_in_use, |
251 | MAX_MSI_IRQS, pos0); | 251 | MAX_MSI_IRQS, pos0); |
252 | /* there must be nvec number of consecutive free bits */ | 252 | /* there must be nvec number of consecutive free bits */ |
253 | while ((pos1 - pos0) < no_irqs) { | 253 | while ((pos1 - pos0) < no_irqs) { |
254 | if (find_valid_pos0(pp, no_irqs, pos1, &pos0)) | 254 | if (find_valid_pos0(pp, no_irqs, pos1, &pos0)) |
255 | goto no_valid_irq; | 255 | goto no_valid_irq; |
256 | pos1 = find_next_bit(pp->msi_irq_in_use, | 256 | pos1 = find_next_bit(pp->msi_irq_in_use, |
257 | MAX_MSI_IRQS, pos0); | 257 | MAX_MSI_IRQS, pos0); |
258 | } | 258 | } |
259 | } | 259 | } |
260 | 260 | ||
261 | irq = irq_find_mapping(pp->irq_domain, pos0); | 261 | irq = irq_find_mapping(pp->irq_domain, pos0); |
262 | if (!irq) | 262 | if (!irq) |
263 | goto no_valid_irq; | 263 | goto no_valid_irq; |
264 | 264 | ||
265 | /* | 265 | /* |
266 | * irq_create_mapping (called from dw_pcie_host_init) pre-allocates | 266 | * irq_create_mapping (called from dw_pcie_host_init) pre-allocates |
267 | * descs so there is no need to allocate descs here. We can therefore | 267 | * descs so there is no need to allocate descs here. We can therefore |
268 | * assume that if irq_find_mapping above returns non-zero, then the | 268 | * assume that if irq_find_mapping above returns non-zero, then the |
269 | * descs are also successfully allocated. | 269 | * descs are also successfully allocated. |
270 | */ | 270 | */ |
271 | 271 | ||
272 | for (i = 0; i < no_irqs; i++) { | 272 | for (i = 0; i < no_irqs; i++) { |
273 | if (irq_set_msi_desc_off(irq, i, desc) != 0) { | 273 | if (irq_set_msi_desc_off(irq, i, desc) != 0) { |
274 | clear_irq_range(pp, irq, i, pos0); | 274 | clear_irq_range(pp, irq, i, pos0); |
275 | goto no_valid_irq; | 275 | goto no_valid_irq; |
276 | } | 276 | } |
277 | set_bit(pos0 + i, pp->msi_irq_in_use); | 277 | set_bit(pos0 + i, pp->msi_irq_in_use); |
278 | /*Enable corresponding interrupt in MSI interrupt controller */ | 278 | /*Enable corresponding interrupt in MSI interrupt controller */ |
279 | res = ((pos0 + i) / 32) * 12; | 279 | res = ((pos0 + i) / 32) * 12; |
280 | bit = (pos0 + i) % 32; | 280 | bit = (pos0 + i) % 32; |
281 | dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); | 281 | dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); |
282 | val |= 1 << bit; | 282 | val |= 1 << bit; |
283 | dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val); | 283 | dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val); |
284 | } | 284 | } |
285 | 285 | ||
286 | *pos = pos0; | 286 | *pos = pos0; |
287 | return irq; | 287 | return irq; |
288 | 288 | ||
289 | no_valid_irq: | 289 | no_valid_irq: |
290 | *pos = pos0; | 290 | *pos = pos0; |
291 | return -ENOSPC; | 291 | return -ENOSPC; |
292 | } | 292 | } |
293 | 293 | ||
294 | static void clear_irq(unsigned int irq) | 294 | static void clear_irq(unsigned int irq) |
295 | { | 295 | { |
296 | unsigned int pos, nvec; | 296 | unsigned int pos, nvec; |
297 | struct irq_desc *desc; | 297 | struct irq_desc *desc; |
298 | struct msi_desc *msi; | 298 | struct msi_desc *msi; |
299 | struct pcie_port *pp; | 299 | struct pcie_port *pp; |
300 | struct irq_data *data = irq_get_irq_data(irq); | 300 | struct irq_data *data = irq_get_irq_data(irq); |
301 | 301 | ||
302 | /* get the port structure */ | 302 | /* get the port structure */ |
303 | desc = irq_to_desc(irq); | 303 | desc = irq_to_desc(irq); |
304 | msi = irq_desc_get_msi_desc(desc); | 304 | msi = irq_desc_get_msi_desc(desc); |
305 | pp = sys_to_pcie(msi->dev->bus->sysdata); | 305 | pp = sys_to_pcie(msi->dev->bus->sysdata); |
306 | if (!pp) { | 306 | if (!pp) { |
307 | BUG(); | 307 | BUG(); |
308 | return; | 308 | return; |
309 | } | 309 | } |
310 | 310 | ||
311 | /* undo what was done in assign_irq */ | 311 | /* undo what was done in assign_irq */ |
312 | pos = data->hwirq; | 312 | pos = data->hwirq; |
313 | nvec = 1 << msi->msi_attrib.multiple; | 313 | nvec = 1 << msi->msi_attrib.multiple; |
314 | 314 | ||
315 | clear_irq_range(pp, irq, nvec, pos); | 315 | clear_irq_range(pp, irq, nvec, pos); |
316 | 316 | ||
317 | /* all irqs cleared; reset attributes */ | 317 | /* all irqs cleared; reset attributes */ |
318 | msi->irq = 0; | 318 | msi->irq = 0; |
319 | msi->msi_attrib.multiple = 0; | 319 | msi->msi_attrib.multiple = 0; |
320 | } | 320 | } |
321 | 321 | ||
322 | static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev, | 322 | static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev, |
323 | struct msi_desc *desc) | 323 | struct msi_desc *desc) |
324 | { | 324 | { |
325 | int irq, pos, msgvec; | 325 | int irq, pos, msgvec; |
326 | u16 msg_ctr; | 326 | u16 msg_ctr; |
327 | struct msi_msg msg; | 327 | struct msi_msg msg; |
328 | struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata); | 328 | struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata); |
329 | 329 | ||
330 | if (!pp) { | 330 | if (!pp) { |
331 | BUG(); | 331 | BUG(); |
332 | return -EINVAL; | 332 | return -EINVAL; |
333 | } | 333 | } |
334 | 334 | ||
335 | pci_read_config_word(pdev, desc->msi_attrib.pos+PCI_MSI_FLAGS, | 335 | pci_read_config_word(pdev, desc->msi_attrib.pos+PCI_MSI_FLAGS, |
336 | &msg_ctr); | 336 | &msg_ctr); |
337 | msgvec = (msg_ctr&PCI_MSI_FLAGS_QSIZE) >> 4; | 337 | msgvec = (msg_ctr&PCI_MSI_FLAGS_QSIZE) >> 4; |
338 | if (msgvec == 0) | 338 | if (msgvec == 0) |
339 | msgvec = (msg_ctr & PCI_MSI_FLAGS_QMASK) >> 1; | 339 | msgvec = (msg_ctr & PCI_MSI_FLAGS_QMASK) >> 1; |
340 | if (msgvec > 5) | 340 | if (msgvec > 5) |
341 | msgvec = 0; | 341 | msgvec = 0; |
342 | 342 | ||
343 | irq = assign_irq((1 << msgvec), desc, &pos); | 343 | irq = assign_irq((1 << msgvec), desc, &pos); |
344 | if (irq < 0) | 344 | if (irq < 0) |
345 | return irq; | 345 | return irq; |
346 | 346 | ||
347 | /* | 347 | /* |
348 | * write_msi_msg() will update PCI_MSI_FLAGS so there is | 348 | * write_msi_msg() will update PCI_MSI_FLAGS so there is |
349 | * no need to explicitly call pci_write_config_word(). | 349 | * no need to explicitly call pci_write_config_word(). |
350 | */ | 350 | */ |
351 | desc->msi_attrib.multiple = msgvec; | 351 | desc->msi_attrib.multiple = msgvec; |
352 | 352 | ||
353 | msg.address_lo = virt_to_phys((void *)pp->msi_data); | 353 | msg.address_lo = virt_to_phys((void *)pp->msi_data); |
354 | msg.address_hi = 0x0; | 354 | msg.address_hi = 0x0; |
355 | msg.data = pos; | 355 | msg.data = pos; |
356 | write_msi_msg(irq, &msg); | 356 | write_msi_msg(irq, &msg); |
357 | 357 | ||
358 | return 0; | 358 | return 0; |
359 | } | 359 | } |
360 | 360 | ||
361 | static void dw_msi_teardown_irq(struct msi_chip *chip, unsigned int irq) | 361 | static void dw_msi_teardown_irq(struct msi_chip *chip, unsigned int irq) |
362 | { | 362 | { |
363 | clear_irq(irq); | 363 | clear_irq(irq); |
364 | } | 364 | } |
365 | 365 | ||
366 | static struct msi_chip dw_pcie_msi_chip = { | 366 | static struct msi_chip dw_pcie_msi_chip = { |
367 | .setup_irq = dw_msi_setup_irq, | 367 | .setup_irq = dw_msi_setup_irq, |
368 | .teardown_irq = dw_msi_teardown_irq, | 368 | .teardown_irq = dw_msi_teardown_irq, |
369 | }; | 369 | }; |
370 | 370 | ||
371 | int dw_pcie_link_up(struct pcie_port *pp) | 371 | int dw_pcie_link_up(struct pcie_port *pp) |
372 | { | 372 | { |
373 | if (pp->ops->link_up) | 373 | if (pp->ops->link_up) |
374 | return pp->ops->link_up(pp); | 374 | return pp->ops->link_up(pp); |
375 | else | 375 | else |
376 | return 0; | 376 | return 0; |
377 | } | 377 | } |
378 | 378 | ||
379 | static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq, | 379 | static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq, |
380 | irq_hw_number_t hwirq) | 380 | irq_hw_number_t hwirq) |
381 | { | 381 | { |
382 | irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq); | 382 | irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq); |
383 | irq_set_chip_data(irq, domain->host_data); | 383 | irq_set_chip_data(irq, domain->host_data); |
384 | set_irq_flags(irq, IRQF_VALID); | 384 | set_irq_flags(irq, IRQF_VALID); |
385 | 385 | ||
386 | return 0; | 386 | return 0; |
387 | } | 387 | } |
388 | 388 | ||
389 | static const struct irq_domain_ops msi_domain_ops = { | 389 | static const struct irq_domain_ops msi_domain_ops = { |
390 | .map = dw_pcie_msi_map, | 390 | .map = dw_pcie_msi_map, |
391 | }; | 391 | }; |
392 | 392 | ||
393 | int __init dw_pcie_host_init(struct pcie_port *pp) | 393 | int __init dw_pcie_host_init(struct pcie_port *pp) |
394 | { | 394 | { |
395 | struct device_node *np = pp->dev->of_node; | 395 | struct device_node *np = pp->dev->of_node; |
396 | struct of_pci_range range; | 396 | struct of_pci_range range; |
397 | struct of_pci_range_parser parser; | 397 | struct of_pci_range_parser parser; |
398 | u32 val; | 398 | u32 val; |
399 | int i; | 399 | int i; |
400 | 400 | ||
401 | if (of_pci_range_parser_init(&parser, np)) { | 401 | if (of_pci_range_parser_init(&parser, np)) { |
402 | dev_err(pp->dev, "missing ranges property\n"); | 402 | dev_err(pp->dev, "missing ranges property\n"); |
403 | return -EINVAL; | 403 | return -EINVAL; |
404 | } | 404 | } |
405 | 405 | ||
406 | /* Get the I/O and memory ranges from DT */ | 406 | /* Get the I/O and memory ranges from DT */ |
407 | for_each_of_pci_range(&parser, &range) { | 407 | for_each_of_pci_range(&parser, &range) { |
408 | unsigned long restype = range.flags & IORESOURCE_TYPE_BITS; | 408 | unsigned long restype = range.flags & IORESOURCE_TYPE_BITS; |
409 | if (restype == IORESOURCE_IO) { | 409 | if (restype == IORESOURCE_IO) { |
410 | of_pci_range_to_resource(&range, np, &pp->io); | 410 | of_pci_range_to_resource(&range, np, &pp->io); |
411 | pp->io.name = "I/O"; | 411 | pp->io.name = "I/O"; |
412 | pp->io.start = max_t(resource_size_t, | 412 | pp->io.start = max_t(resource_size_t, |
413 | PCIBIOS_MIN_IO, | 413 | PCIBIOS_MIN_IO, |
414 | range.pci_addr + global_io_offset); | 414 | range.pci_addr + global_io_offset); |
415 | pp->io.end = min_t(resource_size_t, | 415 | pp->io.end = min_t(resource_size_t, |
416 | IO_SPACE_LIMIT, | 416 | IO_SPACE_LIMIT, |
417 | range.pci_addr + range.size | 417 | range.pci_addr + range.size |
418 | + global_io_offset); | 418 | + global_io_offset); |
419 | pp->config.io_size = resource_size(&pp->io); | 419 | pp->config.io_size = resource_size(&pp->io); |
420 | pp->config.io_bus_addr = range.pci_addr; | 420 | pp->config.io_bus_addr = range.pci_addr; |
421 | pp->io_base = range.cpu_addr; | 421 | pp->io_base = range.cpu_addr; |
422 | } | 422 | } |
423 | if (restype == IORESOURCE_MEM) { | 423 | if (restype == IORESOURCE_MEM) { |
424 | of_pci_range_to_resource(&range, np, &pp->mem); | 424 | of_pci_range_to_resource(&range, np, &pp->mem); |
425 | pp->mem.name = "MEM"; | 425 | pp->mem.name = "MEM"; |
426 | pp->config.mem_size = resource_size(&pp->mem); | 426 | pp->config.mem_size = resource_size(&pp->mem); |
427 | pp->config.mem_bus_addr = range.pci_addr; | 427 | pp->config.mem_bus_addr = range.pci_addr; |
428 | } | 428 | } |
429 | if (restype == 0) { | 429 | if (restype == 0) { |
430 | of_pci_range_to_resource(&range, np, &pp->cfg); | 430 | of_pci_range_to_resource(&range, np, &pp->cfg); |
431 | pp->config.cfg0_size = resource_size(&pp->cfg)/2; | 431 | pp->config.cfg0_size = resource_size(&pp->cfg)/2; |
432 | pp->config.cfg1_size = resource_size(&pp->cfg)/2; | 432 | pp->config.cfg1_size = resource_size(&pp->cfg)/2; |
433 | } | 433 | } |
434 | } | 434 | } |
435 | 435 | ||
436 | if (!pp->dbi_base) { | 436 | if (!pp->dbi_base) { |
437 | pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start, | 437 | pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start, |
438 | resource_size(&pp->cfg)); | 438 | resource_size(&pp->cfg)); |
439 | if (!pp->dbi_base) { | 439 | if (!pp->dbi_base) { |
440 | dev_err(pp->dev, "error with ioremap\n"); | 440 | dev_err(pp->dev, "error with ioremap\n"); |
441 | return -ENOMEM; | 441 | return -ENOMEM; |
442 | } | 442 | } |
443 | } | 443 | } |
444 | 444 | ||
445 | pp->cfg0_base = pp->cfg.start; | 445 | pp->cfg0_base = pp->cfg.start; |
446 | pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size; | 446 | pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size; |
447 | pp->mem_base = pp->mem.start; | 447 | pp->mem_base = pp->mem.start; |
448 | 448 | ||
449 | pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base, | 449 | pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base, |
450 | pp->config.cfg0_size); | 450 | pp->config.cfg0_size); |
451 | if (!pp->va_cfg0_base) { | 451 | if (!pp->va_cfg0_base) { |
452 | dev_err(pp->dev, "error with ioremap in function\n"); | 452 | dev_err(pp->dev, "error with ioremap in function\n"); |
453 | return -ENOMEM; | 453 | return -ENOMEM; |
454 | } | 454 | } |
455 | pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base, | 455 | pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base, |
456 | pp->config.cfg1_size); | 456 | pp->config.cfg1_size); |
457 | if (!pp->va_cfg1_base) { | 457 | if (!pp->va_cfg1_base) { |
458 | dev_err(pp->dev, "error with ioremap\n"); | 458 | dev_err(pp->dev, "error with ioremap\n"); |
459 | return -ENOMEM; | 459 | return -ENOMEM; |
460 | } | 460 | } |
461 | 461 | ||
462 | if (of_property_read_u32(np, "num-lanes", &pp->lanes)) { | 462 | if (of_property_read_u32(np, "num-lanes", &pp->lanes)) { |
463 | dev_err(pp->dev, "Failed to parse the number of lanes\n"); | 463 | dev_err(pp->dev, "Failed to parse the number of lanes\n"); |
464 | return -EINVAL; | 464 | return -EINVAL; |
465 | } | 465 | } |
466 | 466 | ||
467 | if (IS_ENABLED(CONFIG_PCI_MSI)) { | 467 | if (IS_ENABLED(CONFIG_PCI_MSI)) { |
468 | pp->irq_domain = irq_domain_add_linear(pp->dev->of_node, | 468 | pp->irq_domain = irq_domain_add_linear(pp->dev->of_node, |
469 | MAX_MSI_IRQS, &msi_domain_ops, | 469 | MAX_MSI_IRQS, &msi_domain_ops, |
470 | &dw_pcie_msi_chip); | 470 | &dw_pcie_msi_chip); |
471 | if (!pp->irq_domain) { | 471 | if (!pp->irq_domain) { |
472 | dev_err(pp->dev, "irq domain init failed\n"); | 472 | dev_err(pp->dev, "irq domain init failed\n"); |
473 | return -ENXIO; | 473 | return -ENXIO; |
474 | } | 474 | } |
475 | 475 | ||
476 | for (i = 0; i < MAX_MSI_IRQS; i++) | 476 | for (i = 0; i < MAX_MSI_IRQS; i++) |
477 | irq_create_mapping(pp->irq_domain, i); | 477 | irq_create_mapping(pp->irq_domain, i); |
478 | } | 478 | } |
479 | 479 | ||
480 | if (pp->ops->host_init) | 480 | if (pp->ops->host_init) |
481 | pp->ops->host_init(pp); | 481 | pp->ops->host_init(pp); |
482 | 482 | ||
483 | dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); | 483 | dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); |
484 | 484 | ||
485 | /* program correct class for RC */ | 485 | /* program correct class for RC */ |
486 | dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); | 486 | dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); |
487 | 487 | ||
488 | dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); | 488 | dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); |
489 | val |= PORT_LOGIC_SPEED_CHANGE; | 489 | val |= PORT_LOGIC_SPEED_CHANGE; |
490 | dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); | 490 | dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); |
491 | 491 | ||
492 | dw_pci.nr_controllers = 1; | 492 | dw_pci.nr_controllers = 1; |
493 | dw_pci.private_data = (void **)&pp; | 493 | dw_pci.private_data = (void **)&pp; |
494 | 494 | ||
495 | pci_common_init(&dw_pci); | 495 | pci_common_init(&dw_pci); |
496 | pci_assign_unassigned_resources(); | 496 | pci_assign_unassigned_resources(); |
497 | #ifdef CONFIG_PCI_DOMAINS | 497 | #ifdef CONFIG_PCI_DOMAINS |
498 | dw_pci.domain++; | 498 | dw_pci.domain++; |
499 | #endif | 499 | #endif |
500 | 500 | ||
501 | return 0; | 501 | return 0; |
502 | } | 502 | } |
503 | 503 | ||
504 | static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev) | 504 | static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev) |
505 | { | 505 | { |
506 | /* Program viewport 0 : OUTBOUND : CFG0 */ | 506 | /* Program viewport 0 : OUTBOUND : CFG0 */ |
507 | dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0, | 507 | dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0, |
508 | PCIE_ATU_VIEWPORT); | 508 | PCIE_ATU_VIEWPORT); |
509 | dw_pcie_writel_rc(pp, pp->cfg0_base, PCIE_ATU_LOWER_BASE); | 509 | dw_pcie_writel_rc(pp, pp->cfg0_base, PCIE_ATU_LOWER_BASE); |
510 | dw_pcie_writel_rc(pp, (pp->cfg0_base >> 32), PCIE_ATU_UPPER_BASE); | 510 | dw_pcie_writel_rc(pp, (pp->cfg0_base >> 32), PCIE_ATU_UPPER_BASE); |
511 | dw_pcie_writel_rc(pp, pp->cfg0_base + pp->config.cfg0_size - 1, | 511 | dw_pcie_writel_rc(pp, pp->cfg0_base + pp->config.cfg0_size - 1, |
512 | PCIE_ATU_LIMIT); | 512 | PCIE_ATU_LIMIT); |
513 | dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET); | 513 | dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET); |
514 | dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET); | 514 | dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET); |
515 | dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG0, PCIE_ATU_CR1); | 515 | dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG0, PCIE_ATU_CR1); |
516 | dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); | 516 | dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); |
517 | } | 517 | } |
518 | 518 | ||
519 | static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev) | 519 | static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev) |
520 | { | 520 | { |
521 | /* Program viewport 1 : OUTBOUND : CFG1 */ | 521 | /* Program viewport 1 : OUTBOUND : CFG1 */ |
522 | dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1, | 522 | dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1, |
523 | PCIE_ATU_VIEWPORT); | 523 | PCIE_ATU_VIEWPORT); |
524 | dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1); | 524 | dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1); |
525 | dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); | ||
526 | dw_pcie_writel_rc(pp, pp->cfg1_base, PCIE_ATU_LOWER_BASE); | 525 | dw_pcie_writel_rc(pp, pp->cfg1_base, PCIE_ATU_LOWER_BASE); |
527 | dw_pcie_writel_rc(pp, (pp->cfg1_base >> 32), PCIE_ATU_UPPER_BASE); | 526 | dw_pcie_writel_rc(pp, (pp->cfg1_base >> 32), PCIE_ATU_UPPER_BASE); |
528 | dw_pcie_writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1, | 527 | dw_pcie_writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1, |
529 | PCIE_ATU_LIMIT); | 528 | PCIE_ATU_LIMIT); |
530 | dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET); | 529 | dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET); |
531 | dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET); | 530 | dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET); |
531 | dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); | ||
532 | } | 532 | } |
533 | 533 | ||
534 | static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp) | 534 | static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp) |
535 | { | 535 | { |
536 | /* Program viewport 0 : OUTBOUND : MEM */ | 536 | /* Program viewport 0 : OUTBOUND : MEM */ |
537 | dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0, | 537 | dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0, |
538 | PCIE_ATU_VIEWPORT); | 538 | PCIE_ATU_VIEWPORT); |
539 | dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1); | 539 | dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1); |
540 | dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); | ||
541 | dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE); | 540 | dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE); |
542 | dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE); | 541 | dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE); |
543 | dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1, | 542 | dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1, |
544 | PCIE_ATU_LIMIT); | 543 | PCIE_ATU_LIMIT); |
545 | dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET); | 544 | dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET); |
546 | dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr), | 545 | dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr), |
547 | PCIE_ATU_UPPER_TARGET); | 546 | PCIE_ATU_UPPER_TARGET); |
547 | dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); | ||
548 | } | 548 | } |
549 | 549 | ||
550 | static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp) | 550 | static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp) |
551 | { | 551 | { |
552 | /* Program viewport 1 : OUTBOUND : IO */ | 552 | /* Program viewport 1 : OUTBOUND : IO */ |
553 | dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1, | 553 | dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1, |
554 | PCIE_ATU_VIEWPORT); | 554 | PCIE_ATU_VIEWPORT); |
555 | dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1); | 555 | dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1); |
556 | dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); | ||
557 | dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE); | 556 | dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE); |
558 | dw_pcie_writel_rc(pp, (pp->io_base >> 32), PCIE_ATU_UPPER_BASE); | 557 | dw_pcie_writel_rc(pp, (pp->io_base >> 32), PCIE_ATU_UPPER_BASE); |
559 | dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1, | 558 | dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1, |
560 | PCIE_ATU_LIMIT); | 559 | PCIE_ATU_LIMIT); |
561 | dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET); | 560 | dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET); |
562 | dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr), | 561 | dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr), |
563 | PCIE_ATU_UPPER_TARGET); | 562 | PCIE_ATU_UPPER_TARGET); |
563 | dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); | ||
564 | } | 564 | } |
565 | 565 | ||
566 | static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, | 566 | static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, |
567 | u32 devfn, int where, int size, u32 *val) | 567 | u32 devfn, int where, int size, u32 *val) |
568 | { | 568 | { |
569 | int ret = PCIBIOS_SUCCESSFUL; | 569 | int ret = PCIBIOS_SUCCESSFUL; |
570 | u32 address, busdev; | 570 | u32 address, busdev; |
571 | 571 | ||
572 | busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | | 572 | busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | |
573 | PCIE_ATU_FUNC(PCI_FUNC(devfn)); | 573 | PCIE_ATU_FUNC(PCI_FUNC(devfn)); |
574 | address = where & ~0x3; | 574 | address = where & ~0x3; |
575 | 575 | ||
576 | if (bus->parent->number == pp->root_bus_nr) { | 576 | if (bus->parent->number == pp->root_bus_nr) { |
577 | dw_pcie_prog_viewport_cfg0(pp, busdev); | 577 | dw_pcie_prog_viewport_cfg0(pp, busdev); |
578 | ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size, | 578 | ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size, |
579 | val); | 579 | val); |
580 | dw_pcie_prog_viewport_mem_outbound(pp); | 580 | dw_pcie_prog_viewport_mem_outbound(pp); |
581 | } else { | 581 | } else { |
582 | dw_pcie_prog_viewport_cfg1(pp, busdev); | 582 | dw_pcie_prog_viewport_cfg1(pp, busdev); |
583 | ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size, | 583 | ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size, |
584 | val); | 584 | val); |
585 | dw_pcie_prog_viewport_io_outbound(pp); | 585 | dw_pcie_prog_viewport_io_outbound(pp); |
586 | } | 586 | } |
587 | 587 | ||
588 | return ret; | 588 | return ret; |
589 | } | 589 | } |
590 | 590 | ||
591 | static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, | 591 | static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, |
592 | u32 devfn, int where, int size, u32 val) | 592 | u32 devfn, int where, int size, u32 val) |
593 | { | 593 | { |
594 | int ret = PCIBIOS_SUCCESSFUL; | 594 | int ret = PCIBIOS_SUCCESSFUL; |
595 | u32 address, busdev; | 595 | u32 address, busdev; |
596 | 596 | ||
597 | busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | | 597 | busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | |
598 | PCIE_ATU_FUNC(PCI_FUNC(devfn)); | 598 | PCIE_ATU_FUNC(PCI_FUNC(devfn)); |
599 | address = where & ~0x3; | 599 | address = where & ~0x3; |
600 | 600 | ||
601 | if (bus->parent->number == pp->root_bus_nr) { | 601 | if (bus->parent->number == pp->root_bus_nr) { |
602 | dw_pcie_prog_viewport_cfg0(pp, busdev); | 602 | dw_pcie_prog_viewport_cfg0(pp, busdev); |
603 | ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size, | 603 | ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size, |
604 | val); | 604 | val); |
605 | dw_pcie_prog_viewport_mem_outbound(pp); | 605 | dw_pcie_prog_viewport_mem_outbound(pp); |
606 | } else { | 606 | } else { |
607 | dw_pcie_prog_viewport_cfg1(pp, busdev); | 607 | dw_pcie_prog_viewport_cfg1(pp, busdev); |
608 | ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size, | 608 | ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size, |
609 | val); | 609 | val); |
610 | dw_pcie_prog_viewport_io_outbound(pp); | 610 | dw_pcie_prog_viewport_io_outbound(pp); |
611 | } | 611 | } |
612 | 612 | ||
613 | return ret; | 613 | return ret; |
614 | } | 614 | } |
615 | 615 | ||
616 | static int dw_pcie_valid_config(struct pcie_port *pp, | 616 | static int dw_pcie_valid_config(struct pcie_port *pp, |
617 | struct pci_bus *bus, int dev) | 617 | struct pci_bus *bus, int dev) |
618 | { | 618 | { |
619 | /* If there is no link, then there is no device */ | 619 | /* If there is no link, then there is no device */ |
620 | if (bus->number != pp->root_bus_nr) { | 620 | if (bus->number != pp->root_bus_nr) { |
621 | if (!dw_pcie_link_up(pp)) | 621 | if (!dw_pcie_link_up(pp)) |
622 | return 0; | 622 | return 0; |
623 | } | 623 | } |
624 | 624 | ||
625 | /* access only one slot on each root port */ | 625 | /* access only one slot on each root port */ |
626 | if (bus->number == pp->root_bus_nr && dev > 0) | 626 | if (bus->number == pp->root_bus_nr && dev > 0) |
627 | return 0; | 627 | return 0; |
628 | 628 | ||
629 | /* | 629 | /* |
630 | * do not read more than one device on the bus directly attached | 630 | * do not read more than one device on the bus directly attached |
631 | * to RC's (Virtual Bridge's) DS side. | 631 | * to RC's (Virtual Bridge's) DS side. |
632 | */ | 632 | */ |
633 | if (bus->primary == pp->root_bus_nr && dev > 0) | 633 | if (bus->primary == pp->root_bus_nr && dev > 0) |
634 | return 0; | 634 | return 0; |
635 | 635 | ||
636 | return 1; | 636 | return 1; |
637 | } | 637 | } |
638 | 638 | ||
639 | static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, | 639 | static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, |
640 | int size, u32 *val) | 640 | int size, u32 *val) |
641 | { | 641 | { |
642 | struct pcie_port *pp = sys_to_pcie(bus->sysdata); | 642 | struct pcie_port *pp = sys_to_pcie(bus->sysdata); |
643 | unsigned long flags; | 643 | unsigned long flags; |
644 | int ret; | 644 | int ret; |
645 | 645 | ||
646 | if (!pp) { | 646 | if (!pp) { |
647 | BUG(); | 647 | BUG(); |
648 | return -EINVAL; | 648 | return -EINVAL; |
649 | } | 649 | } |
650 | 650 | ||
651 | if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) { | 651 | if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) { |
652 | *val = 0xffffffff; | 652 | *val = 0xffffffff; |
653 | return PCIBIOS_DEVICE_NOT_FOUND; | 653 | return PCIBIOS_DEVICE_NOT_FOUND; |
654 | } | 654 | } |
655 | 655 | ||
656 | spin_lock_irqsave(&pp->conf_lock, flags); | 656 | spin_lock_irqsave(&pp->conf_lock, flags); |
657 | if (bus->number != pp->root_bus_nr) | 657 | if (bus->number != pp->root_bus_nr) |
658 | ret = dw_pcie_rd_other_conf(pp, bus, devfn, | 658 | ret = dw_pcie_rd_other_conf(pp, bus, devfn, |
659 | where, size, val); | 659 | where, size, val); |
660 | else | 660 | else |
661 | ret = dw_pcie_rd_own_conf(pp, where, size, val); | 661 | ret = dw_pcie_rd_own_conf(pp, where, size, val); |
662 | spin_unlock_irqrestore(&pp->conf_lock, flags); | 662 | spin_unlock_irqrestore(&pp->conf_lock, flags); |
663 | 663 | ||
664 | return ret; | 664 | return ret; |
665 | } | 665 | } |
666 | 666 | ||
667 | static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, | 667 | static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, |
668 | int where, int size, u32 val) | 668 | int where, int size, u32 val) |
669 | { | 669 | { |
670 | struct pcie_port *pp = sys_to_pcie(bus->sysdata); | 670 | struct pcie_port *pp = sys_to_pcie(bus->sysdata); |
671 | unsigned long flags; | 671 | unsigned long flags; |
672 | int ret; | 672 | int ret; |
673 | 673 | ||
674 | if (!pp) { | 674 | if (!pp) { |
675 | BUG(); | 675 | BUG(); |
676 | return -EINVAL; | 676 | return -EINVAL; |
677 | } | 677 | } |
678 | 678 | ||
679 | if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) | 679 | if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) |
680 | return PCIBIOS_DEVICE_NOT_FOUND; | 680 | return PCIBIOS_DEVICE_NOT_FOUND; |
681 | 681 | ||
682 | spin_lock_irqsave(&pp->conf_lock, flags); | 682 | spin_lock_irqsave(&pp->conf_lock, flags); |
683 | if (bus->number != pp->root_bus_nr) | 683 | if (bus->number != pp->root_bus_nr) |
684 | ret = dw_pcie_wr_other_conf(pp, bus, devfn, | 684 | ret = dw_pcie_wr_other_conf(pp, bus, devfn, |
685 | where, size, val); | 685 | where, size, val); |
686 | else | 686 | else |
687 | ret = dw_pcie_wr_own_conf(pp, where, size, val); | 687 | ret = dw_pcie_wr_own_conf(pp, where, size, val); |
688 | spin_unlock_irqrestore(&pp->conf_lock, flags); | 688 | spin_unlock_irqrestore(&pp->conf_lock, flags); |
689 | 689 | ||
690 | return ret; | 690 | return ret; |
691 | } | 691 | } |
692 | 692 | ||
693 | static struct pci_ops dw_pcie_ops = { | 693 | static struct pci_ops dw_pcie_ops = { |
694 | .read = dw_pcie_rd_conf, | 694 | .read = dw_pcie_rd_conf, |
695 | .write = dw_pcie_wr_conf, | 695 | .write = dw_pcie_wr_conf, |
696 | }; | 696 | }; |
697 | 697 | ||
698 | static int dw_pcie_setup(int nr, struct pci_sys_data *sys) | 698 | static int dw_pcie_setup(int nr, struct pci_sys_data *sys) |
699 | { | 699 | { |
700 | struct pcie_port *pp; | 700 | struct pcie_port *pp; |
701 | 701 | ||
702 | pp = sys_to_pcie(sys); | 702 | pp = sys_to_pcie(sys); |
703 | 703 | ||
704 | if (!pp) | 704 | if (!pp) |
705 | return 0; | 705 | return 0; |
706 | 706 | ||
707 | if (global_io_offset < SZ_1M && pp->config.io_size > 0) { | 707 | if (global_io_offset < SZ_1M && pp->config.io_size > 0) { |
708 | sys->io_offset = global_io_offset - pp->config.io_bus_addr; | 708 | sys->io_offset = global_io_offset - pp->config.io_bus_addr; |
709 | pci_ioremap_io(global_io_offset, pp->io_base); | 709 | pci_ioremap_io(global_io_offset, pp->io_base); |
710 | global_io_offset += SZ_64K; | 710 | global_io_offset += SZ_64K; |
711 | pci_add_resource_offset(&sys->resources, &pp->io, | 711 | pci_add_resource_offset(&sys->resources, &pp->io, |
712 | sys->io_offset); | 712 | sys->io_offset); |
713 | } | 713 | } |
714 | 714 | ||
715 | sys->mem_offset = pp->mem.start - pp->config.mem_bus_addr; | 715 | sys->mem_offset = pp->mem.start - pp->config.mem_bus_addr; |
716 | pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset); | 716 | pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset); |
717 | 717 | ||
718 | return 1; | 718 | return 1; |
719 | } | 719 | } |
720 | 720 | ||
721 | static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys) | 721 | static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys) |
722 | { | 722 | { |
723 | struct pci_bus *bus; | 723 | struct pci_bus *bus; |
724 | struct pcie_port *pp = sys_to_pcie(sys); | 724 | struct pcie_port *pp = sys_to_pcie(sys); |
725 | 725 | ||
726 | if (pp) { | 726 | if (pp) { |
727 | pp->root_bus_nr = sys->busnr; | 727 | pp->root_bus_nr = sys->busnr; |
728 | bus = pci_scan_root_bus(NULL, sys->busnr, &dw_pcie_ops, | 728 | bus = pci_scan_root_bus(NULL, sys->busnr, &dw_pcie_ops, |
729 | sys, &sys->resources); | 729 | sys, &sys->resources); |
730 | } else { | 730 | } else { |
731 | bus = NULL; | 731 | bus = NULL; |
732 | BUG(); | 732 | BUG(); |
733 | } | 733 | } |
734 | 734 | ||
735 | return bus; | 735 | return bus; |
736 | } | 736 | } |
737 | 737 | ||
738 | static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) | 738 | static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
739 | { | 739 | { |
740 | struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata); | 740 | struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata); |
741 | 741 | ||
742 | return pp->irq; | 742 | return pp->irq; |
743 | } | 743 | } |
744 | 744 | ||
745 | static void dw_pcie_add_bus(struct pci_bus *bus) | 745 | static void dw_pcie_add_bus(struct pci_bus *bus) |
746 | { | 746 | { |
747 | if (IS_ENABLED(CONFIG_PCI_MSI)) { | 747 | if (IS_ENABLED(CONFIG_PCI_MSI)) { |
748 | struct pcie_port *pp = sys_to_pcie(bus->sysdata); | 748 | struct pcie_port *pp = sys_to_pcie(bus->sysdata); |
749 | 749 | ||
750 | dw_pcie_msi_chip.dev = pp->dev; | 750 | dw_pcie_msi_chip.dev = pp->dev; |
751 | bus->msi = &dw_pcie_msi_chip; | 751 | bus->msi = &dw_pcie_msi_chip; |
752 | } | 752 | } |
753 | } | 753 | } |
754 | 754 | ||
755 | static struct hw_pci dw_pci = { | 755 | static struct hw_pci dw_pci = { |
756 | .setup = dw_pcie_setup, | 756 | .setup = dw_pcie_setup, |
757 | .scan = dw_pcie_scan_bus, | 757 | .scan = dw_pcie_scan_bus, |
758 | .map_irq = dw_pcie_map_irq, | 758 | .map_irq = dw_pcie_map_irq, |
759 | .add_bus = dw_pcie_add_bus, | 759 | .add_bus = dw_pcie_add_bus, |
760 | }; | 760 | }; |
761 | 761 | ||
762 | void dw_pcie_setup_rc(struct pcie_port *pp) | 762 | void dw_pcie_setup_rc(struct pcie_port *pp) |
763 | { | 763 | { |
764 | struct pcie_port_info *config = &pp->config; | 764 | struct pcie_port_info *config = &pp->config; |
765 | u32 val; | 765 | u32 val; |
766 | u32 membase; | 766 | u32 membase; |
767 | u32 memlimit; | 767 | u32 memlimit; |
768 | 768 | ||
769 | /* set the number of lines as 4 */ | 769 | /* set the number of lines as 4 */ |
770 | dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val); | 770 | dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val); |
771 | val &= ~PORT_LINK_MODE_MASK; | 771 | val &= ~PORT_LINK_MODE_MASK; |
772 | switch (pp->lanes) { | 772 | switch (pp->lanes) { |
773 | case 1: | 773 | case 1: |
774 | val |= PORT_LINK_MODE_1_LANES; | 774 | val |= PORT_LINK_MODE_1_LANES; |
775 | break; | 775 | break; |
776 | case 2: | 776 | case 2: |
777 | val |= PORT_LINK_MODE_2_LANES; | 777 | val |= PORT_LINK_MODE_2_LANES; |
778 | break; | 778 | break; |
779 | case 4: | 779 | case 4: |
780 | val |= PORT_LINK_MODE_4_LANES; | 780 | val |= PORT_LINK_MODE_4_LANES; |
781 | break; | 781 | break; |
782 | } | 782 | } |
783 | dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL); | 783 | dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL); |
784 | 784 | ||
785 | /* set link width speed control register */ | 785 | /* set link width speed control register */ |
786 | dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val); | 786 | dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val); |
787 | val &= ~PORT_LOGIC_LINK_WIDTH_MASK; | 787 | val &= ~PORT_LOGIC_LINK_WIDTH_MASK; |
788 | switch (pp->lanes) { | 788 | switch (pp->lanes) { |
789 | case 1: | 789 | case 1: |
790 | val |= PORT_LOGIC_LINK_WIDTH_1_LANES; | 790 | val |= PORT_LOGIC_LINK_WIDTH_1_LANES; |
791 | break; | 791 | break; |
792 | case 2: | 792 | case 2: |
793 | val |= PORT_LOGIC_LINK_WIDTH_2_LANES; | 793 | val |= PORT_LOGIC_LINK_WIDTH_2_LANES; |
794 | break; | 794 | break; |
795 | case 4: | 795 | case 4: |
796 | val |= PORT_LOGIC_LINK_WIDTH_4_LANES; | 796 | val |= PORT_LOGIC_LINK_WIDTH_4_LANES; |
797 | break; | 797 | break; |
798 | } | 798 | } |
799 | dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL); | 799 | dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL); |
800 | 800 | ||
801 | /* setup RC BARs */ | 801 | /* setup RC BARs */ |
802 | dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0); | 802 | dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0); |
803 | dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1); | 803 | dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1); |
804 | 804 | ||
805 | /* setup interrupt pins */ | 805 | /* setup interrupt pins */ |
806 | dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val); | 806 | dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val); |
807 | val &= 0xffff00ff; | 807 | val &= 0xffff00ff; |
808 | val |= 0x00000100; | 808 | val |= 0x00000100; |
809 | dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE); | 809 | dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE); |
810 | 810 | ||
811 | /* setup bus numbers */ | 811 | /* setup bus numbers */ |
812 | dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val); | 812 | dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val); |
813 | val &= 0xff000000; | 813 | val &= 0xff000000; |
814 | val |= 0x00010100; | 814 | val |= 0x00010100; |
815 | dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS); | 815 | dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS); |
816 | 816 | ||
817 | /* setup memory base, memory limit */ | 817 | /* setup memory base, memory limit */ |
818 | membase = ((u32)pp->mem_base & 0xfff00000) >> 16; | 818 | membase = ((u32)pp->mem_base & 0xfff00000) >> 16; |
819 | memlimit = (config->mem_size + (u32)pp->mem_base) & 0xfff00000; | 819 | memlimit = (config->mem_size + (u32)pp->mem_base) & 0xfff00000; |
820 | val = memlimit | membase; | 820 | val = memlimit | membase; |
821 | dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE); | 821 | dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE); |
822 | 822 | ||
823 | /* setup command register */ | 823 | /* setup command register */ |
824 | dw_pcie_readl_rc(pp, PCI_COMMAND, &val); | 824 | dw_pcie_readl_rc(pp, PCI_COMMAND, &val); |
825 | val &= 0xffff0000; | 825 | val &= 0xffff0000; |
826 | val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | | 826 | val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | |
827 | PCI_COMMAND_MASTER | PCI_COMMAND_SERR; | 827 | PCI_COMMAND_MASTER | PCI_COMMAND_SERR; |
828 | dw_pcie_writel_rc(pp, val, PCI_COMMAND); | 828 | dw_pcie_writel_rc(pp, val, PCI_COMMAND); |
829 | } | 829 | } |
830 | 830 | ||
831 | MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>"); | 831 | MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>"); |