Commit 6ba736dd02e7b3658c344efeb2f4a096a6785d83
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ALSA: hda - Suppress CORBRP clear on Nvidia controller chips
The recent commit (ca460f86521) changed the CORB RP reset procedure to follow the specification with a couple of sanity checks. Unfortunately, Nvidia controller chips seem not following this way, and spew the warning messages like: snd_hda_intel 0000:00:10.1: CORB reset timeout#1, CORBRP = 0 This patch adds the workaround for such chips. It just skips the new reset procedure for the known broken chips. Signed-off-by: Takashi Iwai <tiwai@suse.de>
Showing 3 changed files with 21 additions and 17 deletions Inline Diff
sound/pci/hda/hda_controller.c
1 | /* | 1 | /* |
2 | * | 2 | * |
3 | * Implementation of primary alsa driver code base for Intel HD Audio. | 3 | * Implementation of primary alsa driver code base for Intel HD Audio. |
4 | * | 4 | * |
5 | * Copyright(c) 2004 Intel Corporation. All rights reserved. | 5 | * Copyright(c) 2004 Intel Corporation. All rights reserved. |
6 | * | 6 | * |
7 | * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> | 7 | * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> |
8 | * PeiSen Hou <pshou@realtek.com.tw> | 8 | * PeiSen Hou <pshou@realtek.com.tw> |
9 | * | 9 | * |
10 | * This program is free software; you can redistribute it and/or modify it | 10 | * This program is free software; you can redistribute it and/or modify it |
11 | * under the terms of the GNU General Public License as published by the Free | 11 | * under the terms of the GNU General Public License as published by the Free |
12 | * Software Foundation; either version 2 of the License, or (at your option) | 12 | * Software Foundation; either version 2 of the License, or (at your option) |
13 | * any later version. | 13 | * any later version. |
14 | * | 14 | * |
15 | * This program is distributed in the hope that it will be useful, but WITHOUT | 15 | * This program is distributed in the hope that it will be useful, but WITHOUT |
16 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | 16 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
17 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | 17 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
18 | * more details. | 18 | * more details. |
19 | * | 19 | * |
20 | * | 20 | * |
21 | */ | 21 | */ |
22 | 22 | ||
23 | #include <linux/clocksource.h> | 23 | #include <linux/clocksource.h> |
24 | #include <linux/delay.h> | 24 | #include <linux/delay.h> |
25 | #include <linux/interrupt.h> | 25 | #include <linux/interrupt.h> |
26 | #include <linux/kernel.h> | 26 | #include <linux/kernel.h> |
27 | #include <linux/module.h> | 27 | #include <linux/module.h> |
28 | #include <linux/pm_runtime.h> | 28 | #include <linux/pm_runtime.h> |
29 | #include <linux/slab.h> | 29 | #include <linux/slab.h> |
30 | #include <sound/core.h> | 30 | #include <sound/core.h> |
31 | #include <sound/initval.h> | 31 | #include <sound/initval.h> |
32 | #include "hda_priv.h" | 32 | #include "hda_priv.h" |
33 | #include "hda_controller.h" | 33 | #include "hda_controller.h" |
34 | 34 | ||
35 | #define CREATE_TRACE_POINTS | 35 | #define CREATE_TRACE_POINTS |
36 | #include "hda_intel_trace.h" | 36 | #include "hda_intel_trace.h" |
37 | 37 | ||
38 | /* DSP lock helpers */ | 38 | /* DSP lock helpers */ |
39 | #ifdef CONFIG_SND_HDA_DSP_LOADER | 39 | #ifdef CONFIG_SND_HDA_DSP_LOADER |
40 | #define dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex) | 40 | #define dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex) |
41 | #define dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex) | 41 | #define dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex) |
42 | #define dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex) | 42 | #define dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex) |
43 | #define dsp_is_locked(dev) ((dev)->locked) | 43 | #define dsp_is_locked(dev) ((dev)->locked) |
44 | #else | 44 | #else |
45 | #define dsp_lock_init(dev) do {} while (0) | 45 | #define dsp_lock_init(dev) do {} while (0) |
46 | #define dsp_lock(dev) do {} while (0) | 46 | #define dsp_lock(dev) do {} while (0) |
47 | #define dsp_unlock(dev) do {} while (0) | 47 | #define dsp_unlock(dev) do {} while (0) |
48 | #define dsp_is_locked(dev) 0 | 48 | #define dsp_is_locked(dev) 0 |
49 | #endif | 49 | #endif |
50 | 50 | ||
51 | /* | 51 | /* |
52 | * AZX stream operations. | 52 | * AZX stream operations. |
53 | */ | 53 | */ |
54 | 54 | ||
55 | /* start a stream */ | 55 | /* start a stream */ |
56 | static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev) | 56 | static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev) |
57 | { | 57 | { |
58 | /* | 58 | /* |
59 | * Before stream start, initialize parameter | 59 | * Before stream start, initialize parameter |
60 | */ | 60 | */ |
61 | azx_dev->insufficient = 1; | 61 | azx_dev->insufficient = 1; |
62 | 62 | ||
63 | /* enable SIE */ | 63 | /* enable SIE */ |
64 | azx_writel(chip, INTCTL, | 64 | azx_writel(chip, INTCTL, |
65 | azx_readl(chip, INTCTL) | (1 << azx_dev->index)); | 65 | azx_readl(chip, INTCTL) | (1 << azx_dev->index)); |
66 | /* set DMA start and interrupt mask */ | 66 | /* set DMA start and interrupt mask */ |
67 | azx_sd_writeb(chip, azx_dev, SD_CTL, | 67 | azx_sd_writeb(chip, azx_dev, SD_CTL, |
68 | azx_sd_readb(chip, azx_dev, SD_CTL) | | 68 | azx_sd_readb(chip, azx_dev, SD_CTL) | |
69 | SD_CTL_DMA_START | SD_INT_MASK); | 69 | SD_CTL_DMA_START | SD_INT_MASK); |
70 | } | 70 | } |
71 | 71 | ||
72 | /* stop DMA */ | 72 | /* stop DMA */ |
73 | static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev) | 73 | static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev) |
74 | { | 74 | { |
75 | azx_sd_writeb(chip, azx_dev, SD_CTL, | 75 | azx_sd_writeb(chip, azx_dev, SD_CTL, |
76 | azx_sd_readb(chip, azx_dev, SD_CTL) & | 76 | azx_sd_readb(chip, azx_dev, SD_CTL) & |
77 | ~(SD_CTL_DMA_START | SD_INT_MASK)); | 77 | ~(SD_CTL_DMA_START | SD_INT_MASK)); |
78 | azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ | 78 | azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ |
79 | } | 79 | } |
80 | 80 | ||
81 | /* stop a stream */ | 81 | /* stop a stream */ |
82 | void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev) | 82 | void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev) |
83 | { | 83 | { |
84 | azx_stream_clear(chip, azx_dev); | 84 | azx_stream_clear(chip, azx_dev); |
85 | /* disable SIE */ | 85 | /* disable SIE */ |
86 | azx_writel(chip, INTCTL, | 86 | azx_writel(chip, INTCTL, |
87 | azx_readl(chip, INTCTL) & ~(1 << azx_dev->index)); | 87 | azx_readl(chip, INTCTL) & ~(1 << azx_dev->index)); |
88 | } | 88 | } |
89 | EXPORT_SYMBOL_GPL(azx_stream_stop); | 89 | EXPORT_SYMBOL_GPL(azx_stream_stop); |
90 | 90 | ||
91 | /* reset stream */ | 91 | /* reset stream */ |
92 | static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev) | 92 | static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev) |
93 | { | 93 | { |
94 | unsigned char val; | 94 | unsigned char val; |
95 | int timeout; | 95 | int timeout; |
96 | 96 | ||
97 | azx_stream_clear(chip, azx_dev); | 97 | azx_stream_clear(chip, azx_dev); |
98 | 98 | ||
99 | azx_sd_writeb(chip, azx_dev, SD_CTL, | 99 | azx_sd_writeb(chip, azx_dev, SD_CTL, |
100 | azx_sd_readb(chip, azx_dev, SD_CTL) | | 100 | azx_sd_readb(chip, azx_dev, SD_CTL) | |
101 | SD_CTL_STREAM_RESET); | 101 | SD_CTL_STREAM_RESET); |
102 | udelay(3); | 102 | udelay(3); |
103 | timeout = 300; | 103 | timeout = 300; |
104 | while (!((val = azx_sd_readb(chip, azx_dev, SD_CTL)) & | 104 | while (!((val = azx_sd_readb(chip, azx_dev, SD_CTL)) & |
105 | SD_CTL_STREAM_RESET) && --timeout) | 105 | SD_CTL_STREAM_RESET) && --timeout) |
106 | ; | 106 | ; |
107 | val &= ~SD_CTL_STREAM_RESET; | 107 | val &= ~SD_CTL_STREAM_RESET; |
108 | azx_sd_writeb(chip, azx_dev, SD_CTL, val); | 108 | azx_sd_writeb(chip, azx_dev, SD_CTL, val); |
109 | udelay(3); | 109 | udelay(3); |
110 | 110 | ||
111 | timeout = 300; | 111 | timeout = 300; |
112 | /* waiting for hardware to report that the stream is out of reset */ | 112 | /* waiting for hardware to report that the stream is out of reset */ |
113 | while (((val = azx_sd_readb(chip, azx_dev, SD_CTL)) & | 113 | while (((val = azx_sd_readb(chip, azx_dev, SD_CTL)) & |
114 | SD_CTL_STREAM_RESET) && --timeout) | 114 | SD_CTL_STREAM_RESET) && --timeout) |
115 | ; | 115 | ; |
116 | 116 | ||
117 | /* reset first position - may not be synced with hw at this time */ | 117 | /* reset first position - may not be synced with hw at this time */ |
118 | *azx_dev->posbuf = 0; | 118 | *azx_dev->posbuf = 0; |
119 | } | 119 | } |
120 | 120 | ||
121 | /* | 121 | /* |
122 | * set up the SD for streaming | 122 | * set up the SD for streaming |
123 | */ | 123 | */ |
124 | static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev) | 124 | static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev) |
125 | { | 125 | { |
126 | unsigned int val; | 126 | unsigned int val; |
127 | /* make sure the run bit is zero for SD */ | 127 | /* make sure the run bit is zero for SD */ |
128 | azx_stream_clear(chip, azx_dev); | 128 | azx_stream_clear(chip, azx_dev); |
129 | /* program the stream_tag */ | 129 | /* program the stream_tag */ |
130 | val = azx_sd_readl(chip, azx_dev, SD_CTL); | 130 | val = azx_sd_readl(chip, azx_dev, SD_CTL); |
131 | val = (val & ~SD_CTL_STREAM_TAG_MASK) | | 131 | val = (val & ~SD_CTL_STREAM_TAG_MASK) | |
132 | (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT); | 132 | (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT); |
133 | if (!azx_snoop(chip)) | 133 | if (!azx_snoop(chip)) |
134 | val |= SD_CTL_TRAFFIC_PRIO; | 134 | val |= SD_CTL_TRAFFIC_PRIO; |
135 | azx_sd_writel(chip, azx_dev, SD_CTL, val); | 135 | azx_sd_writel(chip, azx_dev, SD_CTL, val); |
136 | 136 | ||
137 | /* program the length of samples in cyclic buffer */ | 137 | /* program the length of samples in cyclic buffer */ |
138 | azx_sd_writel(chip, azx_dev, SD_CBL, azx_dev->bufsize); | 138 | azx_sd_writel(chip, azx_dev, SD_CBL, azx_dev->bufsize); |
139 | 139 | ||
140 | /* program the stream format */ | 140 | /* program the stream format */ |
141 | /* this value needs to be the same as the one programmed */ | 141 | /* this value needs to be the same as the one programmed */ |
142 | azx_sd_writew(chip, azx_dev, SD_FORMAT, azx_dev->format_val); | 142 | azx_sd_writew(chip, azx_dev, SD_FORMAT, azx_dev->format_val); |
143 | 143 | ||
144 | /* program the stream LVI (last valid index) of the BDL */ | 144 | /* program the stream LVI (last valid index) of the BDL */ |
145 | azx_sd_writew(chip, azx_dev, SD_LVI, azx_dev->frags - 1); | 145 | azx_sd_writew(chip, azx_dev, SD_LVI, azx_dev->frags - 1); |
146 | 146 | ||
147 | /* program the BDL address */ | 147 | /* program the BDL address */ |
148 | /* lower BDL address */ | 148 | /* lower BDL address */ |
149 | azx_sd_writel(chip, azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr); | 149 | azx_sd_writel(chip, azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr); |
150 | /* upper BDL address */ | 150 | /* upper BDL address */ |
151 | azx_sd_writel(chip, azx_dev, SD_BDLPU, | 151 | azx_sd_writel(chip, azx_dev, SD_BDLPU, |
152 | upper_32_bits(azx_dev->bdl.addr)); | 152 | upper_32_bits(azx_dev->bdl.addr)); |
153 | 153 | ||
154 | /* enable the position buffer */ | 154 | /* enable the position buffer */ |
155 | if (chip->position_fix[0] != POS_FIX_LPIB || | 155 | if (chip->position_fix[0] != POS_FIX_LPIB || |
156 | chip->position_fix[1] != POS_FIX_LPIB) { | 156 | chip->position_fix[1] != POS_FIX_LPIB) { |
157 | if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE)) | 157 | if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE)) |
158 | azx_writel(chip, DPLBASE, | 158 | azx_writel(chip, DPLBASE, |
159 | (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE); | 159 | (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE); |
160 | } | 160 | } |
161 | 161 | ||
162 | /* set the interrupt enable bits in the descriptor control register */ | 162 | /* set the interrupt enable bits in the descriptor control register */ |
163 | azx_sd_writel(chip, azx_dev, SD_CTL, | 163 | azx_sd_writel(chip, azx_dev, SD_CTL, |
164 | azx_sd_readl(chip, azx_dev, SD_CTL) | SD_INT_MASK); | 164 | azx_sd_readl(chip, azx_dev, SD_CTL) | SD_INT_MASK); |
165 | 165 | ||
166 | return 0; | 166 | return 0; |
167 | } | 167 | } |
168 | 168 | ||
169 | /* assign a stream for the PCM */ | 169 | /* assign a stream for the PCM */ |
170 | static inline struct azx_dev * | 170 | static inline struct azx_dev * |
171 | azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream) | 171 | azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream) |
172 | { | 172 | { |
173 | int dev, i, nums; | 173 | int dev, i, nums; |
174 | struct azx_dev *res = NULL; | 174 | struct azx_dev *res = NULL; |
175 | /* make a non-zero unique key for the substream */ | 175 | /* make a non-zero unique key for the substream */ |
176 | int key = (substream->pcm->device << 16) | (substream->number << 2) | | 176 | int key = (substream->pcm->device << 16) | (substream->number << 2) | |
177 | (substream->stream + 1); | 177 | (substream->stream + 1); |
178 | 178 | ||
179 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | 179 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
180 | dev = chip->playback_index_offset; | 180 | dev = chip->playback_index_offset; |
181 | nums = chip->playback_streams; | 181 | nums = chip->playback_streams; |
182 | } else { | 182 | } else { |
183 | dev = chip->capture_index_offset; | 183 | dev = chip->capture_index_offset; |
184 | nums = chip->capture_streams; | 184 | nums = chip->capture_streams; |
185 | } | 185 | } |
186 | for (i = 0; i < nums; i++, dev++) { | 186 | for (i = 0; i < nums; i++, dev++) { |
187 | struct azx_dev *azx_dev = &chip->azx_dev[dev]; | 187 | struct azx_dev *azx_dev = &chip->azx_dev[dev]; |
188 | dsp_lock(azx_dev); | 188 | dsp_lock(azx_dev); |
189 | if (!azx_dev->opened && !dsp_is_locked(azx_dev)) { | 189 | if (!azx_dev->opened && !dsp_is_locked(azx_dev)) { |
190 | if (azx_dev->assigned_key == key) { | 190 | if (azx_dev->assigned_key == key) { |
191 | azx_dev->opened = 1; | 191 | azx_dev->opened = 1; |
192 | azx_dev->assigned_key = key; | 192 | azx_dev->assigned_key = key; |
193 | dsp_unlock(azx_dev); | 193 | dsp_unlock(azx_dev); |
194 | return azx_dev; | 194 | return azx_dev; |
195 | } | 195 | } |
196 | if (!res) | 196 | if (!res) |
197 | res = azx_dev; | 197 | res = azx_dev; |
198 | } | 198 | } |
199 | dsp_unlock(azx_dev); | 199 | dsp_unlock(azx_dev); |
200 | } | 200 | } |
201 | if (res) { | 201 | if (res) { |
202 | dsp_lock(res); | 202 | dsp_lock(res); |
203 | res->opened = 1; | 203 | res->opened = 1; |
204 | res->assigned_key = key; | 204 | res->assigned_key = key; |
205 | dsp_unlock(res); | 205 | dsp_unlock(res); |
206 | } | 206 | } |
207 | return res; | 207 | return res; |
208 | } | 208 | } |
209 | 209 | ||
210 | /* release the assigned stream */ | 210 | /* release the assigned stream */ |
211 | static inline void azx_release_device(struct azx_dev *azx_dev) | 211 | static inline void azx_release_device(struct azx_dev *azx_dev) |
212 | { | 212 | { |
213 | azx_dev->opened = 0; | 213 | azx_dev->opened = 0; |
214 | } | 214 | } |
215 | 215 | ||
216 | static cycle_t azx_cc_read(const struct cyclecounter *cc) | 216 | static cycle_t azx_cc_read(const struct cyclecounter *cc) |
217 | { | 217 | { |
218 | struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc); | 218 | struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc); |
219 | struct snd_pcm_substream *substream = azx_dev->substream; | 219 | struct snd_pcm_substream *substream = azx_dev->substream; |
220 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | 220 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
221 | struct azx *chip = apcm->chip; | 221 | struct azx *chip = apcm->chip; |
222 | 222 | ||
223 | return azx_readl(chip, WALLCLK); | 223 | return azx_readl(chip, WALLCLK); |
224 | } | 224 | } |
225 | 225 | ||
226 | static void azx_timecounter_init(struct snd_pcm_substream *substream, | 226 | static void azx_timecounter_init(struct snd_pcm_substream *substream, |
227 | bool force, cycle_t last) | 227 | bool force, cycle_t last) |
228 | { | 228 | { |
229 | struct azx_dev *azx_dev = get_azx_dev(substream); | 229 | struct azx_dev *azx_dev = get_azx_dev(substream); |
230 | struct timecounter *tc = &azx_dev->azx_tc; | 230 | struct timecounter *tc = &azx_dev->azx_tc; |
231 | struct cyclecounter *cc = &azx_dev->azx_cc; | 231 | struct cyclecounter *cc = &azx_dev->azx_cc; |
232 | u64 nsec; | 232 | u64 nsec; |
233 | 233 | ||
234 | cc->read = azx_cc_read; | 234 | cc->read = azx_cc_read; |
235 | cc->mask = CLOCKSOURCE_MASK(32); | 235 | cc->mask = CLOCKSOURCE_MASK(32); |
236 | 236 | ||
237 | /* | 237 | /* |
238 | * Converting from 24 MHz to ns means applying a 125/3 factor. | 238 | * Converting from 24 MHz to ns means applying a 125/3 factor. |
239 | * To avoid any saturation issues in intermediate operations, | 239 | * To avoid any saturation issues in intermediate operations, |
240 | * the 125 factor is applied first. The division is applied | 240 | * the 125 factor is applied first. The division is applied |
241 | * last after reading the timecounter value. | 241 | * last after reading the timecounter value. |
242 | * Applying the 1/3 factor as part of the multiplication | 242 | * Applying the 1/3 factor as part of the multiplication |
243 | * requires at least 20 bits for a decent precision, however | 243 | * requires at least 20 bits for a decent precision, however |
244 | * overflows occur after about 4 hours or less, not a option. | 244 | * overflows occur after about 4 hours or less, not a option. |
245 | */ | 245 | */ |
246 | 246 | ||
247 | cc->mult = 125; /* saturation after 195 years */ | 247 | cc->mult = 125; /* saturation after 195 years */ |
248 | cc->shift = 0; | 248 | cc->shift = 0; |
249 | 249 | ||
250 | nsec = 0; /* audio time is elapsed time since trigger */ | 250 | nsec = 0; /* audio time is elapsed time since trigger */ |
251 | timecounter_init(tc, cc, nsec); | 251 | timecounter_init(tc, cc, nsec); |
252 | if (force) | 252 | if (force) |
253 | /* | 253 | /* |
254 | * force timecounter to use predefined value, | 254 | * force timecounter to use predefined value, |
255 | * used for synchronized starts | 255 | * used for synchronized starts |
256 | */ | 256 | */ |
257 | tc->cycle_last = last; | 257 | tc->cycle_last = last; |
258 | } | 258 | } |
259 | 259 | ||
260 | static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream, | 260 | static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream, |
261 | u64 nsec) | 261 | u64 nsec) |
262 | { | 262 | { |
263 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | 263 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
264 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | 264 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; |
265 | u64 codec_frames, codec_nsecs; | 265 | u64 codec_frames, codec_nsecs; |
266 | 266 | ||
267 | if (!hinfo->ops.get_delay) | 267 | if (!hinfo->ops.get_delay) |
268 | return nsec; | 268 | return nsec; |
269 | 269 | ||
270 | codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream); | 270 | codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream); |
271 | codec_nsecs = div_u64(codec_frames * 1000000000LL, | 271 | codec_nsecs = div_u64(codec_frames * 1000000000LL, |
272 | substream->runtime->rate); | 272 | substream->runtime->rate); |
273 | 273 | ||
274 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | 274 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) |
275 | return nsec + codec_nsecs; | 275 | return nsec + codec_nsecs; |
276 | 276 | ||
277 | return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0; | 277 | return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0; |
278 | } | 278 | } |
279 | 279 | ||
280 | /* | 280 | /* |
281 | * set up a BDL entry | 281 | * set up a BDL entry |
282 | */ | 282 | */ |
283 | static int setup_bdle(struct azx *chip, | 283 | static int setup_bdle(struct azx *chip, |
284 | struct snd_dma_buffer *dmab, | 284 | struct snd_dma_buffer *dmab, |
285 | struct azx_dev *azx_dev, u32 **bdlp, | 285 | struct azx_dev *azx_dev, u32 **bdlp, |
286 | int ofs, int size, int with_ioc) | 286 | int ofs, int size, int with_ioc) |
287 | { | 287 | { |
288 | u32 *bdl = *bdlp; | 288 | u32 *bdl = *bdlp; |
289 | 289 | ||
290 | while (size > 0) { | 290 | while (size > 0) { |
291 | dma_addr_t addr; | 291 | dma_addr_t addr; |
292 | int chunk; | 292 | int chunk; |
293 | 293 | ||
294 | if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES) | 294 | if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES) |
295 | return -EINVAL; | 295 | return -EINVAL; |
296 | 296 | ||
297 | addr = snd_sgbuf_get_addr(dmab, ofs); | 297 | addr = snd_sgbuf_get_addr(dmab, ofs); |
298 | /* program the address field of the BDL entry */ | 298 | /* program the address field of the BDL entry */ |
299 | bdl[0] = cpu_to_le32((u32)addr); | 299 | bdl[0] = cpu_to_le32((u32)addr); |
300 | bdl[1] = cpu_to_le32(upper_32_bits(addr)); | 300 | bdl[1] = cpu_to_le32(upper_32_bits(addr)); |
301 | /* program the size field of the BDL entry */ | 301 | /* program the size field of the BDL entry */ |
302 | chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size); | 302 | chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size); |
303 | /* one BDLE cannot cross 4K boundary on CTHDA chips */ | 303 | /* one BDLE cannot cross 4K boundary on CTHDA chips */ |
304 | if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) { | 304 | if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) { |
305 | u32 remain = 0x1000 - (ofs & 0xfff); | 305 | u32 remain = 0x1000 - (ofs & 0xfff); |
306 | if (chunk > remain) | 306 | if (chunk > remain) |
307 | chunk = remain; | 307 | chunk = remain; |
308 | } | 308 | } |
309 | bdl[2] = cpu_to_le32(chunk); | 309 | bdl[2] = cpu_to_le32(chunk); |
310 | /* program the IOC to enable interrupt | 310 | /* program the IOC to enable interrupt |
311 | * only when the whole fragment is processed | 311 | * only when the whole fragment is processed |
312 | */ | 312 | */ |
313 | size -= chunk; | 313 | size -= chunk; |
314 | bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01); | 314 | bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01); |
315 | bdl += 4; | 315 | bdl += 4; |
316 | azx_dev->frags++; | 316 | azx_dev->frags++; |
317 | ofs += chunk; | 317 | ofs += chunk; |
318 | } | 318 | } |
319 | *bdlp = bdl; | 319 | *bdlp = bdl; |
320 | return ofs; | 320 | return ofs; |
321 | } | 321 | } |
322 | 322 | ||
323 | /* | 323 | /* |
324 | * set up BDL entries | 324 | * set up BDL entries |
325 | */ | 325 | */ |
326 | static int azx_setup_periods(struct azx *chip, | 326 | static int azx_setup_periods(struct azx *chip, |
327 | struct snd_pcm_substream *substream, | 327 | struct snd_pcm_substream *substream, |
328 | struct azx_dev *azx_dev) | 328 | struct azx_dev *azx_dev) |
329 | { | 329 | { |
330 | u32 *bdl; | 330 | u32 *bdl; |
331 | int i, ofs, periods, period_bytes; | 331 | int i, ofs, periods, period_bytes; |
332 | int pos_adj = 0; | 332 | int pos_adj = 0; |
333 | 333 | ||
334 | /* reset BDL address */ | 334 | /* reset BDL address */ |
335 | azx_sd_writel(chip, azx_dev, SD_BDLPL, 0); | 335 | azx_sd_writel(chip, azx_dev, SD_BDLPL, 0); |
336 | azx_sd_writel(chip, azx_dev, SD_BDLPU, 0); | 336 | azx_sd_writel(chip, azx_dev, SD_BDLPU, 0); |
337 | 337 | ||
338 | period_bytes = azx_dev->period_bytes; | 338 | period_bytes = azx_dev->period_bytes; |
339 | periods = azx_dev->bufsize / period_bytes; | 339 | periods = azx_dev->bufsize / period_bytes; |
340 | 340 | ||
341 | /* program the initial BDL entries */ | 341 | /* program the initial BDL entries */ |
342 | bdl = (u32 *)azx_dev->bdl.area; | 342 | bdl = (u32 *)azx_dev->bdl.area; |
343 | ofs = 0; | 343 | ofs = 0; |
344 | azx_dev->frags = 0; | 344 | azx_dev->frags = 0; |
345 | 345 | ||
346 | if (chip->bdl_pos_adj) | 346 | if (chip->bdl_pos_adj) |
347 | pos_adj = chip->bdl_pos_adj[chip->dev_index]; | 347 | pos_adj = chip->bdl_pos_adj[chip->dev_index]; |
348 | if (!azx_dev->no_period_wakeup && pos_adj > 0) { | 348 | if (!azx_dev->no_period_wakeup && pos_adj > 0) { |
349 | struct snd_pcm_runtime *runtime = substream->runtime; | 349 | struct snd_pcm_runtime *runtime = substream->runtime; |
350 | int pos_align = pos_adj; | 350 | int pos_align = pos_adj; |
351 | pos_adj = (pos_adj * runtime->rate + 47999) / 48000; | 351 | pos_adj = (pos_adj * runtime->rate + 47999) / 48000; |
352 | if (!pos_adj) | 352 | if (!pos_adj) |
353 | pos_adj = pos_align; | 353 | pos_adj = pos_align; |
354 | else | 354 | else |
355 | pos_adj = ((pos_adj + pos_align - 1) / pos_align) * | 355 | pos_adj = ((pos_adj + pos_align - 1) / pos_align) * |
356 | pos_align; | 356 | pos_align; |
357 | pos_adj = frames_to_bytes(runtime, pos_adj); | 357 | pos_adj = frames_to_bytes(runtime, pos_adj); |
358 | if (pos_adj >= period_bytes) { | 358 | if (pos_adj >= period_bytes) { |
359 | dev_warn(chip->card->dev,"Too big adjustment %d\n", | 359 | dev_warn(chip->card->dev,"Too big adjustment %d\n", |
360 | pos_adj); | 360 | pos_adj); |
361 | pos_adj = 0; | 361 | pos_adj = 0; |
362 | } else { | 362 | } else { |
363 | ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream), | 363 | ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream), |
364 | azx_dev, | 364 | azx_dev, |
365 | &bdl, ofs, pos_adj, true); | 365 | &bdl, ofs, pos_adj, true); |
366 | if (ofs < 0) | 366 | if (ofs < 0) |
367 | goto error; | 367 | goto error; |
368 | } | 368 | } |
369 | } else | 369 | } else |
370 | pos_adj = 0; | 370 | pos_adj = 0; |
371 | 371 | ||
372 | for (i = 0; i < periods; i++) { | 372 | for (i = 0; i < periods; i++) { |
373 | if (i == periods - 1 && pos_adj) | 373 | if (i == periods - 1 && pos_adj) |
374 | ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream), | 374 | ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream), |
375 | azx_dev, &bdl, ofs, | 375 | azx_dev, &bdl, ofs, |
376 | period_bytes - pos_adj, 0); | 376 | period_bytes - pos_adj, 0); |
377 | else | 377 | else |
378 | ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream), | 378 | ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream), |
379 | azx_dev, &bdl, ofs, | 379 | azx_dev, &bdl, ofs, |
380 | period_bytes, | 380 | period_bytes, |
381 | !azx_dev->no_period_wakeup); | 381 | !azx_dev->no_period_wakeup); |
382 | if (ofs < 0) | 382 | if (ofs < 0) |
383 | goto error; | 383 | goto error; |
384 | } | 384 | } |
385 | return 0; | 385 | return 0; |
386 | 386 | ||
387 | error: | 387 | error: |
388 | dev_err(chip->card->dev, "Too many BDL entries: buffer=%d, period=%d\n", | 388 | dev_err(chip->card->dev, "Too many BDL entries: buffer=%d, period=%d\n", |
389 | azx_dev->bufsize, period_bytes); | 389 | azx_dev->bufsize, period_bytes); |
390 | return -EINVAL; | 390 | return -EINVAL; |
391 | } | 391 | } |
392 | 392 | ||
393 | /* | 393 | /* |
394 | * PCM ops | 394 | * PCM ops |
395 | */ | 395 | */ |
396 | 396 | ||
397 | static int azx_pcm_close(struct snd_pcm_substream *substream) | 397 | static int azx_pcm_close(struct snd_pcm_substream *substream) |
398 | { | 398 | { |
399 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | 399 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
400 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | 400 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; |
401 | struct azx *chip = apcm->chip; | 401 | struct azx *chip = apcm->chip; |
402 | struct azx_dev *azx_dev = get_azx_dev(substream); | 402 | struct azx_dev *azx_dev = get_azx_dev(substream); |
403 | unsigned long flags; | 403 | unsigned long flags; |
404 | 404 | ||
405 | mutex_lock(&chip->open_mutex); | 405 | mutex_lock(&chip->open_mutex); |
406 | spin_lock_irqsave(&chip->reg_lock, flags); | 406 | spin_lock_irqsave(&chip->reg_lock, flags); |
407 | azx_dev->substream = NULL; | 407 | azx_dev->substream = NULL; |
408 | azx_dev->running = 0; | 408 | azx_dev->running = 0; |
409 | spin_unlock_irqrestore(&chip->reg_lock, flags); | 409 | spin_unlock_irqrestore(&chip->reg_lock, flags); |
410 | azx_release_device(azx_dev); | 410 | azx_release_device(azx_dev); |
411 | hinfo->ops.close(hinfo, apcm->codec, substream); | 411 | hinfo->ops.close(hinfo, apcm->codec, substream); |
412 | snd_hda_power_down(apcm->codec); | 412 | snd_hda_power_down(apcm->codec); |
413 | mutex_unlock(&chip->open_mutex); | 413 | mutex_unlock(&chip->open_mutex); |
414 | return 0; | 414 | return 0; |
415 | } | 415 | } |
416 | 416 | ||
417 | static int azx_pcm_hw_params(struct snd_pcm_substream *substream, | 417 | static int azx_pcm_hw_params(struct snd_pcm_substream *substream, |
418 | struct snd_pcm_hw_params *hw_params) | 418 | struct snd_pcm_hw_params *hw_params) |
419 | { | 419 | { |
420 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | 420 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
421 | struct azx *chip = apcm->chip; | 421 | struct azx *chip = apcm->chip; |
422 | int ret; | 422 | int ret; |
423 | 423 | ||
424 | dsp_lock(get_azx_dev(substream)); | 424 | dsp_lock(get_azx_dev(substream)); |
425 | if (dsp_is_locked(get_azx_dev(substream))) { | 425 | if (dsp_is_locked(get_azx_dev(substream))) { |
426 | ret = -EBUSY; | 426 | ret = -EBUSY; |
427 | goto unlock; | 427 | goto unlock; |
428 | } | 428 | } |
429 | 429 | ||
430 | ret = chip->ops->substream_alloc_pages(chip, substream, | 430 | ret = chip->ops->substream_alloc_pages(chip, substream, |
431 | params_buffer_bytes(hw_params)); | 431 | params_buffer_bytes(hw_params)); |
432 | unlock: | 432 | unlock: |
433 | dsp_unlock(get_azx_dev(substream)); | 433 | dsp_unlock(get_azx_dev(substream)); |
434 | return ret; | 434 | return ret; |
435 | } | 435 | } |
436 | 436 | ||
437 | static int azx_pcm_hw_free(struct snd_pcm_substream *substream) | 437 | static int azx_pcm_hw_free(struct snd_pcm_substream *substream) |
438 | { | 438 | { |
439 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | 439 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
440 | struct azx_dev *azx_dev = get_azx_dev(substream); | 440 | struct azx_dev *azx_dev = get_azx_dev(substream); |
441 | struct azx *chip = apcm->chip; | 441 | struct azx *chip = apcm->chip; |
442 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | 442 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; |
443 | int err; | 443 | int err; |
444 | 444 | ||
445 | /* reset BDL address */ | 445 | /* reset BDL address */ |
446 | dsp_lock(azx_dev); | 446 | dsp_lock(azx_dev); |
447 | if (!dsp_is_locked(azx_dev)) { | 447 | if (!dsp_is_locked(azx_dev)) { |
448 | azx_sd_writel(chip, azx_dev, SD_BDLPL, 0); | 448 | azx_sd_writel(chip, azx_dev, SD_BDLPL, 0); |
449 | azx_sd_writel(chip, azx_dev, SD_BDLPU, 0); | 449 | azx_sd_writel(chip, azx_dev, SD_BDLPU, 0); |
450 | azx_sd_writel(chip, azx_dev, SD_CTL, 0); | 450 | azx_sd_writel(chip, azx_dev, SD_CTL, 0); |
451 | azx_dev->bufsize = 0; | 451 | azx_dev->bufsize = 0; |
452 | azx_dev->period_bytes = 0; | 452 | azx_dev->period_bytes = 0; |
453 | azx_dev->format_val = 0; | 453 | azx_dev->format_val = 0; |
454 | } | 454 | } |
455 | 455 | ||
456 | snd_hda_codec_cleanup(apcm->codec, hinfo, substream); | 456 | snd_hda_codec_cleanup(apcm->codec, hinfo, substream); |
457 | 457 | ||
458 | err = chip->ops->substream_free_pages(chip, substream); | 458 | err = chip->ops->substream_free_pages(chip, substream); |
459 | azx_dev->prepared = 0; | 459 | azx_dev->prepared = 0; |
460 | dsp_unlock(azx_dev); | 460 | dsp_unlock(azx_dev); |
461 | return err; | 461 | return err; |
462 | } | 462 | } |
463 | 463 | ||
464 | static int azx_pcm_prepare(struct snd_pcm_substream *substream) | 464 | static int azx_pcm_prepare(struct snd_pcm_substream *substream) |
465 | { | 465 | { |
466 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | 466 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
467 | struct azx *chip = apcm->chip; | 467 | struct azx *chip = apcm->chip; |
468 | struct azx_dev *azx_dev = get_azx_dev(substream); | 468 | struct azx_dev *azx_dev = get_azx_dev(substream); |
469 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | 469 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; |
470 | struct snd_pcm_runtime *runtime = substream->runtime; | 470 | struct snd_pcm_runtime *runtime = substream->runtime; |
471 | unsigned int bufsize, period_bytes, format_val, stream_tag; | 471 | unsigned int bufsize, period_bytes, format_val, stream_tag; |
472 | int err; | 472 | int err; |
473 | struct hda_spdif_out *spdif = | 473 | struct hda_spdif_out *spdif = |
474 | snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid); | 474 | snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid); |
475 | unsigned short ctls = spdif ? spdif->ctls : 0; | 475 | unsigned short ctls = spdif ? spdif->ctls : 0; |
476 | 476 | ||
477 | dsp_lock(azx_dev); | 477 | dsp_lock(azx_dev); |
478 | if (dsp_is_locked(azx_dev)) { | 478 | if (dsp_is_locked(azx_dev)) { |
479 | err = -EBUSY; | 479 | err = -EBUSY; |
480 | goto unlock; | 480 | goto unlock; |
481 | } | 481 | } |
482 | 482 | ||
483 | azx_stream_reset(chip, azx_dev); | 483 | azx_stream_reset(chip, azx_dev); |
484 | format_val = snd_hda_calc_stream_format(runtime->rate, | 484 | format_val = snd_hda_calc_stream_format(runtime->rate, |
485 | runtime->channels, | 485 | runtime->channels, |
486 | runtime->format, | 486 | runtime->format, |
487 | hinfo->maxbps, | 487 | hinfo->maxbps, |
488 | ctls); | 488 | ctls); |
489 | if (!format_val) { | 489 | if (!format_val) { |
490 | dev_err(chip->card->dev, | 490 | dev_err(chip->card->dev, |
491 | "invalid format_val, rate=%d, ch=%d, format=%d\n", | 491 | "invalid format_val, rate=%d, ch=%d, format=%d\n", |
492 | runtime->rate, runtime->channels, runtime->format); | 492 | runtime->rate, runtime->channels, runtime->format); |
493 | err = -EINVAL; | 493 | err = -EINVAL; |
494 | goto unlock; | 494 | goto unlock; |
495 | } | 495 | } |
496 | 496 | ||
497 | bufsize = snd_pcm_lib_buffer_bytes(substream); | 497 | bufsize = snd_pcm_lib_buffer_bytes(substream); |
498 | period_bytes = snd_pcm_lib_period_bytes(substream); | 498 | period_bytes = snd_pcm_lib_period_bytes(substream); |
499 | 499 | ||
500 | dev_dbg(chip->card->dev, "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n", | 500 | dev_dbg(chip->card->dev, "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n", |
501 | bufsize, format_val); | 501 | bufsize, format_val); |
502 | 502 | ||
503 | if (bufsize != azx_dev->bufsize || | 503 | if (bufsize != azx_dev->bufsize || |
504 | period_bytes != azx_dev->period_bytes || | 504 | period_bytes != azx_dev->period_bytes || |
505 | format_val != azx_dev->format_val || | 505 | format_val != azx_dev->format_val || |
506 | runtime->no_period_wakeup != azx_dev->no_period_wakeup) { | 506 | runtime->no_period_wakeup != azx_dev->no_period_wakeup) { |
507 | azx_dev->bufsize = bufsize; | 507 | azx_dev->bufsize = bufsize; |
508 | azx_dev->period_bytes = period_bytes; | 508 | azx_dev->period_bytes = period_bytes; |
509 | azx_dev->format_val = format_val; | 509 | azx_dev->format_val = format_val; |
510 | azx_dev->no_period_wakeup = runtime->no_period_wakeup; | 510 | azx_dev->no_period_wakeup = runtime->no_period_wakeup; |
511 | err = azx_setup_periods(chip, substream, azx_dev); | 511 | err = azx_setup_periods(chip, substream, azx_dev); |
512 | if (err < 0) | 512 | if (err < 0) |
513 | goto unlock; | 513 | goto unlock; |
514 | } | 514 | } |
515 | 515 | ||
516 | /* when LPIB delay correction gives a small negative value, | 516 | /* when LPIB delay correction gives a small negative value, |
517 | * we ignore it; currently set the threshold statically to | 517 | * we ignore it; currently set the threshold statically to |
518 | * 64 frames | 518 | * 64 frames |
519 | */ | 519 | */ |
520 | if (runtime->period_size > 64) | 520 | if (runtime->period_size > 64) |
521 | azx_dev->delay_negative_threshold = -frames_to_bytes(runtime, 64); | 521 | azx_dev->delay_negative_threshold = -frames_to_bytes(runtime, 64); |
522 | else | 522 | else |
523 | azx_dev->delay_negative_threshold = 0; | 523 | azx_dev->delay_negative_threshold = 0; |
524 | 524 | ||
525 | /* wallclk has 24Mhz clock source */ | 525 | /* wallclk has 24Mhz clock source */ |
526 | azx_dev->period_wallclk = (((runtime->period_size * 24000) / | 526 | azx_dev->period_wallclk = (((runtime->period_size * 24000) / |
527 | runtime->rate) * 1000); | 527 | runtime->rate) * 1000); |
528 | azx_setup_controller(chip, azx_dev); | 528 | azx_setup_controller(chip, azx_dev); |
529 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | 529 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
530 | azx_dev->fifo_size = | 530 | azx_dev->fifo_size = |
531 | azx_sd_readw(chip, azx_dev, SD_FIFOSIZE) + 1; | 531 | azx_sd_readw(chip, azx_dev, SD_FIFOSIZE) + 1; |
532 | else | 532 | else |
533 | azx_dev->fifo_size = 0; | 533 | azx_dev->fifo_size = 0; |
534 | 534 | ||
535 | stream_tag = azx_dev->stream_tag; | 535 | stream_tag = azx_dev->stream_tag; |
536 | /* CA-IBG chips need the playback stream starting from 1 */ | 536 | /* CA-IBG chips need the playback stream starting from 1 */ |
537 | if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) && | 537 | if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) && |
538 | stream_tag > chip->capture_streams) | 538 | stream_tag > chip->capture_streams) |
539 | stream_tag -= chip->capture_streams; | 539 | stream_tag -= chip->capture_streams; |
540 | err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag, | 540 | err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag, |
541 | azx_dev->format_val, substream); | 541 | azx_dev->format_val, substream); |
542 | 542 | ||
543 | unlock: | 543 | unlock: |
544 | if (!err) | 544 | if (!err) |
545 | azx_dev->prepared = 1; | 545 | azx_dev->prepared = 1; |
546 | dsp_unlock(azx_dev); | 546 | dsp_unlock(azx_dev); |
547 | return err; | 547 | return err; |
548 | } | 548 | } |
549 | 549 | ||
550 | static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) | 550 | static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) |
551 | { | 551 | { |
552 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | 552 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
553 | struct azx *chip = apcm->chip; | 553 | struct azx *chip = apcm->chip; |
554 | struct azx_dev *azx_dev; | 554 | struct azx_dev *azx_dev; |
555 | struct snd_pcm_substream *s; | 555 | struct snd_pcm_substream *s; |
556 | int rstart = 0, start, nsync = 0, sbits = 0; | 556 | int rstart = 0, start, nsync = 0, sbits = 0; |
557 | int nwait, timeout; | 557 | int nwait, timeout; |
558 | 558 | ||
559 | azx_dev = get_azx_dev(substream); | 559 | azx_dev = get_azx_dev(substream); |
560 | trace_azx_pcm_trigger(chip, azx_dev, cmd); | 560 | trace_azx_pcm_trigger(chip, azx_dev, cmd); |
561 | 561 | ||
562 | if (dsp_is_locked(azx_dev) || !azx_dev->prepared) | 562 | if (dsp_is_locked(azx_dev) || !azx_dev->prepared) |
563 | return -EPIPE; | 563 | return -EPIPE; |
564 | 564 | ||
565 | switch (cmd) { | 565 | switch (cmd) { |
566 | case SNDRV_PCM_TRIGGER_START: | 566 | case SNDRV_PCM_TRIGGER_START: |
567 | rstart = 1; | 567 | rstart = 1; |
568 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | 568 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
569 | case SNDRV_PCM_TRIGGER_RESUME: | 569 | case SNDRV_PCM_TRIGGER_RESUME: |
570 | start = 1; | 570 | start = 1; |
571 | break; | 571 | break; |
572 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | 572 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
573 | case SNDRV_PCM_TRIGGER_SUSPEND: | 573 | case SNDRV_PCM_TRIGGER_SUSPEND: |
574 | case SNDRV_PCM_TRIGGER_STOP: | 574 | case SNDRV_PCM_TRIGGER_STOP: |
575 | start = 0; | 575 | start = 0; |
576 | break; | 576 | break; |
577 | default: | 577 | default: |
578 | return -EINVAL; | 578 | return -EINVAL; |
579 | } | 579 | } |
580 | 580 | ||
581 | snd_pcm_group_for_each_entry(s, substream) { | 581 | snd_pcm_group_for_each_entry(s, substream) { |
582 | if (s->pcm->card != substream->pcm->card) | 582 | if (s->pcm->card != substream->pcm->card) |
583 | continue; | 583 | continue; |
584 | azx_dev = get_azx_dev(s); | 584 | azx_dev = get_azx_dev(s); |
585 | sbits |= 1 << azx_dev->index; | 585 | sbits |= 1 << azx_dev->index; |
586 | nsync++; | 586 | nsync++; |
587 | snd_pcm_trigger_done(s, substream); | 587 | snd_pcm_trigger_done(s, substream); |
588 | } | 588 | } |
589 | 589 | ||
590 | spin_lock(&chip->reg_lock); | 590 | spin_lock(&chip->reg_lock); |
591 | 591 | ||
592 | /* first, set SYNC bits of corresponding streams */ | 592 | /* first, set SYNC bits of corresponding streams */ |
593 | if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC) | 593 | if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC) |
594 | azx_writel(chip, OLD_SSYNC, | 594 | azx_writel(chip, OLD_SSYNC, |
595 | azx_readl(chip, OLD_SSYNC) | sbits); | 595 | azx_readl(chip, OLD_SSYNC) | sbits); |
596 | else | 596 | else |
597 | azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits); | 597 | azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits); |
598 | 598 | ||
599 | snd_pcm_group_for_each_entry(s, substream) { | 599 | snd_pcm_group_for_each_entry(s, substream) { |
600 | if (s->pcm->card != substream->pcm->card) | 600 | if (s->pcm->card != substream->pcm->card) |
601 | continue; | 601 | continue; |
602 | azx_dev = get_azx_dev(s); | 602 | azx_dev = get_azx_dev(s); |
603 | if (start) { | 603 | if (start) { |
604 | azx_dev->start_wallclk = azx_readl(chip, WALLCLK); | 604 | azx_dev->start_wallclk = azx_readl(chip, WALLCLK); |
605 | if (!rstart) | 605 | if (!rstart) |
606 | azx_dev->start_wallclk -= | 606 | azx_dev->start_wallclk -= |
607 | azx_dev->period_wallclk; | 607 | azx_dev->period_wallclk; |
608 | azx_stream_start(chip, azx_dev); | 608 | azx_stream_start(chip, azx_dev); |
609 | } else { | 609 | } else { |
610 | azx_stream_stop(chip, azx_dev); | 610 | azx_stream_stop(chip, azx_dev); |
611 | } | 611 | } |
612 | azx_dev->running = start; | 612 | azx_dev->running = start; |
613 | } | 613 | } |
614 | spin_unlock(&chip->reg_lock); | 614 | spin_unlock(&chip->reg_lock); |
615 | if (start) { | 615 | if (start) { |
616 | /* wait until all FIFOs get ready */ | 616 | /* wait until all FIFOs get ready */ |
617 | for (timeout = 5000; timeout; timeout--) { | 617 | for (timeout = 5000; timeout; timeout--) { |
618 | nwait = 0; | 618 | nwait = 0; |
619 | snd_pcm_group_for_each_entry(s, substream) { | 619 | snd_pcm_group_for_each_entry(s, substream) { |
620 | if (s->pcm->card != substream->pcm->card) | 620 | if (s->pcm->card != substream->pcm->card) |
621 | continue; | 621 | continue; |
622 | azx_dev = get_azx_dev(s); | 622 | azx_dev = get_azx_dev(s); |
623 | if (!(azx_sd_readb(chip, azx_dev, SD_STS) & | 623 | if (!(azx_sd_readb(chip, azx_dev, SD_STS) & |
624 | SD_STS_FIFO_READY)) | 624 | SD_STS_FIFO_READY)) |
625 | nwait++; | 625 | nwait++; |
626 | } | 626 | } |
627 | if (!nwait) | 627 | if (!nwait) |
628 | break; | 628 | break; |
629 | cpu_relax(); | 629 | cpu_relax(); |
630 | } | 630 | } |
631 | } else { | 631 | } else { |
632 | /* wait until all RUN bits are cleared */ | 632 | /* wait until all RUN bits are cleared */ |
633 | for (timeout = 5000; timeout; timeout--) { | 633 | for (timeout = 5000; timeout; timeout--) { |
634 | nwait = 0; | 634 | nwait = 0; |
635 | snd_pcm_group_for_each_entry(s, substream) { | 635 | snd_pcm_group_for_each_entry(s, substream) { |
636 | if (s->pcm->card != substream->pcm->card) | 636 | if (s->pcm->card != substream->pcm->card) |
637 | continue; | 637 | continue; |
638 | azx_dev = get_azx_dev(s); | 638 | azx_dev = get_azx_dev(s); |
639 | if (azx_sd_readb(chip, azx_dev, SD_CTL) & | 639 | if (azx_sd_readb(chip, azx_dev, SD_CTL) & |
640 | SD_CTL_DMA_START) | 640 | SD_CTL_DMA_START) |
641 | nwait++; | 641 | nwait++; |
642 | } | 642 | } |
643 | if (!nwait) | 643 | if (!nwait) |
644 | break; | 644 | break; |
645 | cpu_relax(); | 645 | cpu_relax(); |
646 | } | 646 | } |
647 | } | 647 | } |
648 | spin_lock(&chip->reg_lock); | 648 | spin_lock(&chip->reg_lock); |
649 | /* reset SYNC bits */ | 649 | /* reset SYNC bits */ |
650 | if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC) | 650 | if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC) |
651 | azx_writel(chip, OLD_SSYNC, | 651 | azx_writel(chip, OLD_SSYNC, |
652 | azx_readl(chip, OLD_SSYNC) & ~sbits); | 652 | azx_readl(chip, OLD_SSYNC) & ~sbits); |
653 | else | 653 | else |
654 | azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits); | 654 | azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits); |
655 | if (start) { | 655 | if (start) { |
656 | azx_timecounter_init(substream, 0, 0); | 656 | azx_timecounter_init(substream, 0, 0); |
657 | if (nsync > 1) { | 657 | if (nsync > 1) { |
658 | cycle_t cycle_last; | 658 | cycle_t cycle_last; |
659 | 659 | ||
660 | /* same start cycle for master and group */ | 660 | /* same start cycle for master and group */ |
661 | azx_dev = get_azx_dev(substream); | 661 | azx_dev = get_azx_dev(substream); |
662 | cycle_last = azx_dev->azx_tc.cycle_last; | 662 | cycle_last = azx_dev->azx_tc.cycle_last; |
663 | 663 | ||
664 | snd_pcm_group_for_each_entry(s, substream) { | 664 | snd_pcm_group_for_each_entry(s, substream) { |
665 | if (s->pcm->card != substream->pcm->card) | 665 | if (s->pcm->card != substream->pcm->card) |
666 | continue; | 666 | continue; |
667 | azx_timecounter_init(s, 1, cycle_last); | 667 | azx_timecounter_init(s, 1, cycle_last); |
668 | } | 668 | } |
669 | } | 669 | } |
670 | } | 670 | } |
671 | spin_unlock(&chip->reg_lock); | 671 | spin_unlock(&chip->reg_lock); |
672 | return 0; | 672 | return 0; |
673 | } | 673 | } |
674 | 674 | ||
675 | /* get the current DMA position with correction on VIA chips */ | 675 | /* get the current DMA position with correction on VIA chips */ |
676 | static unsigned int azx_via_get_position(struct azx *chip, | 676 | static unsigned int azx_via_get_position(struct azx *chip, |
677 | struct azx_dev *azx_dev) | 677 | struct azx_dev *azx_dev) |
678 | { | 678 | { |
679 | unsigned int link_pos, mini_pos, bound_pos; | 679 | unsigned int link_pos, mini_pos, bound_pos; |
680 | unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; | 680 | unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; |
681 | unsigned int fifo_size; | 681 | unsigned int fifo_size; |
682 | 682 | ||
683 | link_pos = azx_sd_readl(chip, azx_dev, SD_LPIB); | 683 | link_pos = azx_sd_readl(chip, azx_dev, SD_LPIB); |
684 | if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | 684 | if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
685 | /* Playback, no problem using link position */ | 685 | /* Playback, no problem using link position */ |
686 | return link_pos; | 686 | return link_pos; |
687 | } | 687 | } |
688 | 688 | ||
689 | /* Capture */ | 689 | /* Capture */ |
690 | /* For new chipset, | 690 | /* For new chipset, |
691 | * use mod to get the DMA position just like old chipset | 691 | * use mod to get the DMA position just like old chipset |
692 | */ | 692 | */ |
693 | mod_dma_pos = le32_to_cpu(*azx_dev->posbuf); | 693 | mod_dma_pos = le32_to_cpu(*azx_dev->posbuf); |
694 | mod_dma_pos %= azx_dev->period_bytes; | 694 | mod_dma_pos %= azx_dev->period_bytes; |
695 | 695 | ||
696 | /* azx_dev->fifo_size can't get FIFO size of in stream. | 696 | /* azx_dev->fifo_size can't get FIFO size of in stream. |
697 | * Get from base address + offset. | 697 | * Get from base address + offset. |
698 | */ | 698 | */ |
699 | fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET); | 699 | fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET); |
700 | 700 | ||
701 | if (azx_dev->insufficient) { | 701 | if (azx_dev->insufficient) { |
702 | /* Link position never gather than FIFO size */ | 702 | /* Link position never gather than FIFO size */ |
703 | if (link_pos <= fifo_size) | 703 | if (link_pos <= fifo_size) |
704 | return 0; | 704 | return 0; |
705 | 705 | ||
706 | azx_dev->insufficient = 0; | 706 | azx_dev->insufficient = 0; |
707 | } | 707 | } |
708 | 708 | ||
709 | if (link_pos <= fifo_size) | 709 | if (link_pos <= fifo_size) |
710 | mini_pos = azx_dev->bufsize + link_pos - fifo_size; | 710 | mini_pos = azx_dev->bufsize + link_pos - fifo_size; |
711 | else | 711 | else |
712 | mini_pos = link_pos - fifo_size; | 712 | mini_pos = link_pos - fifo_size; |
713 | 713 | ||
714 | /* Find nearest previous boudary */ | 714 | /* Find nearest previous boudary */ |
715 | mod_mini_pos = mini_pos % azx_dev->period_bytes; | 715 | mod_mini_pos = mini_pos % azx_dev->period_bytes; |
716 | mod_link_pos = link_pos % azx_dev->period_bytes; | 716 | mod_link_pos = link_pos % azx_dev->period_bytes; |
717 | if (mod_link_pos >= fifo_size) | 717 | if (mod_link_pos >= fifo_size) |
718 | bound_pos = link_pos - mod_link_pos; | 718 | bound_pos = link_pos - mod_link_pos; |
719 | else if (mod_dma_pos >= mod_mini_pos) | 719 | else if (mod_dma_pos >= mod_mini_pos) |
720 | bound_pos = mini_pos - mod_mini_pos; | 720 | bound_pos = mini_pos - mod_mini_pos; |
721 | else { | 721 | else { |
722 | bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes; | 722 | bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes; |
723 | if (bound_pos >= azx_dev->bufsize) | 723 | if (bound_pos >= azx_dev->bufsize) |
724 | bound_pos = 0; | 724 | bound_pos = 0; |
725 | } | 725 | } |
726 | 726 | ||
727 | /* Calculate real DMA position we want */ | 727 | /* Calculate real DMA position we want */ |
728 | return bound_pos + mod_dma_pos; | 728 | return bound_pos + mod_dma_pos; |
729 | } | 729 | } |
730 | 730 | ||
731 | unsigned int azx_get_position(struct azx *chip, | 731 | unsigned int azx_get_position(struct azx *chip, |
732 | struct azx_dev *azx_dev, | 732 | struct azx_dev *azx_dev, |
733 | bool with_check) | 733 | bool with_check) |
734 | { | 734 | { |
735 | struct snd_pcm_substream *substream = azx_dev->substream; | 735 | struct snd_pcm_substream *substream = azx_dev->substream; |
736 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | 736 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
737 | unsigned int pos; | 737 | unsigned int pos; |
738 | int stream = substream->stream; | 738 | int stream = substream->stream; |
739 | struct hda_pcm_stream *hinfo = apcm->hinfo[stream]; | 739 | struct hda_pcm_stream *hinfo = apcm->hinfo[stream]; |
740 | int delay = 0; | 740 | int delay = 0; |
741 | 741 | ||
742 | switch (chip->position_fix[stream]) { | 742 | switch (chip->position_fix[stream]) { |
743 | case POS_FIX_LPIB: | 743 | case POS_FIX_LPIB: |
744 | /* read LPIB */ | 744 | /* read LPIB */ |
745 | pos = azx_sd_readl(chip, azx_dev, SD_LPIB); | 745 | pos = azx_sd_readl(chip, azx_dev, SD_LPIB); |
746 | break; | 746 | break; |
747 | case POS_FIX_VIACOMBO: | 747 | case POS_FIX_VIACOMBO: |
748 | pos = azx_via_get_position(chip, azx_dev); | 748 | pos = azx_via_get_position(chip, azx_dev); |
749 | break; | 749 | break; |
750 | default: | 750 | default: |
751 | /* use the position buffer */ | 751 | /* use the position buffer */ |
752 | pos = le32_to_cpu(*azx_dev->posbuf); | 752 | pos = le32_to_cpu(*azx_dev->posbuf); |
753 | if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) { | 753 | if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) { |
754 | if (!pos || pos == (u32)-1) { | 754 | if (!pos || pos == (u32)-1) { |
755 | dev_info(chip->card->dev, | 755 | dev_info(chip->card->dev, |
756 | "Invalid position buffer, using LPIB read method instead.\n"); | 756 | "Invalid position buffer, using LPIB read method instead.\n"); |
757 | chip->position_fix[stream] = POS_FIX_LPIB; | 757 | chip->position_fix[stream] = POS_FIX_LPIB; |
758 | pos = azx_sd_readl(chip, azx_dev, SD_LPIB); | 758 | pos = azx_sd_readl(chip, azx_dev, SD_LPIB); |
759 | } else | 759 | } else |
760 | chip->position_fix[stream] = POS_FIX_POSBUF; | 760 | chip->position_fix[stream] = POS_FIX_POSBUF; |
761 | } | 761 | } |
762 | break; | 762 | break; |
763 | } | 763 | } |
764 | 764 | ||
765 | if (pos >= azx_dev->bufsize) | 765 | if (pos >= azx_dev->bufsize) |
766 | pos = 0; | 766 | pos = 0; |
767 | 767 | ||
768 | /* calculate runtime delay from LPIB */ | 768 | /* calculate runtime delay from LPIB */ |
769 | if (substream->runtime && | 769 | if (substream->runtime && |
770 | chip->position_fix[stream] == POS_FIX_POSBUF && | 770 | chip->position_fix[stream] == POS_FIX_POSBUF && |
771 | (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { | 771 | (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { |
772 | unsigned int lpib_pos = azx_sd_readl(chip, azx_dev, SD_LPIB); | 772 | unsigned int lpib_pos = azx_sd_readl(chip, azx_dev, SD_LPIB); |
773 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) | 773 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) |
774 | delay = pos - lpib_pos; | 774 | delay = pos - lpib_pos; |
775 | else | 775 | else |
776 | delay = lpib_pos - pos; | 776 | delay = lpib_pos - pos; |
777 | if (delay < 0) { | 777 | if (delay < 0) { |
778 | if (delay >= azx_dev->delay_negative_threshold) | 778 | if (delay >= azx_dev->delay_negative_threshold) |
779 | delay = 0; | 779 | delay = 0; |
780 | else | 780 | else |
781 | delay += azx_dev->bufsize; | 781 | delay += azx_dev->bufsize; |
782 | } | 782 | } |
783 | if (delay >= azx_dev->period_bytes) { | 783 | if (delay >= azx_dev->period_bytes) { |
784 | dev_info(chip->card->dev, | 784 | dev_info(chip->card->dev, |
785 | "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", | 785 | "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", |
786 | delay, azx_dev->period_bytes); | 786 | delay, azx_dev->period_bytes); |
787 | delay = 0; | 787 | delay = 0; |
788 | chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; | 788 | chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; |
789 | } | 789 | } |
790 | delay = bytes_to_frames(substream->runtime, delay); | 790 | delay = bytes_to_frames(substream->runtime, delay); |
791 | } | 791 | } |
792 | 792 | ||
793 | if (substream->runtime) { | 793 | if (substream->runtime) { |
794 | if (hinfo->ops.get_delay) | 794 | if (hinfo->ops.get_delay) |
795 | delay += hinfo->ops.get_delay(hinfo, apcm->codec, | 795 | delay += hinfo->ops.get_delay(hinfo, apcm->codec, |
796 | substream); | 796 | substream); |
797 | substream->runtime->delay = delay; | 797 | substream->runtime->delay = delay; |
798 | } | 798 | } |
799 | 799 | ||
800 | trace_azx_get_position(chip, azx_dev, pos, delay); | 800 | trace_azx_get_position(chip, azx_dev, pos, delay); |
801 | return pos; | 801 | return pos; |
802 | } | 802 | } |
803 | EXPORT_SYMBOL_GPL(azx_get_position); | 803 | EXPORT_SYMBOL_GPL(azx_get_position); |
804 | 804 | ||
805 | static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream) | 805 | static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream) |
806 | { | 806 | { |
807 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | 807 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
808 | struct azx *chip = apcm->chip; | 808 | struct azx *chip = apcm->chip; |
809 | struct azx_dev *azx_dev = get_azx_dev(substream); | 809 | struct azx_dev *azx_dev = get_azx_dev(substream); |
810 | return bytes_to_frames(substream->runtime, | 810 | return bytes_to_frames(substream->runtime, |
811 | azx_get_position(chip, azx_dev, false)); | 811 | azx_get_position(chip, azx_dev, false)); |
812 | } | 812 | } |
813 | 813 | ||
814 | static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream, | 814 | static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream, |
815 | struct timespec *ts) | 815 | struct timespec *ts) |
816 | { | 816 | { |
817 | struct azx_dev *azx_dev = get_azx_dev(substream); | 817 | struct azx_dev *azx_dev = get_azx_dev(substream); |
818 | u64 nsec; | 818 | u64 nsec; |
819 | 819 | ||
820 | nsec = timecounter_read(&azx_dev->azx_tc); | 820 | nsec = timecounter_read(&azx_dev->azx_tc); |
821 | nsec = div_u64(nsec, 3); /* can be optimized */ | 821 | nsec = div_u64(nsec, 3); /* can be optimized */ |
822 | nsec = azx_adjust_codec_delay(substream, nsec); | 822 | nsec = azx_adjust_codec_delay(substream, nsec); |
823 | 823 | ||
824 | *ts = ns_to_timespec(nsec); | 824 | *ts = ns_to_timespec(nsec); |
825 | 825 | ||
826 | return 0; | 826 | return 0; |
827 | } | 827 | } |
828 | 828 | ||
829 | static struct snd_pcm_hardware azx_pcm_hw = { | 829 | static struct snd_pcm_hardware azx_pcm_hw = { |
830 | .info = (SNDRV_PCM_INFO_MMAP | | 830 | .info = (SNDRV_PCM_INFO_MMAP | |
831 | SNDRV_PCM_INFO_INTERLEAVED | | 831 | SNDRV_PCM_INFO_INTERLEAVED | |
832 | SNDRV_PCM_INFO_BLOCK_TRANSFER | | 832 | SNDRV_PCM_INFO_BLOCK_TRANSFER | |
833 | SNDRV_PCM_INFO_MMAP_VALID | | 833 | SNDRV_PCM_INFO_MMAP_VALID | |
834 | /* No full-resume yet implemented */ | 834 | /* No full-resume yet implemented */ |
835 | /* SNDRV_PCM_INFO_RESUME |*/ | 835 | /* SNDRV_PCM_INFO_RESUME |*/ |
836 | SNDRV_PCM_INFO_PAUSE | | 836 | SNDRV_PCM_INFO_PAUSE | |
837 | SNDRV_PCM_INFO_SYNC_START | | 837 | SNDRV_PCM_INFO_SYNC_START | |
838 | SNDRV_PCM_INFO_HAS_WALL_CLOCK | | 838 | SNDRV_PCM_INFO_HAS_WALL_CLOCK | |
839 | SNDRV_PCM_INFO_NO_PERIOD_WAKEUP), | 839 | SNDRV_PCM_INFO_NO_PERIOD_WAKEUP), |
840 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | 840 | .formats = SNDRV_PCM_FMTBIT_S16_LE, |
841 | .rates = SNDRV_PCM_RATE_48000, | 841 | .rates = SNDRV_PCM_RATE_48000, |
842 | .rate_min = 48000, | 842 | .rate_min = 48000, |
843 | .rate_max = 48000, | 843 | .rate_max = 48000, |
844 | .channels_min = 2, | 844 | .channels_min = 2, |
845 | .channels_max = 2, | 845 | .channels_max = 2, |
846 | .buffer_bytes_max = AZX_MAX_BUF_SIZE, | 846 | .buffer_bytes_max = AZX_MAX_BUF_SIZE, |
847 | .period_bytes_min = 128, | 847 | .period_bytes_min = 128, |
848 | .period_bytes_max = AZX_MAX_BUF_SIZE / 2, | 848 | .period_bytes_max = AZX_MAX_BUF_SIZE / 2, |
849 | .periods_min = 2, | 849 | .periods_min = 2, |
850 | .periods_max = AZX_MAX_FRAG, | 850 | .periods_max = AZX_MAX_FRAG, |
851 | .fifo_size = 0, | 851 | .fifo_size = 0, |
852 | }; | 852 | }; |
853 | 853 | ||
854 | static int azx_pcm_open(struct snd_pcm_substream *substream) | 854 | static int azx_pcm_open(struct snd_pcm_substream *substream) |
855 | { | 855 | { |
856 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | 856 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
857 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | 857 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; |
858 | struct azx *chip = apcm->chip; | 858 | struct azx *chip = apcm->chip; |
859 | struct azx_dev *azx_dev; | 859 | struct azx_dev *azx_dev; |
860 | struct snd_pcm_runtime *runtime = substream->runtime; | 860 | struct snd_pcm_runtime *runtime = substream->runtime; |
861 | unsigned long flags; | 861 | unsigned long flags; |
862 | int err; | 862 | int err; |
863 | int buff_step; | 863 | int buff_step; |
864 | 864 | ||
865 | mutex_lock(&chip->open_mutex); | 865 | mutex_lock(&chip->open_mutex); |
866 | azx_dev = azx_assign_device(chip, substream); | 866 | azx_dev = azx_assign_device(chip, substream); |
867 | if (azx_dev == NULL) { | 867 | if (azx_dev == NULL) { |
868 | mutex_unlock(&chip->open_mutex); | 868 | mutex_unlock(&chip->open_mutex); |
869 | return -EBUSY; | 869 | return -EBUSY; |
870 | } | 870 | } |
871 | runtime->hw = azx_pcm_hw; | 871 | runtime->hw = azx_pcm_hw; |
872 | runtime->hw.channels_min = hinfo->channels_min; | 872 | runtime->hw.channels_min = hinfo->channels_min; |
873 | runtime->hw.channels_max = hinfo->channels_max; | 873 | runtime->hw.channels_max = hinfo->channels_max; |
874 | runtime->hw.formats = hinfo->formats; | 874 | runtime->hw.formats = hinfo->formats; |
875 | runtime->hw.rates = hinfo->rates; | 875 | runtime->hw.rates = hinfo->rates; |
876 | snd_pcm_limit_hw_rates(runtime); | 876 | snd_pcm_limit_hw_rates(runtime); |
877 | snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); | 877 | snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); |
878 | 878 | ||
879 | /* avoid wrap-around with wall-clock */ | 879 | /* avoid wrap-around with wall-clock */ |
880 | snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME, | 880 | snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME, |
881 | 20, | 881 | 20, |
882 | 178000000); | 882 | 178000000); |
883 | 883 | ||
884 | if (chip->align_buffer_size) | 884 | if (chip->align_buffer_size) |
885 | /* constrain buffer sizes to be multiple of 128 | 885 | /* constrain buffer sizes to be multiple of 128 |
886 | bytes. This is more efficient in terms of memory | 886 | bytes. This is more efficient in terms of memory |
887 | access but isn't required by the HDA spec and | 887 | access but isn't required by the HDA spec and |
888 | prevents users from specifying exact period/buffer | 888 | prevents users from specifying exact period/buffer |
889 | sizes. For example for 44.1kHz, a period size set | 889 | sizes. For example for 44.1kHz, a period size set |
890 | to 20ms will be rounded to 19.59ms. */ | 890 | to 20ms will be rounded to 19.59ms. */ |
891 | buff_step = 128; | 891 | buff_step = 128; |
892 | else | 892 | else |
893 | /* Don't enforce steps on buffer sizes, still need to | 893 | /* Don't enforce steps on buffer sizes, still need to |
894 | be multiple of 4 bytes (HDA spec). Tested on Intel | 894 | be multiple of 4 bytes (HDA spec). Tested on Intel |
895 | HDA controllers, may not work on all devices where | 895 | HDA controllers, may not work on all devices where |
896 | option needs to be disabled */ | 896 | option needs to be disabled */ |
897 | buff_step = 4; | 897 | buff_step = 4; |
898 | 898 | ||
899 | snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, | 899 | snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, |
900 | buff_step); | 900 | buff_step); |
901 | snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, | 901 | snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, |
902 | buff_step); | 902 | buff_step); |
903 | snd_hda_power_up_d3wait(apcm->codec); | 903 | snd_hda_power_up_d3wait(apcm->codec); |
904 | err = hinfo->ops.open(hinfo, apcm->codec, substream); | 904 | err = hinfo->ops.open(hinfo, apcm->codec, substream); |
905 | if (err < 0) { | 905 | if (err < 0) { |
906 | azx_release_device(azx_dev); | 906 | azx_release_device(azx_dev); |
907 | snd_hda_power_down(apcm->codec); | 907 | snd_hda_power_down(apcm->codec); |
908 | mutex_unlock(&chip->open_mutex); | 908 | mutex_unlock(&chip->open_mutex); |
909 | return err; | 909 | return err; |
910 | } | 910 | } |
911 | snd_pcm_limit_hw_rates(runtime); | 911 | snd_pcm_limit_hw_rates(runtime); |
912 | /* sanity check */ | 912 | /* sanity check */ |
913 | if (snd_BUG_ON(!runtime->hw.channels_min) || | 913 | if (snd_BUG_ON(!runtime->hw.channels_min) || |
914 | snd_BUG_ON(!runtime->hw.channels_max) || | 914 | snd_BUG_ON(!runtime->hw.channels_max) || |
915 | snd_BUG_ON(!runtime->hw.formats) || | 915 | snd_BUG_ON(!runtime->hw.formats) || |
916 | snd_BUG_ON(!runtime->hw.rates)) { | 916 | snd_BUG_ON(!runtime->hw.rates)) { |
917 | azx_release_device(azx_dev); | 917 | azx_release_device(azx_dev); |
918 | hinfo->ops.close(hinfo, apcm->codec, substream); | 918 | hinfo->ops.close(hinfo, apcm->codec, substream); |
919 | snd_hda_power_down(apcm->codec); | 919 | snd_hda_power_down(apcm->codec); |
920 | mutex_unlock(&chip->open_mutex); | 920 | mutex_unlock(&chip->open_mutex); |
921 | return -EINVAL; | 921 | return -EINVAL; |
922 | } | 922 | } |
923 | 923 | ||
924 | /* disable WALLCLOCK timestamps for capture streams | 924 | /* disable WALLCLOCK timestamps for capture streams |
925 | until we figure out how to handle digital inputs */ | 925 | until we figure out how to handle digital inputs */ |
926 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | 926 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) |
927 | runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; | 927 | runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; |
928 | 928 | ||
929 | spin_lock_irqsave(&chip->reg_lock, flags); | 929 | spin_lock_irqsave(&chip->reg_lock, flags); |
930 | azx_dev->substream = substream; | 930 | azx_dev->substream = substream; |
931 | azx_dev->running = 0; | 931 | azx_dev->running = 0; |
932 | spin_unlock_irqrestore(&chip->reg_lock, flags); | 932 | spin_unlock_irqrestore(&chip->reg_lock, flags); |
933 | 933 | ||
934 | runtime->private_data = azx_dev; | 934 | runtime->private_data = azx_dev; |
935 | snd_pcm_set_sync(substream); | 935 | snd_pcm_set_sync(substream); |
936 | mutex_unlock(&chip->open_mutex); | 936 | mutex_unlock(&chip->open_mutex); |
937 | return 0; | 937 | return 0; |
938 | } | 938 | } |
939 | 939 | ||
940 | static int azx_pcm_mmap(struct snd_pcm_substream *substream, | 940 | static int azx_pcm_mmap(struct snd_pcm_substream *substream, |
941 | struct vm_area_struct *area) | 941 | struct vm_area_struct *area) |
942 | { | 942 | { |
943 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | 943 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
944 | struct azx *chip = apcm->chip; | 944 | struct azx *chip = apcm->chip; |
945 | if (chip->ops->pcm_mmap_prepare) | 945 | if (chip->ops->pcm_mmap_prepare) |
946 | chip->ops->pcm_mmap_prepare(substream, area); | 946 | chip->ops->pcm_mmap_prepare(substream, area); |
947 | return snd_pcm_lib_default_mmap(substream, area); | 947 | return snd_pcm_lib_default_mmap(substream, area); |
948 | } | 948 | } |
949 | 949 | ||
950 | static struct snd_pcm_ops azx_pcm_ops = { | 950 | static struct snd_pcm_ops azx_pcm_ops = { |
951 | .open = azx_pcm_open, | 951 | .open = azx_pcm_open, |
952 | .close = azx_pcm_close, | 952 | .close = azx_pcm_close, |
953 | .ioctl = snd_pcm_lib_ioctl, | 953 | .ioctl = snd_pcm_lib_ioctl, |
954 | .hw_params = azx_pcm_hw_params, | 954 | .hw_params = azx_pcm_hw_params, |
955 | .hw_free = azx_pcm_hw_free, | 955 | .hw_free = azx_pcm_hw_free, |
956 | .prepare = azx_pcm_prepare, | 956 | .prepare = azx_pcm_prepare, |
957 | .trigger = azx_pcm_trigger, | 957 | .trigger = azx_pcm_trigger, |
958 | .pointer = azx_pcm_pointer, | 958 | .pointer = azx_pcm_pointer, |
959 | .wall_clock = azx_get_wallclock_tstamp, | 959 | .wall_clock = azx_get_wallclock_tstamp, |
960 | .mmap = azx_pcm_mmap, | 960 | .mmap = azx_pcm_mmap, |
961 | .page = snd_pcm_sgbuf_ops_page, | 961 | .page = snd_pcm_sgbuf_ops_page, |
962 | }; | 962 | }; |
963 | 963 | ||
964 | static void azx_pcm_free(struct snd_pcm *pcm) | 964 | static void azx_pcm_free(struct snd_pcm *pcm) |
965 | { | 965 | { |
966 | struct azx_pcm *apcm = pcm->private_data; | 966 | struct azx_pcm *apcm = pcm->private_data; |
967 | if (apcm) { | 967 | if (apcm) { |
968 | list_del(&apcm->list); | 968 | list_del(&apcm->list); |
969 | kfree(apcm); | 969 | kfree(apcm); |
970 | } | 970 | } |
971 | } | 971 | } |
972 | 972 | ||
973 | #define MAX_PREALLOC_SIZE (32 * 1024 * 1024) | 973 | #define MAX_PREALLOC_SIZE (32 * 1024 * 1024) |
974 | 974 | ||
975 | static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec, | 975 | static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec, |
976 | struct hda_pcm *cpcm) | 976 | struct hda_pcm *cpcm) |
977 | { | 977 | { |
978 | struct azx *chip = bus->private_data; | 978 | struct azx *chip = bus->private_data; |
979 | struct snd_pcm *pcm; | 979 | struct snd_pcm *pcm; |
980 | struct azx_pcm *apcm; | 980 | struct azx_pcm *apcm; |
981 | int pcm_dev = cpcm->device; | 981 | int pcm_dev = cpcm->device; |
982 | unsigned int size; | 982 | unsigned int size; |
983 | int s, err; | 983 | int s, err; |
984 | 984 | ||
985 | list_for_each_entry(apcm, &chip->pcm_list, list) { | 985 | list_for_each_entry(apcm, &chip->pcm_list, list) { |
986 | if (apcm->pcm->device == pcm_dev) { | 986 | if (apcm->pcm->device == pcm_dev) { |
987 | dev_err(chip->card->dev, "PCM %d already exists\n", | 987 | dev_err(chip->card->dev, "PCM %d already exists\n", |
988 | pcm_dev); | 988 | pcm_dev); |
989 | return -EBUSY; | 989 | return -EBUSY; |
990 | } | 990 | } |
991 | } | 991 | } |
992 | err = snd_pcm_new(chip->card, cpcm->name, pcm_dev, | 992 | err = snd_pcm_new(chip->card, cpcm->name, pcm_dev, |
993 | cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams, | 993 | cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams, |
994 | cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams, | 994 | cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams, |
995 | &pcm); | 995 | &pcm); |
996 | if (err < 0) | 996 | if (err < 0) |
997 | return err; | 997 | return err; |
998 | strlcpy(pcm->name, cpcm->name, sizeof(pcm->name)); | 998 | strlcpy(pcm->name, cpcm->name, sizeof(pcm->name)); |
999 | apcm = kzalloc(sizeof(*apcm), GFP_KERNEL); | 999 | apcm = kzalloc(sizeof(*apcm), GFP_KERNEL); |
1000 | if (apcm == NULL) | 1000 | if (apcm == NULL) |
1001 | return -ENOMEM; | 1001 | return -ENOMEM; |
1002 | apcm->chip = chip; | 1002 | apcm->chip = chip; |
1003 | apcm->pcm = pcm; | 1003 | apcm->pcm = pcm; |
1004 | apcm->codec = codec; | 1004 | apcm->codec = codec; |
1005 | pcm->private_data = apcm; | 1005 | pcm->private_data = apcm; |
1006 | pcm->private_free = azx_pcm_free; | 1006 | pcm->private_free = azx_pcm_free; |
1007 | if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM) | 1007 | if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM) |
1008 | pcm->dev_class = SNDRV_PCM_CLASS_MODEM; | 1008 | pcm->dev_class = SNDRV_PCM_CLASS_MODEM; |
1009 | list_add_tail(&apcm->list, &chip->pcm_list); | 1009 | list_add_tail(&apcm->list, &chip->pcm_list); |
1010 | cpcm->pcm = pcm; | 1010 | cpcm->pcm = pcm; |
1011 | for (s = 0; s < 2; s++) { | 1011 | for (s = 0; s < 2; s++) { |
1012 | apcm->hinfo[s] = &cpcm->stream[s]; | 1012 | apcm->hinfo[s] = &cpcm->stream[s]; |
1013 | if (cpcm->stream[s].substreams) | 1013 | if (cpcm->stream[s].substreams) |
1014 | snd_pcm_set_ops(pcm, s, &azx_pcm_ops); | 1014 | snd_pcm_set_ops(pcm, s, &azx_pcm_ops); |
1015 | } | 1015 | } |
1016 | /* buffer pre-allocation */ | 1016 | /* buffer pre-allocation */ |
1017 | size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024; | 1017 | size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024; |
1018 | if (size > MAX_PREALLOC_SIZE) | 1018 | if (size > MAX_PREALLOC_SIZE) |
1019 | size = MAX_PREALLOC_SIZE; | 1019 | size = MAX_PREALLOC_SIZE; |
1020 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG, | 1020 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG, |
1021 | chip->card->dev, | 1021 | chip->card->dev, |
1022 | size, MAX_PREALLOC_SIZE); | 1022 | size, MAX_PREALLOC_SIZE); |
1023 | /* link to codec */ | 1023 | /* link to codec */ |
1024 | pcm->dev = &codec->dev; | 1024 | pcm->dev = &codec->dev; |
1025 | return 0; | 1025 | return 0; |
1026 | } | 1026 | } |
1027 | 1027 | ||
1028 | /* | 1028 | /* |
1029 | * CORB / RIRB interface | 1029 | * CORB / RIRB interface |
1030 | */ | 1030 | */ |
1031 | static int azx_alloc_cmd_io(struct azx *chip) | 1031 | static int azx_alloc_cmd_io(struct azx *chip) |
1032 | { | 1032 | { |
1033 | int err; | 1033 | int err; |
1034 | 1034 | ||
1035 | /* single page (at least 4096 bytes) must suffice for both ringbuffes */ | 1035 | /* single page (at least 4096 bytes) must suffice for both ringbuffes */ |
1036 | err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV, | 1036 | err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV, |
1037 | PAGE_SIZE, &chip->rb); | 1037 | PAGE_SIZE, &chip->rb); |
1038 | if (err < 0) | 1038 | if (err < 0) |
1039 | dev_err(chip->card->dev, "cannot allocate CORB/RIRB\n"); | 1039 | dev_err(chip->card->dev, "cannot allocate CORB/RIRB\n"); |
1040 | return err; | 1040 | return err; |
1041 | } | 1041 | } |
1042 | EXPORT_SYMBOL_GPL(azx_alloc_cmd_io); | 1042 | EXPORT_SYMBOL_GPL(azx_alloc_cmd_io); |
1043 | 1043 | ||
1044 | static void azx_init_cmd_io(struct azx *chip) | 1044 | static void azx_init_cmd_io(struct azx *chip) |
1045 | { | 1045 | { |
1046 | int timeout; | 1046 | int timeout; |
1047 | 1047 | ||
1048 | spin_lock_irq(&chip->reg_lock); | 1048 | spin_lock_irq(&chip->reg_lock); |
1049 | /* CORB set up */ | 1049 | /* CORB set up */ |
1050 | chip->corb.addr = chip->rb.addr; | 1050 | chip->corb.addr = chip->rb.addr; |
1051 | chip->corb.buf = (u32 *)chip->rb.area; | 1051 | chip->corb.buf = (u32 *)chip->rb.area; |
1052 | azx_writel(chip, CORBLBASE, (u32)chip->corb.addr); | 1052 | azx_writel(chip, CORBLBASE, (u32)chip->corb.addr); |
1053 | azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr)); | 1053 | azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr)); |
1054 | 1054 | ||
1055 | /* set the corb size to 256 entries (ULI requires explicitly) */ | 1055 | /* set the corb size to 256 entries (ULI requires explicitly) */ |
1056 | azx_writeb(chip, CORBSIZE, 0x02); | 1056 | azx_writeb(chip, CORBSIZE, 0x02); |
1057 | /* set the corb write pointer to 0 */ | 1057 | /* set the corb write pointer to 0 */ |
1058 | azx_writew(chip, CORBWP, 0); | 1058 | azx_writew(chip, CORBWP, 0); |
1059 | 1059 | ||
1060 | /* reset the corb hw read pointer */ | 1060 | /* reset the corb hw read pointer */ |
1061 | azx_writew(chip, CORBRP, ICH6_CORBRP_RST); | 1061 | azx_writew(chip, CORBRP, ICH6_CORBRP_RST); |
1062 | for (timeout = 1000; timeout > 0; timeout--) { | 1062 | if (!(chip->driver_caps & AZX_DCAPS_CORBRP_SELF_CLEAR)) { |
1063 | if ((azx_readw(chip, CORBRP) & ICH6_CORBRP_RST) == ICH6_CORBRP_RST) | 1063 | for (timeout = 1000; timeout > 0; timeout--) { |
1064 | break; | 1064 | if ((azx_readw(chip, CORBRP) & ICH6_CORBRP_RST) == ICH6_CORBRP_RST) |
1065 | udelay(1); | 1065 | break; |
1066 | } | 1066 | udelay(1); |
1067 | if (timeout <= 0) | 1067 | } |
1068 | dev_err(chip->card->dev, "CORB reset timeout#1, CORBRP = %d\n", | 1068 | if (timeout <= 0) |
1069 | azx_readw(chip, CORBRP)); | 1069 | dev_err(chip->card->dev, "CORB reset timeout#1, CORBRP = %d\n", |
1070 | azx_readw(chip, CORBRP)); | ||
1070 | 1071 | ||
1071 | azx_writew(chip, CORBRP, 0); | 1072 | azx_writew(chip, CORBRP, 0); |
1072 | for (timeout = 1000; timeout > 0; timeout--) { | 1073 | for (timeout = 1000; timeout > 0; timeout--) { |
1073 | if (azx_readw(chip, CORBRP) == 0) | 1074 | if (azx_readw(chip, CORBRP) == 0) |
1074 | break; | 1075 | break; |
1075 | udelay(1); | 1076 | udelay(1); |
1077 | } | ||
1078 | if (timeout <= 0) | ||
1079 | dev_err(chip->card->dev, "CORB reset timeout#2, CORBRP = %d\n", | ||
1080 | azx_readw(chip, CORBRP)); | ||
1076 | } | 1081 | } |
1077 | if (timeout <= 0) | ||
1078 | dev_err(chip->card->dev, "CORB reset timeout#2, CORBRP = %d\n", | ||
1079 | azx_readw(chip, CORBRP)); | ||
1080 | 1082 | ||
1081 | /* enable corb dma */ | 1083 | /* enable corb dma */ |
1082 | azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN); | 1084 | azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN); |
1083 | 1085 | ||
1084 | /* RIRB set up */ | 1086 | /* RIRB set up */ |
1085 | chip->rirb.addr = chip->rb.addr + 2048; | 1087 | chip->rirb.addr = chip->rb.addr + 2048; |
1086 | chip->rirb.buf = (u32 *)(chip->rb.area + 2048); | 1088 | chip->rirb.buf = (u32 *)(chip->rb.area + 2048); |
1087 | chip->rirb.wp = chip->rirb.rp = 0; | 1089 | chip->rirb.wp = chip->rirb.rp = 0; |
1088 | memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds)); | 1090 | memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds)); |
1089 | azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr); | 1091 | azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr); |
1090 | azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr)); | 1092 | azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr)); |
1091 | 1093 | ||
1092 | /* set the rirb size to 256 entries (ULI requires explicitly) */ | 1094 | /* set the rirb size to 256 entries (ULI requires explicitly) */ |
1093 | azx_writeb(chip, RIRBSIZE, 0x02); | 1095 | azx_writeb(chip, RIRBSIZE, 0x02); |
1094 | /* reset the rirb hw write pointer */ | 1096 | /* reset the rirb hw write pointer */ |
1095 | azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST); | 1097 | azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST); |
1096 | /* set N=1, get RIRB response interrupt for new entry */ | 1098 | /* set N=1, get RIRB response interrupt for new entry */ |
1097 | if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) | 1099 | if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) |
1098 | azx_writew(chip, RINTCNT, 0xc0); | 1100 | azx_writew(chip, RINTCNT, 0xc0); |
1099 | else | 1101 | else |
1100 | azx_writew(chip, RINTCNT, 1); | 1102 | azx_writew(chip, RINTCNT, 1); |
1101 | /* enable rirb dma and response irq */ | 1103 | /* enable rirb dma and response irq */ |
1102 | azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN); | 1104 | azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN); |
1103 | spin_unlock_irq(&chip->reg_lock); | 1105 | spin_unlock_irq(&chip->reg_lock); |
1104 | } | 1106 | } |
1105 | EXPORT_SYMBOL_GPL(azx_init_cmd_io); | 1107 | EXPORT_SYMBOL_GPL(azx_init_cmd_io); |
1106 | 1108 | ||
1107 | static void azx_free_cmd_io(struct azx *chip) | 1109 | static void azx_free_cmd_io(struct azx *chip) |
1108 | { | 1110 | { |
1109 | spin_lock_irq(&chip->reg_lock); | 1111 | spin_lock_irq(&chip->reg_lock); |
1110 | /* disable ringbuffer DMAs */ | 1112 | /* disable ringbuffer DMAs */ |
1111 | azx_writeb(chip, RIRBCTL, 0); | 1113 | azx_writeb(chip, RIRBCTL, 0); |
1112 | azx_writeb(chip, CORBCTL, 0); | 1114 | azx_writeb(chip, CORBCTL, 0); |
1113 | spin_unlock_irq(&chip->reg_lock); | 1115 | spin_unlock_irq(&chip->reg_lock); |
1114 | } | 1116 | } |
1115 | EXPORT_SYMBOL_GPL(azx_free_cmd_io); | 1117 | EXPORT_SYMBOL_GPL(azx_free_cmd_io); |
1116 | 1118 | ||
1117 | static unsigned int azx_command_addr(u32 cmd) | 1119 | static unsigned int azx_command_addr(u32 cmd) |
1118 | { | 1120 | { |
1119 | unsigned int addr = cmd >> 28; | 1121 | unsigned int addr = cmd >> 28; |
1120 | 1122 | ||
1121 | if (addr >= AZX_MAX_CODECS) { | 1123 | if (addr >= AZX_MAX_CODECS) { |
1122 | snd_BUG(); | 1124 | snd_BUG(); |
1123 | addr = 0; | 1125 | addr = 0; |
1124 | } | 1126 | } |
1125 | 1127 | ||
1126 | return addr; | 1128 | return addr; |
1127 | } | 1129 | } |
1128 | 1130 | ||
1129 | /* send a command */ | 1131 | /* send a command */ |
1130 | static int azx_corb_send_cmd(struct hda_bus *bus, u32 val) | 1132 | static int azx_corb_send_cmd(struct hda_bus *bus, u32 val) |
1131 | { | 1133 | { |
1132 | struct azx *chip = bus->private_data; | 1134 | struct azx *chip = bus->private_data; |
1133 | unsigned int addr = azx_command_addr(val); | 1135 | unsigned int addr = azx_command_addr(val); |
1134 | unsigned int wp, rp; | 1136 | unsigned int wp, rp; |
1135 | 1137 | ||
1136 | spin_lock_irq(&chip->reg_lock); | 1138 | spin_lock_irq(&chip->reg_lock); |
1137 | 1139 | ||
1138 | /* add command to corb */ | 1140 | /* add command to corb */ |
1139 | wp = azx_readw(chip, CORBWP); | 1141 | wp = azx_readw(chip, CORBWP); |
1140 | if (wp == 0xffff) { | 1142 | if (wp == 0xffff) { |
1141 | /* something wrong, controller likely turned to D3 */ | 1143 | /* something wrong, controller likely turned to D3 */ |
1142 | spin_unlock_irq(&chip->reg_lock); | 1144 | spin_unlock_irq(&chip->reg_lock); |
1143 | return -EIO; | 1145 | return -EIO; |
1144 | } | 1146 | } |
1145 | wp++; | 1147 | wp++; |
1146 | wp %= ICH6_MAX_CORB_ENTRIES; | 1148 | wp %= ICH6_MAX_CORB_ENTRIES; |
1147 | 1149 | ||
1148 | rp = azx_readw(chip, CORBRP); | 1150 | rp = azx_readw(chip, CORBRP); |
1149 | if (wp == rp) { | 1151 | if (wp == rp) { |
1150 | /* oops, it's full */ | 1152 | /* oops, it's full */ |
1151 | spin_unlock_irq(&chip->reg_lock); | 1153 | spin_unlock_irq(&chip->reg_lock); |
1152 | return -EAGAIN; | 1154 | return -EAGAIN; |
1153 | } | 1155 | } |
1154 | 1156 | ||
1155 | chip->rirb.cmds[addr]++; | 1157 | chip->rirb.cmds[addr]++; |
1156 | chip->corb.buf[wp] = cpu_to_le32(val); | 1158 | chip->corb.buf[wp] = cpu_to_le32(val); |
1157 | azx_writew(chip, CORBWP, wp); | 1159 | azx_writew(chip, CORBWP, wp); |
1158 | 1160 | ||
1159 | spin_unlock_irq(&chip->reg_lock); | 1161 | spin_unlock_irq(&chip->reg_lock); |
1160 | 1162 | ||
1161 | return 0; | 1163 | return 0; |
1162 | } | 1164 | } |
1163 | 1165 | ||
1164 | #define ICH6_RIRB_EX_UNSOL_EV (1<<4) | 1166 | #define ICH6_RIRB_EX_UNSOL_EV (1<<4) |
1165 | 1167 | ||
1166 | /* retrieve RIRB entry - called from interrupt handler */ | 1168 | /* retrieve RIRB entry - called from interrupt handler */ |
1167 | static void azx_update_rirb(struct azx *chip) | 1169 | static void azx_update_rirb(struct azx *chip) |
1168 | { | 1170 | { |
1169 | unsigned int rp, wp; | 1171 | unsigned int rp, wp; |
1170 | unsigned int addr; | 1172 | unsigned int addr; |
1171 | u32 res, res_ex; | 1173 | u32 res, res_ex; |
1172 | 1174 | ||
1173 | wp = azx_readw(chip, RIRBWP); | 1175 | wp = azx_readw(chip, RIRBWP); |
1174 | if (wp == 0xffff) { | 1176 | if (wp == 0xffff) { |
1175 | /* something wrong, controller likely turned to D3 */ | 1177 | /* something wrong, controller likely turned to D3 */ |
1176 | return; | 1178 | return; |
1177 | } | 1179 | } |
1178 | 1180 | ||
1179 | if (wp == chip->rirb.wp) | 1181 | if (wp == chip->rirb.wp) |
1180 | return; | 1182 | return; |
1181 | chip->rirb.wp = wp; | 1183 | chip->rirb.wp = wp; |
1182 | 1184 | ||
1183 | while (chip->rirb.rp != wp) { | 1185 | while (chip->rirb.rp != wp) { |
1184 | chip->rirb.rp++; | 1186 | chip->rirb.rp++; |
1185 | chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES; | 1187 | chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES; |
1186 | 1188 | ||
1187 | rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */ | 1189 | rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */ |
1188 | res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]); | 1190 | res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]); |
1189 | res = le32_to_cpu(chip->rirb.buf[rp]); | 1191 | res = le32_to_cpu(chip->rirb.buf[rp]); |
1190 | addr = res_ex & 0xf; | 1192 | addr = res_ex & 0xf; |
1191 | if ((addr >= AZX_MAX_CODECS) || !(chip->codec_mask & (1 << addr))) { | 1193 | if ((addr >= AZX_MAX_CODECS) || !(chip->codec_mask & (1 << addr))) { |
1192 | dev_err(chip->card->dev, "spurious response %#x:%#x, rp = %d, wp = %d", | 1194 | dev_err(chip->card->dev, "spurious response %#x:%#x, rp = %d, wp = %d", |
1193 | res, res_ex, | 1195 | res, res_ex, |
1194 | chip->rirb.rp, wp); | 1196 | chip->rirb.rp, wp); |
1195 | snd_BUG(); | 1197 | snd_BUG(); |
1196 | } | 1198 | } |
1197 | else if (res_ex & ICH6_RIRB_EX_UNSOL_EV) | 1199 | else if (res_ex & ICH6_RIRB_EX_UNSOL_EV) |
1198 | snd_hda_queue_unsol_event(chip->bus, res, res_ex); | 1200 | snd_hda_queue_unsol_event(chip->bus, res, res_ex); |
1199 | else if (chip->rirb.cmds[addr]) { | 1201 | else if (chip->rirb.cmds[addr]) { |
1200 | chip->rirb.res[addr] = res; | 1202 | chip->rirb.res[addr] = res; |
1201 | smp_wmb(); | 1203 | smp_wmb(); |
1202 | chip->rirb.cmds[addr]--; | 1204 | chip->rirb.cmds[addr]--; |
1203 | } else if (printk_ratelimit()) { | 1205 | } else if (printk_ratelimit()) { |
1204 | dev_err(chip->card->dev, "spurious response %#x:%#x, last cmd=%#08x\n", | 1206 | dev_err(chip->card->dev, "spurious response %#x:%#x, last cmd=%#08x\n", |
1205 | res, res_ex, | 1207 | res, res_ex, |
1206 | chip->last_cmd[addr]); | 1208 | chip->last_cmd[addr]); |
1207 | } | 1209 | } |
1208 | } | 1210 | } |
1209 | } | 1211 | } |
1210 | 1212 | ||
1211 | /* receive a response */ | 1213 | /* receive a response */ |
1212 | static unsigned int azx_rirb_get_response(struct hda_bus *bus, | 1214 | static unsigned int azx_rirb_get_response(struct hda_bus *bus, |
1213 | unsigned int addr) | 1215 | unsigned int addr) |
1214 | { | 1216 | { |
1215 | struct azx *chip = bus->private_data; | 1217 | struct azx *chip = bus->private_data; |
1216 | unsigned long timeout; | 1218 | unsigned long timeout; |
1217 | unsigned long loopcounter; | 1219 | unsigned long loopcounter; |
1218 | int do_poll = 0; | 1220 | int do_poll = 0; |
1219 | 1221 | ||
1220 | again: | 1222 | again: |
1221 | timeout = jiffies + msecs_to_jiffies(1000); | 1223 | timeout = jiffies + msecs_to_jiffies(1000); |
1222 | 1224 | ||
1223 | for (loopcounter = 0;; loopcounter++) { | 1225 | for (loopcounter = 0;; loopcounter++) { |
1224 | if (chip->polling_mode || do_poll) { | 1226 | if (chip->polling_mode || do_poll) { |
1225 | spin_lock_irq(&chip->reg_lock); | 1227 | spin_lock_irq(&chip->reg_lock); |
1226 | azx_update_rirb(chip); | 1228 | azx_update_rirb(chip); |
1227 | spin_unlock_irq(&chip->reg_lock); | 1229 | spin_unlock_irq(&chip->reg_lock); |
1228 | } | 1230 | } |
1229 | if (!chip->rirb.cmds[addr]) { | 1231 | if (!chip->rirb.cmds[addr]) { |
1230 | smp_rmb(); | 1232 | smp_rmb(); |
1231 | bus->rirb_error = 0; | 1233 | bus->rirb_error = 0; |
1232 | 1234 | ||
1233 | if (!do_poll) | 1235 | if (!do_poll) |
1234 | chip->poll_count = 0; | 1236 | chip->poll_count = 0; |
1235 | return chip->rirb.res[addr]; /* the last value */ | 1237 | return chip->rirb.res[addr]; /* the last value */ |
1236 | } | 1238 | } |
1237 | if (time_after(jiffies, timeout)) | 1239 | if (time_after(jiffies, timeout)) |
1238 | break; | 1240 | break; |
1239 | if (bus->needs_damn_long_delay || loopcounter > 3000) | 1241 | if (bus->needs_damn_long_delay || loopcounter > 3000) |
1240 | msleep(2); /* temporary workaround */ | 1242 | msleep(2); /* temporary workaround */ |
1241 | else { | 1243 | else { |
1242 | udelay(10); | 1244 | udelay(10); |
1243 | cond_resched(); | 1245 | cond_resched(); |
1244 | } | 1246 | } |
1245 | } | 1247 | } |
1246 | 1248 | ||
1247 | if (!bus->no_response_fallback) | 1249 | if (!bus->no_response_fallback) |
1248 | return -1; | 1250 | return -1; |
1249 | 1251 | ||
1250 | if (!chip->polling_mode && chip->poll_count < 2) { | 1252 | if (!chip->polling_mode && chip->poll_count < 2) { |
1251 | dev_dbg(chip->card->dev, | 1253 | dev_dbg(chip->card->dev, |
1252 | "azx_get_response timeout, polling the codec once: last cmd=0x%08x\n", | 1254 | "azx_get_response timeout, polling the codec once: last cmd=0x%08x\n", |
1253 | chip->last_cmd[addr]); | 1255 | chip->last_cmd[addr]); |
1254 | do_poll = 1; | 1256 | do_poll = 1; |
1255 | chip->poll_count++; | 1257 | chip->poll_count++; |
1256 | goto again; | 1258 | goto again; |
1257 | } | 1259 | } |
1258 | 1260 | ||
1259 | 1261 | ||
1260 | if (!chip->polling_mode) { | 1262 | if (!chip->polling_mode) { |
1261 | dev_warn(chip->card->dev, | 1263 | dev_warn(chip->card->dev, |
1262 | "azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n", | 1264 | "azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n", |
1263 | chip->last_cmd[addr]); | 1265 | chip->last_cmd[addr]); |
1264 | chip->polling_mode = 1; | 1266 | chip->polling_mode = 1; |
1265 | goto again; | 1267 | goto again; |
1266 | } | 1268 | } |
1267 | 1269 | ||
1268 | if (chip->msi) { | 1270 | if (chip->msi) { |
1269 | dev_warn(chip->card->dev, | 1271 | dev_warn(chip->card->dev, |
1270 | "No response from codec, disabling MSI: last cmd=0x%08x\n", | 1272 | "No response from codec, disabling MSI: last cmd=0x%08x\n", |
1271 | chip->last_cmd[addr]); | 1273 | chip->last_cmd[addr]); |
1272 | if (chip->ops->disable_msi_reset_irq(chip) && | 1274 | if (chip->ops->disable_msi_reset_irq(chip) && |
1273 | chip->ops->disable_msi_reset_irq(chip) < 0) { | 1275 | chip->ops->disable_msi_reset_irq(chip) < 0) { |
1274 | bus->rirb_error = 1; | 1276 | bus->rirb_error = 1; |
1275 | return -1; | 1277 | return -1; |
1276 | } | 1278 | } |
1277 | goto again; | 1279 | goto again; |
1278 | } | 1280 | } |
1279 | 1281 | ||
1280 | if (chip->probing) { | 1282 | if (chip->probing) { |
1281 | /* If this critical timeout happens during the codec probing | 1283 | /* If this critical timeout happens during the codec probing |
1282 | * phase, this is likely an access to a non-existing codec | 1284 | * phase, this is likely an access to a non-existing codec |
1283 | * slot. Better to return an error and reset the system. | 1285 | * slot. Better to return an error and reset the system. |
1284 | */ | 1286 | */ |
1285 | return -1; | 1287 | return -1; |
1286 | } | 1288 | } |
1287 | 1289 | ||
1288 | /* a fatal communication error; need either to reset or to fallback | 1290 | /* a fatal communication error; need either to reset or to fallback |
1289 | * to the single_cmd mode | 1291 | * to the single_cmd mode |
1290 | */ | 1292 | */ |
1291 | bus->rirb_error = 1; | 1293 | bus->rirb_error = 1; |
1292 | if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) { | 1294 | if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) { |
1293 | bus->response_reset = 1; | 1295 | bus->response_reset = 1; |
1294 | return -1; /* give a chance to retry */ | 1296 | return -1; /* give a chance to retry */ |
1295 | } | 1297 | } |
1296 | 1298 | ||
1297 | dev_err(chip->card->dev, | 1299 | dev_err(chip->card->dev, |
1298 | "azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n", | 1300 | "azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n", |
1299 | chip->last_cmd[addr]); | 1301 | chip->last_cmd[addr]); |
1300 | chip->single_cmd = 1; | 1302 | chip->single_cmd = 1; |
1301 | bus->response_reset = 0; | 1303 | bus->response_reset = 0; |
1302 | /* release CORB/RIRB */ | 1304 | /* release CORB/RIRB */ |
1303 | azx_free_cmd_io(chip); | 1305 | azx_free_cmd_io(chip); |
1304 | /* disable unsolicited responses */ | 1306 | /* disable unsolicited responses */ |
1305 | azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL); | 1307 | azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL); |
1306 | return -1; | 1308 | return -1; |
1307 | } | 1309 | } |
1308 | 1310 | ||
1309 | /* | 1311 | /* |
1310 | * Use the single immediate command instead of CORB/RIRB for simplicity | 1312 | * Use the single immediate command instead of CORB/RIRB for simplicity |
1311 | * | 1313 | * |
1312 | * Note: according to Intel, this is not preferred use. The command was | 1314 | * Note: according to Intel, this is not preferred use. The command was |
1313 | * intended for the BIOS only, and may get confused with unsolicited | 1315 | * intended for the BIOS only, and may get confused with unsolicited |
1314 | * responses. So, we shouldn't use it for normal operation from the | 1316 | * responses. So, we shouldn't use it for normal operation from the |
1315 | * driver. | 1317 | * driver. |
1316 | * I left the codes, however, for debugging/testing purposes. | 1318 | * I left the codes, however, for debugging/testing purposes. |
1317 | */ | 1319 | */ |
1318 | 1320 | ||
1319 | /* receive a response */ | 1321 | /* receive a response */ |
1320 | static int azx_single_wait_for_response(struct azx *chip, unsigned int addr) | 1322 | static int azx_single_wait_for_response(struct azx *chip, unsigned int addr) |
1321 | { | 1323 | { |
1322 | int timeout = 50; | 1324 | int timeout = 50; |
1323 | 1325 | ||
1324 | while (timeout--) { | 1326 | while (timeout--) { |
1325 | /* check IRV busy bit */ | 1327 | /* check IRV busy bit */ |
1326 | if (azx_readw(chip, IRS) & ICH6_IRS_VALID) { | 1328 | if (azx_readw(chip, IRS) & ICH6_IRS_VALID) { |
1327 | /* reuse rirb.res as the response return value */ | 1329 | /* reuse rirb.res as the response return value */ |
1328 | chip->rirb.res[addr] = azx_readl(chip, IR); | 1330 | chip->rirb.res[addr] = azx_readl(chip, IR); |
1329 | return 0; | 1331 | return 0; |
1330 | } | 1332 | } |
1331 | udelay(1); | 1333 | udelay(1); |
1332 | } | 1334 | } |
1333 | if (printk_ratelimit()) | 1335 | if (printk_ratelimit()) |
1334 | dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n", | 1336 | dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n", |
1335 | azx_readw(chip, IRS)); | 1337 | azx_readw(chip, IRS)); |
1336 | chip->rirb.res[addr] = -1; | 1338 | chip->rirb.res[addr] = -1; |
1337 | return -EIO; | 1339 | return -EIO; |
1338 | } | 1340 | } |
1339 | 1341 | ||
1340 | /* send a command */ | 1342 | /* send a command */ |
1341 | static int azx_single_send_cmd(struct hda_bus *bus, u32 val) | 1343 | static int azx_single_send_cmd(struct hda_bus *bus, u32 val) |
1342 | { | 1344 | { |
1343 | struct azx *chip = bus->private_data; | 1345 | struct azx *chip = bus->private_data; |
1344 | unsigned int addr = azx_command_addr(val); | 1346 | unsigned int addr = azx_command_addr(val); |
1345 | int timeout = 50; | 1347 | int timeout = 50; |
1346 | 1348 | ||
1347 | bus->rirb_error = 0; | 1349 | bus->rirb_error = 0; |
1348 | while (timeout--) { | 1350 | while (timeout--) { |
1349 | /* check ICB busy bit */ | 1351 | /* check ICB busy bit */ |
1350 | if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) { | 1352 | if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) { |
1351 | /* Clear IRV valid bit */ | 1353 | /* Clear IRV valid bit */ |
1352 | azx_writew(chip, IRS, azx_readw(chip, IRS) | | 1354 | azx_writew(chip, IRS, azx_readw(chip, IRS) | |
1353 | ICH6_IRS_VALID); | 1355 | ICH6_IRS_VALID); |
1354 | azx_writel(chip, IC, val); | 1356 | azx_writel(chip, IC, val); |
1355 | azx_writew(chip, IRS, azx_readw(chip, IRS) | | 1357 | azx_writew(chip, IRS, azx_readw(chip, IRS) | |
1356 | ICH6_IRS_BUSY); | 1358 | ICH6_IRS_BUSY); |
1357 | return azx_single_wait_for_response(chip, addr); | 1359 | return azx_single_wait_for_response(chip, addr); |
1358 | } | 1360 | } |
1359 | udelay(1); | 1361 | udelay(1); |
1360 | } | 1362 | } |
1361 | if (printk_ratelimit()) | 1363 | if (printk_ratelimit()) |
1362 | dev_dbg(chip->card->dev, | 1364 | dev_dbg(chip->card->dev, |
1363 | "send_cmd timeout: IRS=0x%x, val=0x%x\n", | 1365 | "send_cmd timeout: IRS=0x%x, val=0x%x\n", |
1364 | azx_readw(chip, IRS), val); | 1366 | azx_readw(chip, IRS), val); |
1365 | return -EIO; | 1367 | return -EIO; |
1366 | } | 1368 | } |
1367 | 1369 | ||
1368 | /* receive a response */ | 1370 | /* receive a response */ |
1369 | static unsigned int azx_single_get_response(struct hda_bus *bus, | 1371 | static unsigned int azx_single_get_response(struct hda_bus *bus, |
1370 | unsigned int addr) | 1372 | unsigned int addr) |
1371 | { | 1373 | { |
1372 | struct azx *chip = bus->private_data; | 1374 | struct azx *chip = bus->private_data; |
1373 | return chip->rirb.res[addr]; | 1375 | return chip->rirb.res[addr]; |
1374 | } | 1376 | } |
1375 | 1377 | ||
1376 | /* | 1378 | /* |
1377 | * The below are the main callbacks from hda_codec. | 1379 | * The below are the main callbacks from hda_codec. |
1378 | * | 1380 | * |
1379 | * They are just the skeleton to call sub-callbacks according to the | 1381 | * They are just the skeleton to call sub-callbacks according to the |
1380 | * current setting of chip->single_cmd. | 1382 | * current setting of chip->single_cmd. |
1381 | */ | 1383 | */ |
1382 | 1384 | ||
1383 | /* send a command */ | 1385 | /* send a command */ |
1384 | static int azx_send_cmd(struct hda_bus *bus, unsigned int val) | 1386 | static int azx_send_cmd(struct hda_bus *bus, unsigned int val) |
1385 | { | 1387 | { |
1386 | struct azx *chip = bus->private_data; | 1388 | struct azx *chip = bus->private_data; |
1387 | 1389 | ||
1388 | if (chip->disabled) | 1390 | if (chip->disabled) |
1389 | return 0; | 1391 | return 0; |
1390 | chip->last_cmd[azx_command_addr(val)] = val; | 1392 | chip->last_cmd[azx_command_addr(val)] = val; |
1391 | if (chip->single_cmd) | 1393 | if (chip->single_cmd) |
1392 | return azx_single_send_cmd(bus, val); | 1394 | return azx_single_send_cmd(bus, val); |
1393 | else | 1395 | else |
1394 | return azx_corb_send_cmd(bus, val); | 1396 | return azx_corb_send_cmd(bus, val); |
1395 | } | 1397 | } |
1396 | EXPORT_SYMBOL_GPL(azx_send_cmd); | 1398 | EXPORT_SYMBOL_GPL(azx_send_cmd); |
1397 | 1399 | ||
1398 | /* get a response */ | 1400 | /* get a response */ |
1399 | static unsigned int azx_get_response(struct hda_bus *bus, | 1401 | static unsigned int azx_get_response(struct hda_bus *bus, |
1400 | unsigned int addr) | 1402 | unsigned int addr) |
1401 | { | 1403 | { |
1402 | struct azx *chip = bus->private_data; | 1404 | struct azx *chip = bus->private_data; |
1403 | if (chip->disabled) | 1405 | if (chip->disabled) |
1404 | return 0; | 1406 | return 0; |
1405 | if (chip->single_cmd) | 1407 | if (chip->single_cmd) |
1406 | return azx_single_get_response(bus, addr); | 1408 | return azx_single_get_response(bus, addr); |
1407 | else | 1409 | else |
1408 | return azx_rirb_get_response(bus, addr); | 1410 | return azx_rirb_get_response(bus, addr); |
1409 | } | 1411 | } |
1410 | EXPORT_SYMBOL_GPL(azx_get_response); | 1412 | EXPORT_SYMBOL_GPL(azx_get_response); |
1411 | 1413 | ||
1412 | #ifdef CONFIG_SND_HDA_DSP_LOADER | 1414 | #ifdef CONFIG_SND_HDA_DSP_LOADER |
1413 | /* | 1415 | /* |
1414 | * DSP loading code (e.g. for CA0132) | 1416 | * DSP loading code (e.g. for CA0132) |
1415 | */ | 1417 | */ |
1416 | 1418 | ||
1417 | /* use the first stream for loading DSP */ | 1419 | /* use the first stream for loading DSP */ |
1418 | static struct azx_dev * | 1420 | static struct azx_dev * |
1419 | azx_get_dsp_loader_dev(struct azx *chip) | 1421 | azx_get_dsp_loader_dev(struct azx *chip) |
1420 | { | 1422 | { |
1421 | return &chip->azx_dev[chip->playback_index_offset]; | 1423 | return &chip->azx_dev[chip->playback_index_offset]; |
1422 | } | 1424 | } |
1423 | 1425 | ||
1424 | static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format, | 1426 | static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format, |
1425 | unsigned int byte_size, | 1427 | unsigned int byte_size, |
1426 | struct snd_dma_buffer *bufp) | 1428 | struct snd_dma_buffer *bufp) |
1427 | { | 1429 | { |
1428 | u32 *bdl; | 1430 | u32 *bdl; |
1429 | struct azx *chip = bus->private_data; | 1431 | struct azx *chip = bus->private_data; |
1430 | struct azx_dev *azx_dev; | 1432 | struct azx_dev *azx_dev; |
1431 | int err; | 1433 | int err; |
1432 | 1434 | ||
1433 | azx_dev = azx_get_dsp_loader_dev(chip); | 1435 | azx_dev = azx_get_dsp_loader_dev(chip); |
1434 | 1436 | ||
1435 | dsp_lock(azx_dev); | 1437 | dsp_lock(azx_dev); |
1436 | spin_lock_irq(&chip->reg_lock); | 1438 | spin_lock_irq(&chip->reg_lock); |
1437 | if (azx_dev->running || azx_dev->locked) { | 1439 | if (azx_dev->running || azx_dev->locked) { |
1438 | spin_unlock_irq(&chip->reg_lock); | 1440 | spin_unlock_irq(&chip->reg_lock); |
1439 | err = -EBUSY; | 1441 | err = -EBUSY; |
1440 | goto unlock; | 1442 | goto unlock; |
1441 | } | 1443 | } |
1442 | azx_dev->prepared = 0; | 1444 | azx_dev->prepared = 0; |
1443 | chip->saved_azx_dev = *azx_dev; | 1445 | chip->saved_azx_dev = *azx_dev; |
1444 | azx_dev->locked = 1; | 1446 | azx_dev->locked = 1; |
1445 | spin_unlock_irq(&chip->reg_lock); | 1447 | spin_unlock_irq(&chip->reg_lock); |
1446 | 1448 | ||
1447 | err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV_SG, | 1449 | err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV_SG, |
1448 | byte_size, bufp); | 1450 | byte_size, bufp); |
1449 | if (err < 0) | 1451 | if (err < 0) |
1450 | goto err_alloc; | 1452 | goto err_alloc; |
1451 | 1453 | ||
1452 | azx_dev->bufsize = byte_size; | 1454 | azx_dev->bufsize = byte_size; |
1453 | azx_dev->period_bytes = byte_size; | 1455 | azx_dev->period_bytes = byte_size; |
1454 | azx_dev->format_val = format; | 1456 | azx_dev->format_val = format; |
1455 | 1457 | ||
1456 | azx_stream_reset(chip, azx_dev); | 1458 | azx_stream_reset(chip, azx_dev); |
1457 | 1459 | ||
1458 | /* reset BDL address */ | 1460 | /* reset BDL address */ |
1459 | azx_sd_writel(chip, azx_dev, SD_BDLPL, 0); | 1461 | azx_sd_writel(chip, azx_dev, SD_BDLPL, 0); |
1460 | azx_sd_writel(chip, azx_dev, SD_BDLPU, 0); | 1462 | azx_sd_writel(chip, azx_dev, SD_BDLPU, 0); |
1461 | 1463 | ||
1462 | azx_dev->frags = 0; | 1464 | azx_dev->frags = 0; |
1463 | bdl = (u32 *)azx_dev->bdl.area; | 1465 | bdl = (u32 *)azx_dev->bdl.area; |
1464 | err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0); | 1466 | err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0); |
1465 | if (err < 0) | 1467 | if (err < 0) |
1466 | goto error; | 1468 | goto error; |
1467 | 1469 | ||
1468 | azx_setup_controller(chip, azx_dev); | 1470 | azx_setup_controller(chip, azx_dev); |
1469 | dsp_unlock(azx_dev); | 1471 | dsp_unlock(azx_dev); |
1470 | return azx_dev->stream_tag; | 1472 | return azx_dev->stream_tag; |
1471 | 1473 | ||
1472 | error: | 1474 | error: |
1473 | chip->ops->dma_free_pages(chip, bufp); | 1475 | chip->ops->dma_free_pages(chip, bufp); |
1474 | err_alloc: | 1476 | err_alloc: |
1475 | spin_lock_irq(&chip->reg_lock); | 1477 | spin_lock_irq(&chip->reg_lock); |
1476 | if (azx_dev->opened) | 1478 | if (azx_dev->opened) |
1477 | *azx_dev = chip->saved_azx_dev; | 1479 | *azx_dev = chip->saved_azx_dev; |
1478 | azx_dev->locked = 0; | 1480 | azx_dev->locked = 0; |
1479 | spin_unlock_irq(&chip->reg_lock); | 1481 | spin_unlock_irq(&chip->reg_lock); |
1480 | unlock: | 1482 | unlock: |
1481 | dsp_unlock(azx_dev); | 1483 | dsp_unlock(azx_dev); |
1482 | return err; | 1484 | return err; |
1483 | } | 1485 | } |
1484 | 1486 | ||
1485 | static void azx_load_dsp_trigger(struct hda_bus *bus, bool start) | 1487 | static void azx_load_dsp_trigger(struct hda_bus *bus, bool start) |
1486 | { | 1488 | { |
1487 | struct azx *chip = bus->private_data; | 1489 | struct azx *chip = bus->private_data; |
1488 | struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip); | 1490 | struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip); |
1489 | 1491 | ||
1490 | if (start) | 1492 | if (start) |
1491 | azx_stream_start(chip, azx_dev); | 1493 | azx_stream_start(chip, azx_dev); |
1492 | else | 1494 | else |
1493 | azx_stream_stop(chip, azx_dev); | 1495 | azx_stream_stop(chip, azx_dev); |
1494 | azx_dev->running = start; | 1496 | azx_dev->running = start; |
1495 | } | 1497 | } |
1496 | 1498 | ||
1497 | static void azx_load_dsp_cleanup(struct hda_bus *bus, | 1499 | static void azx_load_dsp_cleanup(struct hda_bus *bus, |
1498 | struct snd_dma_buffer *dmab) | 1500 | struct snd_dma_buffer *dmab) |
1499 | { | 1501 | { |
1500 | struct azx *chip = bus->private_data; | 1502 | struct azx *chip = bus->private_data; |
1501 | struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip); | 1503 | struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip); |
1502 | 1504 | ||
1503 | if (!dmab->area || !azx_dev->locked) | 1505 | if (!dmab->area || !azx_dev->locked) |
1504 | return; | 1506 | return; |
1505 | 1507 | ||
1506 | dsp_lock(azx_dev); | 1508 | dsp_lock(azx_dev); |
1507 | /* reset BDL address */ | 1509 | /* reset BDL address */ |
1508 | azx_sd_writel(chip, azx_dev, SD_BDLPL, 0); | 1510 | azx_sd_writel(chip, azx_dev, SD_BDLPL, 0); |
1509 | azx_sd_writel(chip, azx_dev, SD_BDLPU, 0); | 1511 | azx_sd_writel(chip, azx_dev, SD_BDLPU, 0); |
1510 | azx_sd_writel(chip, azx_dev, SD_CTL, 0); | 1512 | azx_sd_writel(chip, azx_dev, SD_CTL, 0); |
1511 | azx_dev->bufsize = 0; | 1513 | azx_dev->bufsize = 0; |
1512 | azx_dev->period_bytes = 0; | 1514 | azx_dev->period_bytes = 0; |
1513 | azx_dev->format_val = 0; | 1515 | azx_dev->format_val = 0; |
1514 | 1516 | ||
1515 | chip->ops->dma_free_pages(chip, dmab); | 1517 | chip->ops->dma_free_pages(chip, dmab); |
1516 | dmab->area = NULL; | 1518 | dmab->area = NULL; |
1517 | 1519 | ||
1518 | spin_lock_irq(&chip->reg_lock); | 1520 | spin_lock_irq(&chip->reg_lock); |
1519 | if (azx_dev->opened) | 1521 | if (azx_dev->opened) |
1520 | *azx_dev = chip->saved_azx_dev; | 1522 | *azx_dev = chip->saved_azx_dev; |
1521 | azx_dev->locked = 0; | 1523 | azx_dev->locked = 0; |
1522 | spin_unlock_irq(&chip->reg_lock); | 1524 | spin_unlock_irq(&chip->reg_lock); |
1523 | dsp_unlock(azx_dev); | 1525 | dsp_unlock(azx_dev); |
1524 | } | 1526 | } |
1525 | #endif /* CONFIG_SND_HDA_DSP_LOADER */ | 1527 | #endif /* CONFIG_SND_HDA_DSP_LOADER */ |
1526 | 1528 | ||
1527 | int azx_alloc_stream_pages(struct azx *chip) | 1529 | int azx_alloc_stream_pages(struct azx *chip) |
1528 | { | 1530 | { |
1529 | int i, err; | 1531 | int i, err; |
1530 | struct snd_card *card = chip->card; | 1532 | struct snd_card *card = chip->card; |
1531 | 1533 | ||
1532 | for (i = 0; i < chip->num_streams; i++) { | 1534 | for (i = 0; i < chip->num_streams; i++) { |
1533 | dsp_lock_init(&chip->azx_dev[i]); | 1535 | dsp_lock_init(&chip->azx_dev[i]); |
1534 | /* allocate memory for the BDL for each stream */ | 1536 | /* allocate memory for the BDL for each stream */ |
1535 | err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV, | 1537 | err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV, |
1536 | BDL_SIZE, | 1538 | BDL_SIZE, |
1537 | &chip->azx_dev[i].bdl); | 1539 | &chip->azx_dev[i].bdl); |
1538 | if (err < 0) { | 1540 | if (err < 0) { |
1539 | dev_err(card->dev, "cannot allocate BDL\n"); | 1541 | dev_err(card->dev, "cannot allocate BDL\n"); |
1540 | return -ENOMEM; | 1542 | return -ENOMEM; |
1541 | } | 1543 | } |
1542 | } | 1544 | } |
1543 | /* allocate memory for the position buffer */ | 1545 | /* allocate memory for the position buffer */ |
1544 | err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV, | 1546 | err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV, |
1545 | chip->num_streams * 8, &chip->posbuf); | 1547 | chip->num_streams * 8, &chip->posbuf); |
1546 | if (err < 0) { | 1548 | if (err < 0) { |
1547 | dev_err(card->dev, "cannot allocate posbuf\n"); | 1549 | dev_err(card->dev, "cannot allocate posbuf\n"); |
1548 | return -ENOMEM; | 1550 | return -ENOMEM; |
1549 | } | 1551 | } |
1550 | 1552 | ||
1551 | /* allocate CORB/RIRB */ | 1553 | /* allocate CORB/RIRB */ |
1552 | err = azx_alloc_cmd_io(chip); | 1554 | err = azx_alloc_cmd_io(chip); |
1553 | if (err < 0) | 1555 | if (err < 0) |
1554 | return err; | 1556 | return err; |
1555 | return 0; | 1557 | return 0; |
1556 | } | 1558 | } |
1557 | EXPORT_SYMBOL_GPL(azx_alloc_stream_pages); | 1559 | EXPORT_SYMBOL_GPL(azx_alloc_stream_pages); |
1558 | 1560 | ||
1559 | void azx_free_stream_pages(struct azx *chip) | 1561 | void azx_free_stream_pages(struct azx *chip) |
1560 | { | 1562 | { |
1561 | int i; | 1563 | int i; |
1562 | if (chip->azx_dev) { | 1564 | if (chip->azx_dev) { |
1563 | for (i = 0; i < chip->num_streams; i++) | 1565 | for (i = 0; i < chip->num_streams; i++) |
1564 | if (chip->azx_dev[i].bdl.area) | 1566 | if (chip->azx_dev[i].bdl.area) |
1565 | chip->ops->dma_free_pages( | 1567 | chip->ops->dma_free_pages( |
1566 | chip, &chip->azx_dev[i].bdl); | 1568 | chip, &chip->azx_dev[i].bdl); |
1567 | } | 1569 | } |
1568 | if (chip->rb.area) | 1570 | if (chip->rb.area) |
1569 | chip->ops->dma_free_pages(chip, &chip->rb); | 1571 | chip->ops->dma_free_pages(chip, &chip->rb); |
1570 | if (chip->posbuf.area) | 1572 | if (chip->posbuf.area) |
1571 | chip->ops->dma_free_pages(chip, &chip->posbuf); | 1573 | chip->ops->dma_free_pages(chip, &chip->posbuf); |
1572 | } | 1574 | } |
1573 | EXPORT_SYMBOL_GPL(azx_free_stream_pages); | 1575 | EXPORT_SYMBOL_GPL(azx_free_stream_pages); |
1574 | 1576 | ||
1575 | /* | 1577 | /* |
1576 | * Lowlevel interface | 1578 | * Lowlevel interface |
1577 | */ | 1579 | */ |
1578 | 1580 | ||
1579 | /* enter link reset */ | 1581 | /* enter link reset */ |
1580 | void azx_enter_link_reset(struct azx *chip) | 1582 | void azx_enter_link_reset(struct azx *chip) |
1581 | { | 1583 | { |
1582 | unsigned long timeout; | 1584 | unsigned long timeout; |
1583 | 1585 | ||
1584 | /* reset controller */ | 1586 | /* reset controller */ |
1585 | azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET); | 1587 | azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET); |
1586 | 1588 | ||
1587 | timeout = jiffies + msecs_to_jiffies(100); | 1589 | timeout = jiffies + msecs_to_jiffies(100); |
1588 | while ((azx_readb(chip, GCTL) & ICH6_GCTL_RESET) && | 1590 | while ((azx_readb(chip, GCTL) & ICH6_GCTL_RESET) && |
1589 | time_before(jiffies, timeout)) | 1591 | time_before(jiffies, timeout)) |
1590 | usleep_range(500, 1000); | 1592 | usleep_range(500, 1000); |
1591 | } | 1593 | } |
1592 | EXPORT_SYMBOL_GPL(azx_enter_link_reset); | 1594 | EXPORT_SYMBOL_GPL(azx_enter_link_reset); |
1593 | 1595 | ||
1594 | /* exit link reset */ | 1596 | /* exit link reset */ |
1595 | static void azx_exit_link_reset(struct azx *chip) | 1597 | static void azx_exit_link_reset(struct azx *chip) |
1596 | { | 1598 | { |
1597 | unsigned long timeout; | 1599 | unsigned long timeout; |
1598 | 1600 | ||
1599 | azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET); | 1601 | azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET); |
1600 | 1602 | ||
1601 | timeout = jiffies + msecs_to_jiffies(100); | 1603 | timeout = jiffies + msecs_to_jiffies(100); |
1602 | while (!azx_readb(chip, GCTL) && | 1604 | while (!azx_readb(chip, GCTL) && |
1603 | time_before(jiffies, timeout)) | 1605 | time_before(jiffies, timeout)) |
1604 | usleep_range(500, 1000); | 1606 | usleep_range(500, 1000); |
1605 | } | 1607 | } |
1606 | 1608 | ||
1607 | /* reset codec link */ | 1609 | /* reset codec link */ |
1608 | static int azx_reset(struct azx *chip, bool full_reset) | 1610 | static int azx_reset(struct azx *chip, bool full_reset) |
1609 | { | 1611 | { |
1610 | if (!full_reset) | 1612 | if (!full_reset) |
1611 | goto __skip; | 1613 | goto __skip; |
1612 | 1614 | ||
1613 | /* clear STATESTS */ | 1615 | /* clear STATESTS */ |
1614 | azx_writew(chip, STATESTS, STATESTS_INT_MASK); | 1616 | azx_writew(chip, STATESTS, STATESTS_INT_MASK); |
1615 | 1617 | ||
1616 | /* reset controller */ | 1618 | /* reset controller */ |
1617 | azx_enter_link_reset(chip); | 1619 | azx_enter_link_reset(chip); |
1618 | 1620 | ||
1619 | /* delay for >= 100us for codec PLL to settle per spec | 1621 | /* delay for >= 100us for codec PLL to settle per spec |
1620 | * Rev 0.9 section 5.5.1 | 1622 | * Rev 0.9 section 5.5.1 |
1621 | */ | 1623 | */ |
1622 | usleep_range(500, 1000); | 1624 | usleep_range(500, 1000); |
1623 | 1625 | ||
1624 | /* Bring controller out of reset */ | 1626 | /* Bring controller out of reset */ |
1625 | azx_exit_link_reset(chip); | 1627 | azx_exit_link_reset(chip); |
1626 | 1628 | ||
1627 | /* Brent Chartrand said to wait >= 540us for codecs to initialize */ | 1629 | /* Brent Chartrand said to wait >= 540us for codecs to initialize */ |
1628 | usleep_range(1000, 1200); | 1630 | usleep_range(1000, 1200); |
1629 | 1631 | ||
1630 | __skip: | 1632 | __skip: |
1631 | /* check to see if controller is ready */ | 1633 | /* check to see if controller is ready */ |
1632 | if (!azx_readb(chip, GCTL)) { | 1634 | if (!azx_readb(chip, GCTL)) { |
1633 | dev_dbg(chip->card->dev, "azx_reset: controller not ready!\n"); | 1635 | dev_dbg(chip->card->dev, "azx_reset: controller not ready!\n"); |
1634 | return -EBUSY; | 1636 | return -EBUSY; |
1635 | } | 1637 | } |
1636 | 1638 | ||
1637 | /* Accept unsolicited responses */ | 1639 | /* Accept unsolicited responses */ |
1638 | if (!chip->single_cmd) | 1640 | if (!chip->single_cmd) |
1639 | azx_writel(chip, GCTL, azx_readl(chip, GCTL) | | 1641 | azx_writel(chip, GCTL, azx_readl(chip, GCTL) | |
1640 | ICH6_GCTL_UNSOL); | 1642 | ICH6_GCTL_UNSOL); |
1641 | 1643 | ||
1642 | /* detect codecs */ | 1644 | /* detect codecs */ |
1643 | if (!chip->codec_mask) { | 1645 | if (!chip->codec_mask) { |
1644 | chip->codec_mask = azx_readw(chip, STATESTS); | 1646 | chip->codec_mask = azx_readw(chip, STATESTS); |
1645 | dev_dbg(chip->card->dev, "codec_mask = 0x%x\n", | 1647 | dev_dbg(chip->card->dev, "codec_mask = 0x%x\n", |
1646 | chip->codec_mask); | 1648 | chip->codec_mask); |
1647 | } | 1649 | } |
1648 | 1650 | ||
1649 | return 0; | 1651 | return 0; |
1650 | } | 1652 | } |
1651 | 1653 | ||
1652 | /* enable interrupts */ | 1654 | /* enable interrupts */ |
1653 | static void azx_int_enable(struct azx *chip) | 1655 | static void azx_int_enable(struct azx *chip) |
1654 | { | 1656 | { |
1655 | /* enable controller CIE and GIE */ | 1657 | /* enable controller CIE and GIE */ |
1656 | azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) | | 1658 | azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) | |
1657 | ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN); | 1659 | ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN); |
1658 | } | 1660 | } |
1659 | 1661 | ||
1660 | /* disable interrupts */ | 1662 | /* disable interrupts */ |
1661 | static void azx_int_disable(struct azx *chip) | 1663 | static void azx_int_disable(struct azx *chip) |
1662 | { | 1664 | { |
1663 | int i; | 1665 | int i; |
1664 | 1666 | ||
1665 | /* disable interrupts in stream descriptor */ | 1667 | /* disable interrupts in stream descriptor */ |
1666 | for (i = 0; i < chip->num_streams; i++) { | 1668 | for (i = 0; i < chip->num_streams; i++) { |
1667 | struct azx_dev *azx_dev = &chip->azx_dev[i]; | 1669 | struct azx_dev *azx_dev = &chip->azx_dev[i]; |
1668 | azx_sd_writeb(chip, azx_dev, SD_CTL, | 1670 | azx_sd_writeb(chip, azx_dev, SD_CTL, |
1669 | azx_sd_readb(chip, azx_dev, SD_CTL) & | 1671 | azx_sd_readb(chip, azx_dev, SD_CTL) & |
1670 | ~SD_INT_MASK); | 1672 | ~SD_INT_MASK); |
1671 | } | 1673 | } |
1672 | 1674 | ||
1673 | /* disable SIE for all streams */ | 1675 | /* disable SIE for all streams */ |
1674 | azx_writeb(chip, INTCTL, 0); | 1676 | azx_writeb(chip, INTCTL, 0); |
1675 | 1677 | ||
1676 | /* disable controller CIE and GIE */ | 1678 | /* disable controller CIE and GIE */ |
1677 | azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) & | 1679 | azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) & |
1678 | ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN)); | 1680 | ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN)); |
1679 | } | 1681 | } |
1680 | 1682 | ||
1681 | /* clear interrupts */ | 1683 | /* clear interrupts */ |
1682 | static void azx_int_clear(struct azx *chip) | 1684 | static void azx_int_clear(struct azx *chip) |
1683 | { | 1685 | { |
1684 | int i; | 1686 | int i; |
1685 | 1687 | ||
1686 | /* clear stream status */ | 1688 | /* clear stream status */ |
1687 | for (i = 0; i < chip->num_streams; i++) { | 1689 | for (i = 0; i < chip->num_streams; i++) { |
1688 | struct azx_dev *azx_dev = &chip->azx_dev[i]; | 1690 | struct azx_dev *azx_dev = &chip->azx_dev[i]; |
1689 | azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK); | 1691 | azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK); |
1690 | } | 1692 | } |
1691 | 1693 | ||
1692 | /* clear STATESTS */ | 1694 | /* clear STATESTS */ |
1693 | azx_writew(chip, STATESTS, STATESTS_INT_MASK); | 1695 | azx_writew(chip, STATESTS, STATESTS_INT_MASK); |
1694 | 1696 | ||
1695 | /* clear rirb status */ | 1697 | /* clear rirb status */ |
1696 | azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); | 1698 | azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); |
1697 | 1699 | ||
1698 | /* clear int status */ | 1700 | /* clear int status */ |
1699 | azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM); | 1701 | azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM); |
1700 | } | 1702 | } |
1701 | 1703 | ||
1702 | /* | 1704 | /* |
1703 | * reset and start the controller registers | 1705 | * reset and start the controller registers |
1704 | */ | 1706 | */ |
1705 | void azx_init_chip(struct azx *chip, bool full_reset) | 1707 | void azx_init_chip(struct azx *chip, bool full_reset) |
1706 | { | 1708 | { |
1707 | if (chip->initialized) | 1709 | if (chip->initialized) |
1708 | return; | 1710 | return; |
1709 | 1711 | ||
1710 | /* reset controller */ | 1712 | /* reset controller */ |
1711 | azx_reset(chip, full_reset); | 1713 | azx_reset(chip, full_reset); |
1712 | 1714 | ||
1713 | /* initialize interrupts */ | 1715 | /* initialize interrupts */ |
1714 | azx_int_clear(chip); | 1716 | azx_int_clear(chip); |
1715 | azx_int_enable(chip); | 1717 | azx_int_enable(chip); |
1716 | 1718 | ||
1717 | /* initialize the codec command I/O */ | 1719 | /* initialize the codec command I/O */ |
1718 | if (!chip->single_cmd) | 1720 | if (!chip->single_cmd) |
1719 | azx_init_cmd_io(chip); | 1721 | azx_init_cmd_io(chip); |
1720 | 1722 | ||
1721 | /* program the position buffer */ | 1723 | /* program the position buffer */ |
1722 | azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr); | 1724 | azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr); |
1723 | azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr)); | 1725 | azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr)); |
1724 | 1726 | ||
1725 | chip->initialized = 1; | 1727 | chip->initialized = 1; |
1726 | } | 1728 | } |
1727 | EXPORT_SYMBOL_GPL(azx_init_chip); | 1729 | EXPORT_SYMBOL_GPL(azx_init_chip); |
1728 | 1730 | ||
1729 | void azx_stop_chip(struct azx *chip) | 1731 | void azx_stop_chip(struct azx *chip) |
1730 | { | 1732 | { |
1731 | if (!chip->initialized) | 1733 | if (!chip->initialized) |
1732 | return; | 1734 | return; |
1733 | 1735 | ||
1734 | /* disable interrupts */ | 1736 | /* disable interrupts */ |
1735 | azx_int_disable(chip); | 1737 | azx_int_disable(chip); |
1736 | azx_int_clear(chip); | 1738 | azx_int_clear(chip); |
1737 | 1739 | ||
1738 | /* disable CORB/RIRB */ | 1740 | /* disable CORB/RIRB */ |
1739 | azx_free_cmd_io(chip); | 1741 | azx_free_cmd_io(chip); |
1740 | 1742 | ||
1741 | /* disable position buffer */ | 1743 | /* disable position buffer */ |
1742 | azx_writel(chip, DPLBASE, 0); | 1744 | azx_writel(chip, DPLBASE, 0); |
1743 | azx_writel(chip, DPUBASE, 0); | 1745 | azx_writel(chip, DPUBASE, 0); |
1744 | 1746 | ||
1745 | chip->initialized = 0; | 1747 | chip->initialized = 0; |
1746 | } | 1748 | } |
1747 | EXPORT_SYMBOL_GPL(azx_stop_chip); | 1749 | EXPORT_SYMBOL_GPL(azx_stop_chip); |
1748 | 1750 | ||
1749 | /* | 1751 | /* |
1750 | * interrupt handler | 1752 | * interrupt handler |
1751 | */ | 1753 | */ |
1752 | irqreturn_t azx_interrupt(int irq, void *dev_id) | 1754 | irqreturn_t azx_interrupt(int irq, void *dev_id) |
1753 | { | 1755 | { |
1754 | struct azx *chip = dev_id; | 1756 | struct azx *chip = dev_id; |
1755 | struct azx_dev *azx_dev; | 1757 | struct azx_dev *azx_dev; |
1756 | u32 status; | 1758 | u32 status; |
1757 | u8 sd_status; | 1759 | u8 sd_status; |
1758 | int i; | 1760 | int i; |
1759 | 1761 | ||
1760 | #ifdef CONFIG_PM_RUNTIME | 1762 | #ifdef CONFIG_PM_RUNTIME |
1761 | if (chip->driver_caps & AZX_DCAPS_PM_RUNTIME) | 1763 | if (chip->driver_caps & AZX_DCAPS_PM_RUNTIME) |
1762 | if (!pm_runtime_active(chip->card->dev)) | 1764 | if (!pm_runtime_active(chip->card->dev)) |
1763 | return IRQ_NONE; | 1765 | return IRQ_NONE; |
1764 | #endif | 1766 | #endif |
1765 | 1767 | ||
1766 | spin_lock(&chip->reg_lock); | 1768 | spin_lock(&chip->reg_lock); |
1767 | 1769 | ||
1768 | if (chip->disabled) { | 1770 | if (chip->disabled) { |
1769 | spin_unlock(&chip->reg_lock); | 1771 | spin_unlock(&chip->reg_lock); |
1770 | return IRQ_NONE; | 1772 | return IRQ_NONE; |
1771 | } | 1773 | } |
1772 | 1774 | ||
1773 | status = azx_readl(chip, INTSTS); | 1775 | status = azx_readl(chip, INTSTS); |
1774 | if (status == 0 || status == 0xffffffff) { | 1776 | if (status == 0 || status == 0xffffffff) { |
1775 | spin_unlock(&chip->reg_lock); | 1777 | spin_unlock(&chip->reg_lock); |
1776 | return IRQ_NONE; | 1778 | return IRQ_NONE; |
1777 | } | 1779 | } |
1778 | 1780 | ||
1779 | for (i = 0; i < chip->num_streams; i++) { | 1781 | for (i = 0; i < chip->num_streams; i++) { |
1780 | azx_dev = &chip->azx_dev[i]; | 1782 | azx_dev = &chip->azx_dev[i]; |
1781 | if (status & azx_dev->sd_int_sta_mask) { | 1783 | if (status & azx_dev->sd_int_sta_mask) { |
1782 | sd_status = azx_sd_readb(chip, azx_dev, SD_STS); | 1784 | sd_status = azx_sd_readb(chip, azx_dev, SD_STS); |
1783 | azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK); | 1785 | azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK); |
1784 | if (!azx_dev->substream || !azx_dev->running || | 1786 | if (!azx_dev->substream || !azx_dev->running || |
1785 | !(sd_status & SD_INT_COMPLETE)) | 1787 | !(sd_status & SD_INT_COMPLETE)) |
1786 | continue; | 1788 | continue; |
1787 | /* check whether this IRQ is really acceptable */ | 1789 | /* check whether this IRQ is really acceptable */ |
1788 | if (!chip->ops->position_check || | 1790 | if (!chip->ops->position_check || |
1789 | chip->ops->position_check(chip, azx_dev)) { | 1791 | chip->ops->position_check(chip, azx_dev)) { |
1790 | spin_unlock(&chip->reg_lock); | 1792 | spin_unlock(&chip->reg_lock); |
1791 | snd_pcm_period_elapsed(azx_dev->substream); | 1793 | snd_pcm_period_elapsed(azx_dev->substream); |
1792 | spin_lock(&chip->reg_lock); | 1794 | spin_lock(&chip->reg_lock); |
1793 | } | 1795 | } |
1794 | } | 1796 | } |
1795 | } | 1797 | } |
1796 | 1798 | ||
1797 | /* clear rirb int */ | 1799 | /* clear rirb int */ |
1798 | status = azx_readb(chip, RIRBSTS); | 1800 | status = azx_readb(chip, RIRBSTS); |
1799 | if (status & RIRB_INT_MASK) { | 1801 | if (status & RIRB_INT_MASK) { |
1800 | if (status & RIRB_INT_RESPONSE) { | 1802 | if (status & RIRB_INT_RESPONSE) { |
1801 | if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY) | 1803 | if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY) |
1802 | udelay(80); | 1804 | udelay(80); |
1803 | azx_update_rirb(chip); | 1805 | azx_update_rirb(chip); |
1804 | } | 1806 | } |
1805 | azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); | 1807 | azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); |
1806 | } | 1808 | } |
1807 | 1809 | ||
1808 | spin_unlock(&chip->reg_lock); | 1810 | spin_unlock(&chip->reg_lock); |
1809 | 1811 | ||
1810 | return IRQ_HANDLED; | 1812 | return IRQ_HANDLED; |
1811 | } | 1813 | } |
1812 | EXPORT_SYMBOL_GPL(azx_interrupt); | 1814 | EXPORT_SYMBOL_GPL(azx_interrupt); |
1813 | 1815 | ||
1814 | /* | 1816 | /* |
1815 | * Codec initerface | 1817 | * Codec initerface |
1816 | */ | 1818 | */ |
1817 | 1819 | ||
1818 | /* | 1820 | /* |
1819 | * Probe the given codec address | 1821 | * Probe the given codec address |
1820 | */ | 1822 | */ |
1821 | static int probe_codec(struct azx *chip, int addr) | 1823 | static int probe_codec(struct azx *chip, int addr) |
1822 | { | 1824 | { |
1823 | unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | | 1825 | unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | |
1824 | (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; | 1826 | (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; |
1825 | unsigned int res; | 1827 | unsigned int res; |
1826 | 1828 | ||
1827 | mutex_lock(&chip->bus->cmd_mutex); | 1829 | mutex_lock(&chip->bus->cmd_mutex); |
1828 | chip->probing = 1; | 1830 | chip->probing = 1; |
1829 | azx_send_cmd(chip->bus, cmd); | 1831 | azx_send_cmd(chip->bus, cmd); |
1830 | res = azx_get_response(chip->bus, addr); | 1832 | res = azx_get_response(chip->bus, addr); |
1831 | chip->probing = 0; | 1833 | chip->probing = 0; |
1832 | mutex_unlock(&chip->bus->cmd_mutex); | 1834 | mutex_unlock(&chip->bus->cmd_mutex); |
1833 | if (res == -1) | 1835 | if (res == -1) |
1834 | return -EIO; | 1836 | return -EIO; |
1835 | dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr); | 1837 | dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr); |
1836 | return 0; | 1838 | return 0; |
1837 | } | 1839 | } |
1838 | 1840 | ||
1839 | static void azx_bus_reset(struct hda_bus *bus) | 1841 | static void azx_bus_reset(struct hda_bus *bus) |
1840 | { | 1842 | { |
1841 | struct azx *chip = bus->private_data; | 1843 | struct azx *chip = bus->private_data; |
1842 | 1844 | ||
1843 | bus->in_reset = 1; | 1845 | bus->in_reset = 1; |
1844 | azx_stop_chip(chip); | 1846 | azx_stop_chip(chip); |
1845 | azx_init_chip(chip, true); | 1847 | azx_init_chip(chip, true); |
1846 | #ifdef CONFIG_PM | 1848 | #ifdef CONFIG_PM |
1847 | if (chip->initialized) { | 1849 | if (chip->initialized) { |
1848 | struct azx_pcm *p; | 1850 | struct azx_pcm *p; |
1849 | list_for_each_entry(p, &chip->pcm_list, list) | 1851 | list_for_each_entry(p, &chip->pcm_list, list) |
1850 | snd_pcm_suspend_all(p->pcm); | 1852 | snd_pcm_suspend_all(p->pcm); |
1851 | snd_hda_suspend(chip->bus); | 1853 | snd_hda_suspend(chip->bus); |
1852 | snd_hda_resume(chip->bus); | 1854 | snd_hda_resume(chip->bus); |
1853 | } | 1855 | } |
1854 | #endif | 1856 | #endif |
1855 | bus->in_reset = 0; | 1857 | bus->in_reset = 0; |
1856 | } | 1858 | } |
1857 | 1859 | ||
1858 | #ifdef CONFIG_PM | 1860 | #ifdef CONFIG_PM |
1859 | /* power-up/down the controller */ | 1861 | /* power-up/down the controller */ |
1860 | static void azx_power_notify(struct hda_bus *bus, bool power_up) | 1862 | static void azx_power_notify(struct hda_bus *bus, bool power_up) |
1861 | { | 1863 | { |
1862 | struct azx *chip = bus->private_data; | 1864 | struct azx *chip = bus->private_data; |
1863 | 1865 | ||
1864 | if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME)) | 1866 | if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME)) |
1865 | return; | 1867 | return; |
1866 | 1868 | ||
1867 | if (power_up) | 1869 | if (power_up) |
1868 | pm_runtime_get_sync(chip->card->dev); | 1870 | pm_runtime_get_sync(chip->card->dev); |
1869 | else | 1871 | else |
1870 | pm_runtime_put_sync(chip->card->dev); | 1872 | pm_runtime_put_sync(chip->card->dev); |
1871 | } | 1873 | } |
1872 | #endif | 1874 | #endif |
1873 | 1875 | ||
1874 | static int get_jackpoll_interval(struct azx *chip) | 1876 | static int get_jackpoll_interval(struct azx *chip) |
1875 | { | 1877 | { |
1876 | int i; | 1878 | int i; |
1877 | unsigned int j; | 1879 | unsigned int j; |
1878 | 1880 | ||
1879 | if (!chip->jackpoll_ms) | 1881 | if (!chip->jackpoll_ms) |
1880 | return 0; | 1882 | return 0; |
1881 | 1883 | ||
1882 | i = chip->jackpoll_ms[chip->dev_index]; | 1884 | i = chip->jackpoll_ms[chip->dev_index]; |
1883 | if (i == 0) | 1885 | if (i == 0) |
1884 | return 0; | 1886 | return 0; |
1885 | if (i < 50 || i > 60000) | 1887 | if (i < 50 || i > 60000) |
1886 | j = 0; | 1888 | j = 0; |
1887 | else | 1889 | else |
1888 | j = msecs_to_jiffies(i); | 1890 | j = msecs_to_jiffies(i); |
1889 | if (j == 0) | 1891 | if (j == 0) |
1890 | dev_warn(chip->card->dev, | 1892 | dev_warn(chip->card->dev, |
1891 | "jackpoll_ms value out of range: %d\n", i); | 1893 | "jackpoll_ms value out of range: %d\n", i); |
1892 | return j; | 1894 | return j; |
1893 | } | 1895 | } |
1894 | 1896 | ||
1895 | /* Codec initialization */ | 1897 | /* Codec initialization */ |
1896 | int azx_codec_create(struct azx *chip, const char *model, | 1898 | int azx_codec_create(struct azx *chip, const char *model, |
1897 | unsigned int max_slots, | 1899 | unsigned int max_slots, |
1898 | int *power_save_to) | 1900 | int *power_save_to) |
1899 | { | 1901 | { |
1900 | struct hda_bus_template bus_temp; | 1902 | struct hda_bus_template bus_temp; |
1901 | int c, codecs, err; | 1903 | int c, codecs, err; |
1902 | 1904 | ||
1903 | memset(&bus_temp, 0, sizeof(bus_temp)); | 1905 | memset(&bus_temp, 0, sizeof(bus_temp)); |
1904 | bus_temp.private_data = chip; | 1906 | bus_temp.private_data = chip; |
1905 | bus_temp.modelname = model; | 1907 | bus_temp.modelname = model; |
1906 | bus_temp.pci = chip->pci; | 1908 | bus_temp.pci = chip->pci; |
1907 | bus_temp.ops.command = azx_send_cmd; | 1909 | bus_temp.ops.command = azx_send_cmd; |
1908 | bus_temp.ops.get_response = azx_get_response; | 1910 | bus_temp.ops.get_response = azx_get_response; |
1909 | bus_temp.ops.attach_pcm = azx_attach_pcm_stream; | 1911 | bus_temp.ops.attach_pcm = azx_attach_pcm_stream; |
1910 | bus_temp.ops.bus_reset = azx_bus_reset; | 1912 | bus_temp.ops.bus_reset = azx_bus_reset; |
1911 | #ifdef CONFIG_PM | 1913 | #ifdef CONFIG_PM |
1912 | bus_temp.power_save = power_save_to; | 1914 | bus_temp.power_save = power_save_to; |
1913 | bus_temp.ops.pm_notify = azx_power_notify; | 1915 | bus_temp.ops.pm_notify = azx_power_notify; |
1914 | #endif | 1916 | #endif |
1915 | #ifdef CONFIG_SND_HDA_DSP_LOADER | 1917 | #ifdef CONFIG_SND_HDA_DSP_LOADER |
1916 | bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare; | 1918 | bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare; |
1917 | bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger; | 1919 | bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger; |
1918 | bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup; | 1920 | bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup; |
1919 | #endif | 1921 | #endif |
1920 | 1922 | ||
1921 | err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus); | 1923 | err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus); |
1922 | if (err < 0) | 1924 | if (err < 0) |
1923 | return err; | 1925 | return err; |
1924 | 1926 | ||
1925 | if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) { | 1927 | if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) { |
1926 | dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); | 1928 | dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); |
1927 | chip->bus->needs_damn_long_delay = 1; | 1929 | chip->bus->needs_damn_long_delay = 1; |
1928 | } | 1930 | } |
1929 | 1931 | ||
1930 | codecs = 0; | 1932 | codecs = 0; |
1931 | if (!max_slots) | 1933 | if (!max_slots) |
1932 | max_slots = AZX_DEFAULT_CODECS; | 1934 | max_slots = AZX_DEFAULT_CODECS; |
1933 | 1935 | ||
1934 | /* First try to probe all given codec slots */ | 1936 | /* First try to probe all given codec slots */ |
1935 | for (c = 0; c < max_slots; c++) { | 1937 | for (c = 0; c < max_slots; c++) { |
1936 | if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) { | 1938 | if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) { |
1937 | if (probe_codec(chip, c) < 0) { | 1939 | if (probe_codec(chip, c) < 0) { |
1938 | /* Some BIOSen give you wrong codec addresses | 1940 | /* Some BIOSen give you wrong codec addresses |
1939 | * that don't exist | 1941 | * that don't exist |
1940 | */ | 1942 | */ |
1941 | dev_warn(chip->card->dev, | 1943 | dev_warn(chip->card->dev, |
1942 | "Codec #%d probe error; disabling it...\n", c); | 1944 | "Codec #%d probe error; disabling it...\n", c); |
1943 | chip->codec_mask &= ~(1 << c); | 1945 | chip->codec_mask &= ~(1 << c); |
1944 | /* More badly, accessing to a non-existing | 1946 | /* More badly, accessing to a non-existing |
1945 | * codec often screws up the controller chip, | 1947 | * codec often screws up the controller chip, |
1946 | * and disturbs the further communications. | 1948 | * and disturbs the further communications. |
1947 | * Thus if an error occurs during probing, | 1949 | * Thus if an error occurs during probing, |
1948 | * better to reset the controller chip to | 1950 | * better to reset the controller chip to |
1949 | * get back to the sanity state. | 1951 | * get back to the sanity state. |
1950 | */ | 1952 | */ |
1951 | azx_stop_chip(chip); | 1953 | azx_stop_chip(chip); |
1952 | azx_init_chip(chip, true); | 1954 | azx_init_chip(chip, true); |
1953 | } | 1955 | } |
1954 | } | 1956 | } |
1955 | } | 1957 | } |
1956 | 1958 | ||
1957 | /* AMD chipsets often cause the communication stalls upon certain | 1959 | /* AMD chipsets often cause the communication stalls upon certain |
1958 | * sequence like the pin-detection. It seems that forcing the synced | 1960 | * sequence like the pin-detection. It seems that forcing the synced |
1959 | * access works around the stall. Grrr... | 1961 | * access works around the stall. Grrr... |
1960 | */ | 1962 | */ |
1961 | if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) { | 1963 | if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) { |
1962 | dev_dbg(chip->card->dev, "Enable sync_write for stable communication\n"); | 1964 | dev_dbg(chip->card->dev, "Enable sync_write for stable communication\n"); |
1963 | chip->bus->sync_write = 1; | 1965 | chip->bus->sync_write = 1; |
1964 | chip->bus->allow_bus_reset = 1; | 1966 | chip->bus->allow_bus_reset = 1; |
1965 | } | 1967 | } |
1966 | 1968 | ||
1967 | /* Then create codec instances */ | 1969 | /* Then create codec instances */ |
1968 | for (c = 0; c < max_slots; c++) { | 1970 | for (c = 0; c < max_slots; c++) { |
1969 | if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) { | 1971 | if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) { |
1970 | struct hda_codec *codec; | 1972 | struct hda_codec *codec; |
1971 | err = snd_hda_codec_new(chip->bus, c, &codec); | 1973 | err = snd_hda_codec_new(chip->bus, c, &codec); |
1972 | if (err < 0) | 1974 | if (err < 0) |
1973 | continue; | 1975 | continue; |
1974 | codec->jackpoll_interval = get_jackpoll_interval(chip); | 1976 | codec->jackpoll_interval = get_jackpoll_interval(chip); |
1975 | codec->beep_mode = chip->beep_mode; | 1977 | codec->beep_mode = chip->beep_mode; |
1976 | codecs++; | 1978 | codecs++; |
1977 | } | 1979 | } |
1978 | } | 1980 | } |
1979 | if (!codecs) { | 1981 | if (!codecs) { |
1980 | dev_err(chip->card->dev, "no codecs initialized\n"); | 1982 | dev_err(chip->card->dev, "no codecs initialized\n"); |
1981 | return -ENXIO; | 1983 | return -ENXIO; |
1982 | } | 1984 | } |
1983 | return 0; | 1985 | return 0; |
1984 | } | 1986 | } |
1985 | EXPORT_SYMBOL_GPL(azx_codec_create); | 1987 | EXPORT_SYMBOL_GPL(azx_codec_create); |
1986 | 1988 | ||
1987 | /* configure each codec instance */ | 1989 | /* configure each codec instance */ |
1988 | int azx_codec_configure(struct azx *chip) | 1990 | int azx_codec_configure(struct azx *chip) |
1989 | { | 1991 | { |
1990 | struct hda_codec *codec; | 1992 | struct hda_codec *codec; |
1991 | list_for_each_entry(codec, &chip->bus->codec_list, list) { | 1993 | list_for_each_entry(codec, &chip->bus->codec_list, list) { |
1992 | snd_hda_codec_configure(codec); | 1994 | snd_hda_codec_configure(codec); |
1993 | } | 1995 | } |
1994 | return 0; | 1996 | return 0; |
1995 | } | 1997 | } |
1996 | EXPORT_SYMBOL_GPL(azx_codec_configure); | 1998 | EXPORT_SYMBOL_GPL(azx_codec_configure); |
1997 | 1999 | ||
1998 | /* mixer creation - all stuff is implemented in hda module */ | 2000 | /* mixer creation - all stuff is implemented in hda module */ |
1999 | int azx_mixer_create(struct azx *chip) | 2001 | int azx_mixer_create(struct azx *chip) |
2000 | { | 2002 | { |
2001 | return snd_hda_build_controls(chip->bus); | 2003 | return snd_hda_build_controls(chip->bus); |
2002 | } | 2004 | } |
2003 | EXPORT_SYMBOL_GPL(azx_mixer_create); | 2005 | EXPORT_SYMBOL_GPL(azx_mixer_create); |
2004 | 2006 | ||
2005 | 2007 | ||
2006 | /* initialize SD streams */ | 2008 | /* initialize SD streams */ |
2007 | int azx_init_stream(struct azx *chip) | 2009 | int azx_init_stream(struct azx *chip) |
2008 | { | 2010 | { |
2009 | int i; | 2011 | int i; |
2010 | 2012 | ||
2011 | /* initialize each stream (aka device) | 2013 | /* initialize each stream (aka device) |
2012 | * assign the starting bdl address to each stream (device) | 2014 | * assign the starting bdl address to each stream (device) |
2013 | * and initialize | 2015 | * and initialize |
2014 | */ | 2016 | */ |
2015 | for (i = 0; i < chip->num_streams; i++) { | 2017 | for (i = 0; i < chip->num_streams; i++) { |
2016 | struct azx_dev *azx_dev = &chip->azx_dev[i]; | 2018 | struct azx_dev *azx_dev = &chip->azx_dev[i]; |
2017 | azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8); | 2019 | azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8); |
2018 | /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ | 2020 | /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ |
2019 | azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80); | 2021 | azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80); |
2020 | /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */ | 2022 | /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */ |
2021 | azx_dev->sd_int_sta_mask = 1 << i; | 2023 | azx_dev->sd_int_sta_mask = 1 << i; |
2022 | /* stream tag: must be non-zero and unique */ | 2024 | /* stream tag: must be non-zero and unique */ |
2023 | azx_dev->index = i; | 2025 | azx_dev->index = i; |
2024 | azx_dev->stream_tag = i + 1; | 2026 | azx_dev->stream_tag = i + 1; |
2025 | } | 2027 | } |
2026 | 2028 | ||
2027 | return 0; | 2029 | return 0; |
2028 | } | 2030 | } |
2029 | EXPORT_SYMBOL_GPL(azx_init_stream); | 2031 | EXPORT_SYMBOL_GPL(azx_init_stream); |
2030 | 2032 |
sound/pci/hda/hda_intel.c
1 | /* | 1 | /* |
2 | * | 2 | * |
3 | * hda_intel.c - Implementation of primary alsa driver code base | 3 | * hda_intel.c - Implementation of primary alsa driver code base |
4 | * for Intel HD Audio. | 4 | * for Intel HD Audio. |
5 | * | 5 | * |
6 | * Copyright(c) 2004 Intel Corporation. All rights reserved. | 6 | * Copyright(c) 2004 Intel Corporation. All rights reserved. |
7 | * | 7 | * |
8 | * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> | 8 | * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> |
9 | * PeiSen Hou <pshou@realtek.com.tw> | 9 | * PeiSen Hou <pshou@realtek.com.tw> |
10 | * | 10 | * |
11 | * This program is free software; you can redistribute it and/or modify it | 11 | * This program is free software; you can redistribute it and/or modify it |
12 | * under the terms of the GNU General Public License as published by the Free | 12 | * under the terms of the GNU General Public License as published by the Free |
13 | * Software Foundation; either version 2 of the License, or (at your option) | 13 | * Software Foundation; either version 2 of the License, or (at your option) |
14 | * any later version. | 14 | * any later version. |
15 | * | 15 | * |
16 | * This program is distributed in the hope that it will be useful, but WITHOUT | 16 | * This program is distributed in the hope that it will be useful, but WITHOUT |
17 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | 17 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
18 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | 18 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
19 | * more details. | 19 | * more details. |
20 | * | 20 | * |
21 | * You should have received a copy of the GNU General Public License along with | 21 | * You should have received a copy of the GNU General Public License along with |
22 | * this program; if not, write to the Free Software Foundation, Inc., 59 | 22 | * this program; if not, write to the Free Software Foundation, Inc., 59 |
23 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | 23 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
24 | * | 24 | * |
25 | * CONTACTS: | 25 | * CONTACTS: |
26 | * | 26 | * |
27 | * Matt Jared matt.jared@intel.com | 27 | * Matt Jared matt.jared@intel.com |
28 | * Andy Kopp andy.kopp@intel.com | 28 | * Andy Kopp andy.kopp@intel.com |
29 | * Dan Kogan dan.d.kogan@intel.com | 29 | * Dan Kogan dan.d.kogan@intel.com |
30 | * | 30 | * |
31 | * CHANGES: | 31 | * CHANGES: |
32 | * | 32 | * |
33 | * 2004.12.01 Major rewrite by tiwai, merged the work of pshou | 33 | * 2004.12.01 Major rewrite by tiwai, merged the work of pshou |
34 | * | 34 | * |
35 | */ | 35 | */ |
36 | 36 | ||
37 | #include <linux/delay.h> | 37 | #include <linux/delay.h> |
38 | #include <linux/interrupt.h> | 38 | #include <linux/interrupt.h> |
39 | #include <linux/kernel.h> | 39 | #include <linux/kernel.h> |
40 | #include <linux/module.h> | 40 | #include <linux/module.h> |
41 | #include <linux/dma-mapping.h> | 41 | #include <linux/dma-mapping.h> |
42 | #include <linux/moduleparam.h> | 42 | #include <linux/moduleparam.h> |
43 | #include <linux/init.h> | 43 | #include <linux/init.h> |
44 | #include <linux/slab.h> | 44 | #include <linux/slab.h> |
45 | #include <linux/pci.h> | 45 | #include <linux/pci.h> |
46 | #include <linux/mutex.h> | 46 | #include <linux/mutex.h> |
47 | #include <linux/reboot.h> | 47 | #include <linux/reboot.h> |
48 | #include <linux/io.h> | 48 | #include <linux/io.h> |
49 | #include <linux/pm_runtime.h> | 49 | #include <linux/pm_runtime.h> |
50 | #include <linux/clocksource.h> | 50 | #include <linux/clocksource.h> |
51 | #include <linux/time.h> | 51 | #include <linux/time.h> |
52 | #include <linux/completion.h> | 52 | #include <linux/completion.h> |
53 | 53 | ||
54 | #ifdef CONFIG_X86 | 54 | #ifdef CONFIG_X86 |
55 | /* for snoop control */ | 55 | /* for snoop control */ |
56 | #include <asm/pgtable.h> | 56 | #include <asm/pgtable.h> |
57 | #include <asm/cacheflush.h> | 57 | #include <asm/cacheflush.h> |
58 | #endif | 58 | #endif |
59 | #include <sound/core.h> | 59 | #include <sound/core.h> |
60 | #include <sound/initval.h> | 60 | #include <sound/initval.h> |
61 | #include <linux/vgaarb.h> | 61 | #include <linux/vgaarb.h> |
62 | #include <linux/vga_switcheroo.h> | 62 | #include <linux/vga_switcheroo.h> |
63 | #include <linux/firmware.h> | 63 | #include <linux/firmware.h> |
64 | #include "hda_codec.h" | 64 | #include "hda_codec.h" |
65 | #include "hda_i915.h" | 65 | #include "hda_i915.h" |
66 | #include "hda_controller.h" | 66 | #include "hda_controller.h" |
67 | #include "hda_priv.h" | 67 | #include "hda_priv.h" |
68 | 68 | ||
69 | 69 | ||
70 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; | 70 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; |
71 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; | 71 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; |
72 | static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; | 72 | static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; |
73 | static char *model[SNDRV_CARDS]; | 73 | static char *model[SNDRV_CARDS]; |
74 | static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; | 74 | static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; |
75 | static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; | 75 | static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; |
76 | static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; | 76 | static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; |
77 | static int probe_only[SNDRV_CARDS]; | 77 | static int probe_only[SNDRV_CARDS]; |
78 | static int jackpoll_ms[SNDRV_CARDS]; | 78 | static int jackpoll_ms[SNDRV_CARDS]; |
79 | static bool single_cmd; | 79 | static bool single_cmd; |
80 | static int enable_msi = -1; | 80 | static int enable_msi = -1; |
81 | #ifdef CONFIG_SND_HDA_PATCH_LOADER | 81 | #ifdef CONFIG_SND_HDA_PATCH_LOADER |
82 | static char *patch[SNDRV_CARDS]; | 82 | static char *patch[SNDRV_CARDS]; |
83 | #endif | 83 | #endif |
84 | #ifdef CONFIG_SND_HDA_INPUT_BEEP | 84 | #ifdef CONFIG_SND_HDA_INPUT_BEEP |
85 | static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = | 85 | static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = |
86 | CONFIG_SND_HDA_INPUT_BEEP_MODE}; | 86 | CONFIG_SND_HDA_INPUT_BEEP_MODE}; |
87 | #endif | 87 | #endif |
88 | 88 | ||
89 | module_param_array(index, int, NULL, 0444); | 89 | module_param_array(index, int, NULL, 0444); |
90 | MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); | 90 | MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); |
91 | module_param_array(id, charp, NULL, 0444); | 91 | module_param_array(id, charp, NULL, 0444); |
92 | MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); | 92 | MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); |
93 | module_param_array(enable, bool, NULL, 0444); | 93 | module_param_array(enable, bool, NULL, 0444); |
94 | MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); | 94 | MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); |
95 | module_param_array(model, charp, NULL, 0444); | 95 | module_param_array(model, charp, NULL, 0444); |
96 | MODULE_PARM_DESC(model, "Use the given board model."); | 96 | MODULE_PARM_DESC(model, "Use the given board model."); |
97 | module_param_array(position_fix, int, NULL, 0444); | 97 | module_param_array(position_fix, int, NULL, 0444); |
98 | MODULE_PARM_DESC(position_fix, "DMA pointer read method." | 98 | MODULE_PARM_DESC(position_fix, "DMA pointer read method." |
99 | "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO)."); | 99 | "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO)."); |
100 | module_param_array(bdl_pos_adj, int, NULL, 0644); | 100 | module_param_array(bdl_pos_adj, int, NULL, 0644); |
101 | MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); | 101 | MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); |
102 | module_param_array(probe_mask, int, NULL, 0444); | 102 | module_param_array(probe_mask, int, NULL, 0444); |
103 | MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); | 103 | MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); |
104 | module_param_array(probe_only, int, NULL, 0444); | 104 | module_param_array(probe_only, int, NULL, 0444); |
105 | MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); | 105 | MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); |
106 | module_param_array(jackpoll_ms, int, NULL, 0444); | 106 | module_param_array(jackpoll_ms, int, NULL, 0444); |
107 | MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); | 107 | MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); |
108 | module_param(single_cmd, bool, 0444); | 108 | module_param(single_cmd, bool, 0444); |
109 | MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " | 109 | MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " |
110 | "(for debugging only)."); | 110 | "(for debugging only)."); |
111 | module_param(enable_msi, bint, 0444); | 111 | module_param(enable_msi, bint, 0444); |
112 | MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); | 112 | MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); |
113 | #ifdef CONFIG_SND_HDA_PATCH_LOADER | 113 | #ifdef CONFIG_SND_HDA_PATCH_LOADER |
114 | module_param_array(patch, charp, NULL, 0444); | 114 | module_param_array(patch, charp, NULL, 0444); |
115 | MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); | 115 | MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); |
116 | #endif | 116 | #endif |
117 | #ifdef CONFIG_SND_HDA_INPUT_BEEP | 117 | #ifdef CONFIG_SND_HDA_INPUT_BEEP |
118 | module_param_array(beep_mode, bool, NULL, 0444); | 118 | module_param_array(beep_mode, bool, NULL, 0444); |
119 | MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " | 119 | MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " |
120 | "(0=off, 1=on) (default=1)."); | 120 | "(0=off, 1=on) (default=1)."); |
121 | #endif | 121 | #endif |
122 | 122 | ||
123 | #ifdef CONFIG_PM | 123 | #ifdef CONFIG_PM |
124 | static int param_set_xint(const char *val, const struct kernel_param *kp); | 124 | static int param_set_xint(const char *val, const struct kernel_param *kp); |
125 | static struct kernel_param_ops param_ops_xint = { | 125 | static struct kernel_param_ops param_ops_xint = { |
126 | .set = param_set_xint, | 126 | .set = param_set_xint, |
127 | .get = param_get_int, | 127 | .get = param_get_int, |
128 | }; | 128 | }; |
129 | #define param_check_xint param_check_int | 129 | #define param_check_xint param_check_int |
130 | 130 | ||
131 | static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; | 131 | static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; |
132 | static int *power_save_addr = &power_save; | 132 | static int *power_save_addr = &power_save; |
133 | module_param(power_save, xint, 0644); | 133 | module_param(power_save, xint, 0644); |
134 | MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " | 134 | MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " |
135 | "(in second, 0 = disable)."); | 135 | "(in second, 0 = disable)."); |
136 | 136 | ||
137 | /* reset the HD-audio controller in power save mode. | 137 | /* reset the HD-audio controller in power save mode. |
138 | * this may give more power-saving, but will take longer time to | 138 | * this may give more power-saving, but will take longer time to |
139 | * wake up. | 139 | * wake up. |
140 | */ | 140 | */ |
141 | static bool power_save_controller = 1; | 141 | static bool power_save_controller = 1; |
142 | module_param(power_save_controller, bool, 0644); | 142 | module_param(power_save_controller, bool, 0644); |
143 | MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); | 143 | MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); |
144 | #else | 144 | #else |
145 | static int *power_save_addr; | 145 | static int *power_save_addr; |
146 | #endif /* CONFIG_PM */ | 146 | #endif /* CONFIG_PM */ |
147 | 147 | ||
148 | static int align_buffer_size = -1; | 148 | static int align_buffer_size = -1; |
149 | module_param(align_buffer_size, bint, 0644); | 149 | module_param(align_buffer_size, bint, 0644); |
150 | MODULE_PARM_DESC(align_buffer_size, | 150 | MODULE_PARM_DESC(align_buffer_size, |
151 | "Force buffer and period sizes to be multiple of 128 bytes."); | 151 | "Force buffer and period sizes to be multiple of 128 bytes."); |
152 | 152 | ||
153 | #ifdef CONFIG_X86 | 153 | #ifdef CONFIG_X86 |
154 | static bool hda_snoop = true; | 154 | static bool hda_snoop = true; |
155 | module_param_named(snoop, hda_snoop, bool, 0444); | 155 | module_param_named(snoop, hda_snoop, bool, 0444); |
156 | MODULE_PARM_DESC(snoop, "Enable/disable snooping"); | 156 | MODULE_PARM_DESC(snoop, "Enable/disable snooping"); |
157 | #else | 157 | #else |
158 | #define hda_snoop true | 158 | #define hda_snoop true |
159 | #endif | 159 | #endif |
160 | 160 | ||
161 | 161 | ||
162 | MODULE_LICENSE("GPL"); | 162 | MODULE_LICENSE("GPL"); |
163 | MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," | 163 | MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," |
164 | "{Intel, ICH6M}," | 164 | "{Intel, ICH6M}," |
165 | "{Intel, ICH7}," | 165 | "{Intel, ICH7}," |
166 | "{Intel, ESB2}," | 166 | "{Intel, ESB2}," |
167 | "{Intel, ICH8}," | 167 | "{Intel, ICH8}," |
168 | "{Intel, ICH9}," | 168 | "{Intel, ICH9}," |
169 | "{Intel, ICH10}," | 169 | "{Intel, ICH10}," |
170 | "{Intel, PCH}," | 170 | "{Intel, PCH}," |
171 | "{Intel, CPT}," | 171 | "{Intel, CPT}," |
172 | "{Intel, PPT}," | 172 | "{Intel, PPT}," |
173 | "{Intel, LPT}," | 173 | "{Intel, LPT}," |
174 | "{Intel, LPT_LP}," | 174 | "{Intel, LPT_LP}," |
175 | "{Intel, WPT_LP}," | 175 | "{Intel, WPT_LP}," |
176 | "{Intel, HPT}," | 176 | "{Intel, HPT}," |
177 | "{Intel, PBG}," | 177 | "{Intel, PBG}," |
178 | "{Intel, SCH}," | 178 | "{Intel, SCH}," |
179 | "{ATI, SB450}," | 179 | "{ATI, SB450}," |
180 | "{ATI, SB600}," | 180 | "{ATI, SB600}," |
181 | "{ATI, RS600}," | 181 | "{ATI, RS600}," |
182 | "{ATI, RS690}," | 182 | "{ATI, RS690}," |
183 | "{ATI, RS780}," | 183 | "{ATI, RS780}," |
184 | "{ATI, R600}," | 184 | "{ATI, R600}," |
185 | "{ATI, RV630}," | 185 | "{ATI, RV630}," |
186 | "{ATI, RV610}," | 186 | "{ATI, RV610}," |
187 | "{ATI, RV670}," | 187 | "{ATI, RV670}," |
188 | "{ATI, RV635}," | 188 | "{ATI, RV635}," |
189 | "{ATI, RV620}," | 189 | "{ATI, RV620}," |
190 | "{ATI, RV770}," | 190 | "{ATI, RV770}," |
191 | "{VIA, VT8251}," | 191 | "{VIA, VT8251}," |
192 | "{VIA, VT8237A}," | 192 | "{VIA, VT8237A}," |
193 | "{SiS, SIS966}," | 193 | "{SiS, SIS966}," |
194 | "{ULI, M5461}}"); | 194 | "{ULI, M5461}}"); |
195 | MODULE_DESCRIPTION("Intel HDA driver"); | 195 | MODULE_DESCRIPTION("Intel HDA driver"); |
196 | 196 | ||
197 | #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) | 197 | #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) |
198 | #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) | 198 | #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) |
199 | #define SUPPORT_VGA_SWITCHEROO | 199 | #define SUPPORT_VGA_SWITCHEROO |
200 | #endif | 200 | #endif |
201 | #endif | 201 | #endif |
202 | 202 | ||
203 | 203 | ||
204 | /* | 204 | /* |
205 | */ | 205 | */ |
206 | 206 | ||
207 | /* driver types */ | 207 | /* driver types */ |
208 | enum { | 208 | enum { |
209 | AZX_DRIVER_ICH, | 209 | AZX_DRIVER_ICH, |
210 | AZX_DRIVER_PCH, | 210 | AZX_DRIVER_PCH, |
211 | AZX_DRIVER_SCH, | 211 | AZX_DRIVER_SCH, |
212 | AZX_DRIVER_HDMI, | 212 | AZX_DRIVER_HDMI, |
213 | AZX_DRIVER_ATI, | 213 | AZX_DRIVER_ATI, |
214 | AZX_DRIVER_ATIHDMI, | 214 | AZX_DRIVER_ATIHDMI, |
215 | AZX_DRIVER_ATIHDMI_NS, | 215 | AZX_DRIVER_ATIHDMI_NS, |
216 | AZX_DRIVER_VIA, | 216 | AZX_DRIVER_VIA, |
217 | AZX_DRIVER_SIS, | 217 | AZX_DRIVER_SIS, |
218 | AZX_DRIVER_ULI, | 218 | AZX_DRIVER_ULI, |
219 | AZX_DRIVER_NVIDIA, | 219 | AZX_DRIVER_NVIDIA, |
220 | AZX_DRIVER_TERA, | 220 | AZX_DRIVER_TERA, |
221 | AZX_DRIVER_CTX, | 221 | AZX_DRIVER_CTX, |
222 | AZX_DRIVER_CTHDA, | 222 | AZX_DRIVER_CTHDA, |
223 | AZX_DRIVER_GENERIC, | 223 | AZX_DRIVER_GENERIC, |
224 | AZX_NUM_DRIVERS, /* keep this as last entry */ | 224 | AZX_NUM_DRIVERS, /* keep this as last entry */ |
225 | }; | 225 | }; |
226 | 226 | ||
227 | /* quirks for Intel PCH */ | 227 | /* quirks for Intel PCH */ |
228 | #define AZX_DCAPS_INTEL_PCH_NOPM \ | 228 | #define AZX_DCAPS_INTEL_PCH_NOPM \ |
229 | (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \ | 229 | (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \ |
230 | AZX_DCAPS_COUNT_LPIB_DELAY) | 230 | AZX_DCAPS_COUNT_LPIB_DELAY) |
231 | 231 | ||
232 | #define AZX_DCAPS_INTEL_PCH \ | 232 | #define AZX_DCAPS_INTEL_PCH \ |
233 | (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME) | 233 | (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME) |
234 | 234 | ||
235 | #define AZX_DCAPS_INTEL_HASWELL \ | 235 | #define AZX_DCAPS_INTEL_HASWELL \ |
236 | (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \ | 236 | (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \ |
237 | AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME | \ | 237 | AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME | \ |
238 | AZX_DCAPS_I915_POWERWELL) | 238 | AZX_DCAPS_I915_POWERWELL) |
239 | 239 | ||
240 | /* quirks for ATI SB / AMD Hudson */ | 240 | /* quirks for ATI SB / AMD Hudson */ |
241 | #define AZX_DCAPS_PRESET_ATI_SB \ | 241 | #define AZX_DCAPS_PRESET_ATI_SB \ |
242 | (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \ | 242 | (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \ |
243 | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB) | 243 | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB) |
244 | 244 | ||
245 | /* quirks for ATI/AMD HDMI */ | 245 | /* quirks for ATI/AMD HDMI */ |
246 | #define AZX_DCAPS_PRESET_ATI_HDMI \ | 246 | #define AZX_DCAPS_PRESET_ATI_HDMI \ |
247 | (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB) | 247 | (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB) |
248 | 248 | ||
249 | /* quirks for Nvidia */ | 249 | /* quirks for Nvidia */ |
250 | #define AZX_DCAPS_PRESET_NVIDIA \ | 250 | #define AZX_DCAPS_PRESET_NVIDIA \ |
251 | (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\ | 251 | (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\ |
252 | AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT) | 252 | AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT |\ |
253 | AZX_DCAPS_CORBRP_SELF_CLEAR) | ||
253 | 254 | ||
254 | #define AZX_DCAPS_PRESET_CTHDA \ | 255 | #define AZX_DCAPS_PRESET_CTHDA \ |
255 | (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY) | 256 | (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY) |
256 | 257 | ||
257 | /* | 258 | /* |
258 | * VGA-switcher support | 259 | * VGA-switcher support |
259 | */ | 260 | */ |
260 | #ifdef SUPPORT_VGA_SWITCHEROO | 261 | #ifdef SUPPORT_VGA_SWITCHEROO |
261 | #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) | 262 | #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) |
262 | #else | 263 | #else |
263 | #define use_vga_switcheroo(chip) 0 | 264 | #define use_vga_switcheroo(chip) 0 |
264 | #endif | 265 | #endif |
265 | 266 | ||
266 | static char *driver_short_names[] = { | 267 | static char *driver_short_names[] = { |
267 | [AZX_DRIVER_ICH] = "HDA Intel", | 268 | [AZX_DRIVER_ICH] = "HDA Intel", |
268 | [AZX_DRIVER_PCH] = "HDA Intel PCH", | 269 | [AZX_DRIVER_PCH] = "HDA Intel PCH", |
269 | [AZX_DRIVER_SCH] = "HDA Intel MID", | 270 | [AZX_DRIVER_SCH] = "HDA Intel MID", |
270 | [AZX_DRIVER_HDMI] = "HDA Intel HDMI", | 271 | [AZX_DRIVER_HDMI] = "HDA Intel HDMI", |
271 | [AZX_DRIVER_ATI] = "HDA ATI SB", | 272 | [AZX_DRIVER_ATI] = "HDA ATI SB", |
272 | [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", | 273 | [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", |
273 | [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", | 274 | [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", |
274 | [AZX_DRIVER_VIA] = "HDA VIA VT82xx", | 275 | [AZX_DRIVER_VIA] = "HDA VIA VT82xx", |
275 | [AZX_DRIVER_SIS] = "HDA SIS966", | 276 | [AZX_DRIVER_SIS] = "HDA SIS966", |
276 | [AZX_DRIVER_ULI] = "HDA ULI M5461", | 277 | [AZX_DRIVER_ULI] = "HDA ULI M5461", |
277 | [AZX_DRIVER_NVIDIA] = "HDA NVidia", | 278 | [AZX_DRIVER_NVIDIA] = "HDA NVidia", |
278 | [AZX_DRIVER_TERA] = "HDA Teradici", | 279 | [AZX_DRIVER_TERA] = "HDA Teradici", |
279 | [AZX_DRIVER_CTX] = "HDA Creative", | 280 | [AZX_DRIVER_CTX] = "HDA Creative", |
280 | [AZX_DRIVER_CTHDA] = "HDA Creative", | 281 | [AZX_DRIVER_CTHDA] = "HDA Creative", |
281 | [AZX_DRIVER_GENERIC] = "HD-Audio Generic", | 282 | [AZX_DRIVER_GENERIC] = "HD-Audio Generic", |
282 | }; | 283 | }; |
283 | 284 | ||
284 | #ifdef CONFIG_X86 | 285 | #ifdef CONFIG_X86 |
285 | static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on) | 286 | static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on) |
286 | { | 287 | { |
287 | int pages; | 288 | int pages; |
288 | 289 | ||
289 | if (azx_snoop(chip)) | 290 | if (azx_snoop(chip)) |
290 | return; | 291 | return; |
291 | if (!dmab || !dmab->area || !dmab->bytes) | 292 | if (!dmab || !dmab->area || !dmab->bytes) |
292 | return; | 293 | return; |
293 | 294 | ||
294 | #ifdef CONFIG_SND_DMA_SGBUF | 295 | #ifdef CONFIG_SND_DMA_SGBUF |
295 | if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) { | 296 | if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) { |
296 | struct snd_sg_buf *sgbuf = dmab->private_data; | 297 | struct snd_sg_buf *sgbuf = dmab->private_data; |
297 | if (on) | 298 | if (on) |
298 | set_pages_array_wc(sgbuf->page_table, sgbuf->pages); | 299 | set_pages_array_wc(sgbuf->page_table, sgbuf->pages); |
299 | else | 300 | else |
300 | set_pages_array_wb(sgbuf->page_table, sgbuf->pages); | 301 | set_pages_array_wb(sgbuf->page_table, sgbuf->pages); |
301 | return; | 302 | return; |
302 | } | 303 | } |
303 | #endif | 304 | #endif |
304 | 305 | ||
305 | pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT; | 306 | pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT; |
306 | if (on) | 307 | if (on) |
307 | set_memory_wc((unsigned long)dmab->area, pages); | 308 | set_memory_wc((unsigned long)dmab->area, pages); |
308 | else | 309 | else |
309 | set_memory_wb((unsigned long)dmab->area, pages); | 310 | set_memory_wb((unsigned long)dmab->area, pages); |
310 | } | 311 | } |
311 | 312 | ||
312 | static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, | 313 | static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, |
313 | bool on) | 314 | bool on) |
314 | { | 315 | { |
315 | __mark_pages_wc(chip, buf, on); | 316 | __mark_pages_wc(chip, buf, on); |
316 | } | 317 | } |
317 | static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, | 318 | static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, |
318 | struct snd_pcm_substream *substream, bool on) | 319 | struct snd_pcm_substream *substream, bool on) |
319 | { | 320 | { |
320 | if (azx_dev->wc_marked != on) { | 321 | if (azx_dev->wc_marked != on) { |
321 | __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on); | 322 | __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on); |
322 | azx_dev->wc_marked = on; | 323 | azx_dev->wc_marked = on; |
323 | } | 324 | } |
324 | } | 325 | } |
325 | #else | 326 | #else |
326 | /* NOP for other archs */ | 327 | /* NOP for other archs */ |
327 | static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, | 328 | static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, |
328 | bool on) | 329 | bool on) |
329 | { | 330 | { |
330 | } | 331 | } |
331 | static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, | 332 | static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, |
332 | struct snd_pcm_substream *substream, bool on) | 333 | struct snd_pcm_substream *substream, bool on) |
333 | { | 334 | { |
334 | } | 335 | } |
335 | #endif | 336 | #endif |
336 | 337 | ||
337 | static int azx_acquire_irq(struct azx *chip, int do_disconnect); | 338 | static int azx_acquire_irq(struct azx *chip, int do_disconnect); |
338 | 339 | ||
339 | /* | 340 | /* |
340 | * initialize the PCI registers | 341 | * initialize the PCI registers |
341 | */ | 342 | */ |
342 | /* update bits in a PCI register byte */ | 343 | /* update bits in a PCI register byte */ |
343 | static void update_pci_byte(struct pci_dev *pci, unsigned int reg, | 344 | static void update_pci_byte(struct pci_dev *pci, unsigned int reg, |
344 | unsigned char mask, unsigned char val) | 345 | unsigned char mask, unsigned char val) |
345 | { | 346 | { |
346 | unsigned char data; | 347 | unsigned char data; |
347 | 348 | ||
348 | pci_read_config_byte(pci, reg, &data); | 349 | pci_read_config_byte(pci, reg, &data); |
349 | data &= ~mask; | 350 | data &= ~mask; |
350 | data |= (val & mask); | 351 | data |= (val & mask); |
351 | pci_write_config_byte(pci, reg, data); | 352 | pci_write_config_byte(pci, reg, data); |
352 | } | 353 | } |
353 | 354 | ||
354 | static void azx_init_pci(struct azx *chip) | 355 | static void azx_init_pci(struct azx *chip) |
355 | { | 356 | { |
356 | /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) | 357 | /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) |
357 | * TCSEL == Traffic Class Select Register, which sets PCI express QOS | 358 | * TCSEL == Traffic Class Select Register, which sets PCI express QOS |
358 | * Ensuring these bits are 0 clears playback static on some HD Audio | 359 | * Ensuring these bits are 0 clears playback static on some HD Audio |
359 | * codecs. | 360 | * codecs. |
360 | * The PCI register TCSEL is defined in the Intel manuals. | 361 | * The PCI register TCSEL is defined in the Intel manuals. |
361 | */ | 362 | */ |
362 | if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { | 363 | if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { |
363 | dev_dbg(chip->card->dev, "Clearing TCSEL\n"); | 364 | dev_dbg(chip->card->dev, "Clearing TCSEL\n"); |
364 | update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0); | 365 | update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0); |
365 | } | 366 | } |
366 | 367 | ||
367 | /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, | 368 | /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, |
368 | * we need to enable snoop. | 369 | * we need to enable snoop. |
369 | */ | 370 | */ |
370 | if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) { | 371 | if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) { |
371 | dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", | 372 | dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", |
372 | azx_snoop(chip)); | 373 | azx_snoop(chip)); |
373 | update_pci_byte(chip->pci, | 374 | update_pci_byte(chip->pci, |
374 | ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, | 375 | ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, |
375 | azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); | 376 | azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); |
376 | } | 377 | } |
377 | 378 | ||
378 | /* For NVIDIA HDA, enable snoop */ | 379 | /* For NVIDIA HDA, enable snoop */ |
379 | if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) { | 380 | if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) { |
380 | dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", | 381 | dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", |
381 | azx_snoop(chip)); | 382 | azx_snoop(chip)); |
382 | update_pci_byte(chip->pci, | 383 | update_pci_byte(chip->pci, |
383 | NVIDIA_HDA_TRANSREG_ADDR, | 384 | NVIDIA_HDA_TRANSREG_ADDR, |
384 | 0x0f, NVIDIA_HDA_ENABLE_COHBITS); | 385 | 0x0f, NVIDIA_HDA_ENABLE_COHBITS); |
385 | update_pci_byte(chip->pci, | 386 | update_pci_byte(chip->pci, |
386 | NVIDIA_HDA_ISTRM_COH, | 387 | NVIDIA_HDA_ISTRM_COH, |
387 | 0x01, NVIDIA_HDA_ENABLE_COHBIT); | 388 | 0x01, NVIDIA_HDA_ENABLE_COHBIT); |
388 | update_pci_byte(chip->pci, | 389 | update_pci_byte(chip->pci, |
389 | NVIDIA_HDA_OSTRM_COH, | 390 | NVIDIA_HDA_OSTRM_COH, |
390 | 0x01, NVIDIA_HDA_ENABLE_COHBIT); | 391 | 0x01, NVIDIA_HDA_ENABLE_COHBIT); |
391 | } | 392 | } |
392 | 393 | ||
393 | /* Enable SCH/PCH snoop if needed */ | 394 | /* Enable SCH/PCH snoop if needed */ |
394 | if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) { | 395 | if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) { |
395 | unsigned short snoop; | 396 | unsigned short snoop; |
396 | pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); | 397 | pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); |
397 | if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || | 398 | if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || |
398 | (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { | 399 | (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { |
399 | snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; | 400 | snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; |
400 | if (!azx_snoop(chip)) | 401 | if (!azx_snoop(chip)) |
401 | snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; | 402 | snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; |
402 | pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); | 403 | pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); |
403 | pci_read_config_word(chip->pci, | 404 | pci_read_config_word(chip->pci, |
404 | INTEL_SCH_HDA_DEVC, &snoop); | 405 | INTEL_SCH_HDA_DEVC, &snoop); |
405 | } | 406 | } |
406 | dev_dbg(chip->card->dev, "SCH snoop: %s\n", | 407 | dev_dbg(chip->card->dev, "SCH snoop: %s\n", |
407 | (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? | 408 | (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? |
408 | "Disabled" : "Enabled"); | 409 | "Disabled" : "Enabled"); |
409 | } | 410 | } |
410 | } | 411 | } |
411 | 412 | ||
412 | static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); | 413 | static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); |
413 | 414 | ||
414 | /* called from IRQ */ | 415 | /* called from IRQ */ |
415 | static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) | 416 | static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) |
416 | { | 417 | { |
417 | int ok; | 418 | int ok; |
418 | 419 | ||
419 | ok = azx_position_ok(chip, azx_dev); | 420 | ok = azx_position_ok(chip, azx_dev); |
420 | if (ok == 1) { | 421 | if (ok == 1) { |
421 | azx_dev->irq_pending = 0; | 422 | azx_dev->irq_pending = 0; |
422 | return ok; | 423 | return ok; |
423 | } else if (ok == 0 && chip->bus && chip->bus->workq) { | 424 | } else if (ok == 0 && chip->bus && chip->bus->workq) { |
424 | /* bogus IRQ, process it later */ | 425 | /* bogus IRQ, process it later */ |
425 | azx_dev->irq_pending = 1; | 426 | azx_dev->irq_pending = 1; |
426 | queue_work(chip->bus->workq, &chip->irq_pending_work); | 427 | queue_work(chip->bus->workq, &chip->irq_pending_work); |
427 | } | 428 | } |
428 | return 0; | 429 | return 0; |
429 | } | 430 | } |
430 | 431 | ||
431 | /* | 432 | /* |
432 | * Check whether the current DMA position is acceptable for updating | 433 | * Check whether the current DMA position is acceptable for updating |
433 | * periods. Returns non-zero if it's OK. | 434 | * periods. Returns non-zero if it's OK. |
434 | * | 435 | * |
435 | * Many HD-audio controllers appear pretty inaccurate about | 436 | * Many HD-audio controllers appear pretty inaccurate about |
436 | * the update-IRQ timing. The IRQ is issued before actually the | 437 | * the update-IRQ timing. The IRQ is issued before actually the |
437 | * data is processed. So, we need to process it afterwords in a | 438 | * data is processed. So, we need to process it afterwords in a |
438 | * workqueue. | 439 | * workqueue. |
439 | */ | 440 | */ |
440 | static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) | 441 | static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) |
441 | { | 442 | { |
442 | u32 wallclk; | 443 | u32 wallclk; |
443 | unsigned int pos; | 444 | unsigned int pos; |
444 | 445 | ||
445 | wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk; | 446 | wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk; |
446 | if (wallclk < (azx_dev->period_wallclk * 2) / 3) | 447 | if (wallclk < (azx_dev->period_wallclk * 2) / 3) |
447 | return -1; /* bogus (too early) interrupt */ | 448 | return -1; /* bogus (too early) interrupt */ |
448 | 449 | ||
449 | pos = azx_get_position(chip, azx_dev, true); | 450 | pos = azx_get_position(chip, azx_dev, true); |
450 | 451 | ||
451 | if (WARN_ONCE(!azx_dev->period_bytes, | 452 | if (WARN_ONCE(!azx_dev->period_bytes, |
452 | "hda-intel: zero azx_dev->period_bytes")) | 453 | "hda-intel: zero azx_dev->period_bytes")) |
453 | return -1; /* this shouldn't happen! */ | 454 | return -1; /* this shouldn't happen! */ |
454 | if (wallclk < (azx_dev->period_wallclk * 5) / 4 && | 455 | if (wallclk < (azx_dev->period_wallclk * 5) / 4 && |
455 | pos % azx_dev->period_bytes > azx_dev->period_bytes / 2) | 456 | pos % azx_dev->period_bytes > azx_dev->period_bytes / 2) |
456 | /* NG - it's below the first next period boundary */ | 457 | /* NG - it's below the first next period boundary */ |
457 | return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1; | 458 | return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1; |
458 | azx_dev->start_wallclk += wallclk; | 459 | azx_dev->start_wallclk += wallclk; |
459 | return 1; /* OK, it's fine */ | 460 | return 1; /* OK, it's fine */ |
460 | } | 461 | } |
461 | 462 | ||
462 | /* | 463 | /* |
463 | * The work for pending PCM period updates. | 464 | * The work for pending PCM period updates. |
464 | */ | 465 | */ |
465 | static void azx_irq_pending_work(struct work_struct *work) | 466 | static void azx_irq_pending_work(struct work_struct *work) |
466 | { | 467 | { |
467 | struct azx *chip = container_of(work, struct azx, irq_pending_work); | 468 | struct azx *chip = container_of(work, struct azx, irq_pending_work); |
468 | int i, pending, ok; | 469 | int i, pending, ok; |
469 | 470 | ||
470 | if (!chip->irq_pending_warned) { | 471 | if (!chip->irq_pending_warned) { |
471 | dev_info(chip->card->dev, | 472 | dev_info(chip->card->dev, |
472 | "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", | 473 | "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", |
473 | chip->card->number); | 474 | chip->card->number); |
474 | chip->irq_pending_warned = 1; | 475 | chip->irq_pending_warned = 1; |
475 | } | 476 | } |
476 | 477 | ||
477 | for (;;) { | 478 | for (;;) { |
478 | pending = 0; | 479 | pending = 0; |
479 | spin_lock_irq(&chip->reg_lock); | 480 | spin_lock_irq(&chip->reg_lock); |
480 | for (i = 0; i < chip->num_streams; i++) { | 481 | for (i = 0; i < chip->num_streams; i++) { |
481 | struct azx_dev *azx_dev = &chip->azx_dev[i]; | 482 | struct azx_dev *azx_dev = &chip->azx_dev[i]; |
482 | if (!azx_dev->irq_pending || | 483 | if (!azx_dev->irq_pending || |
483 | !azx_dev->substream || | 484 | !azx_dev->substream || |
484 | !azx_dev->running) | 485 | !azx_dev->running) |
485 | continue; | 486 | continue; |
486 | ok = azx_position_ok(chip, azx_dev); | 487 | ok = azx_position_ok(chip, azx_dev); |
487 | if (ok > 0) { | 488 | if (ok > 0) { |
488 | azx_dev->irq_pending = 0; | 489 | azx_dev->irq_pending = 0; |
489 | spin_unlock(&chip->reg_lock); | 490 | spin_unlock(&chip->reg_lock); |
490 | snd_pcm_period_elapsed(azx_dev->substream); | 491 | snd_pcm_period_elapsed(azx_dev->substream); |
491 | spin_lock(&chip->reg_lock); | 492 | spin_lock(&chip->reg_lock); |
492 | } else if (ok < 0) { | 493 | } else if (ok < 0) { |
493 | pending = 0; /* too early */ | 494 | pending = 0; /* too early */ |
494 | } else | 495 | } else |
495 | pending++; | 496 | pending++; |
496 | } | 497 | } |
497 | spin_unlock_irq(&chip->reg_lock); | 498 | spin_unlock_irq(&chip->reg_lock); |
498 | if (!pending) | 499 | if (!pending) |
499 | return; | 500 | return; |
500 | msleep(1); | 501 | msleep(1); |
501 | } | 502 | } |
502 | } | 503 | } |
503 | 504 | ||
504 | /* clear irq_pending flags and assure no on-going workq */ | 505 | /* clear irq_pending flags and assure no on-going workq */ |
505 | static void azx_clear_irq_pending(struct azx *chip) | 506 | static void azx_clear_irq_pending(struct azx *chip) |
506 | { | 507 | { |
507 | int i; | 508 | int i; |
508 | 509 | ||
509 | spin_lock_irq(&chip->reg_lock); | 510 | spin_lock_irq(&chip->reg_lock); |
510 | for (i = 0; i < chip->num_streams; i++) | 511 | for (i = 0; i < chip->num_streams; i++) |
511 | chip->azx_dev[i].irq_pending = 0; | 512 | chip->azx_dev[i].irq_pending = 0; |
512 | spin_unlock_irq(&chip->reg_lock); | 513 | spin_unlock_irq(&chip->reg_lock); |
513 | } | 514 | } |
514 | 515 | ||
515 | static int azx_acquire_irq(struct azx *chip, int do_disconnect) | 516 | static int azx_acquire_irq(struct azx *chip, int do_disconnect) |
516 | { | 517 | { |
517 | if (request_irq(chip->pci->irq, azx_interrupt, | 518 | if (request_irq(chip->pci->irq, azx_interrupt, |
518 | chip->msi ? 0 : IRQF_SHARED, | 519 | chip->msi ? 0 : IRQF_SHARED, |
519 | KBUILD_MODNAME, chip)) { | 520 | KBUILD_MODNAME, chip)) { |
520 | dev_err(chip->card->dev, | 521 | dev_err(chip->card->dev, |
521 | "unable to grab IRQ %d, disabling device\n", | 522 | "unable to grab IRQ %d, disabling device\n", |
522 | chip->pci->irq); | 523 | chip->pci->irq); |
523 | if (do_disconnect) | 524 | if (do_disconnect) |
524 | snd_card_disconnect(chip->card); | 525 | snd_card_disconnect(chip->card); |
525 | return -1; | 526 | return -1; |
526 | } | 527 | } |
527 | chip->irq = chip->pci->irq; | 528 | chip->irq = chip->pci->irq; |
528 | pci_intx(chip->pci, !chip->msi); | 529 | pci_intx(chip->pci, !chip->msi); |
529 | return 0; | 530 | return 0; |
530 | } | 531 | } |
531 | 532 | ||
532 | #ifdef CONFIG_PM | 533 | #ifdef CONFIG_PM |
533 | static DEFINE_MUTEX(card_list_lock); | 534 | static DEFINE_MUTEX(card_list_lock); |
534 | static LIST_HEAD(card_list); | 535 | static LIST_HEAD(card_list); |
535 | 536 | ||
536 | static void azx_add_card_list(struct azx *chip) | 537 | static void azx_add_card_list(struct azx *chip) |
537 | { | 538 | { |
538 | mutex_lock(&card_list_lock); | 539 | mutex_lock(&card_list_lock); |
539 | list_add(&chip->list, &card_list); | 540 | list_add(&chip->list, &card_list); |
540 | mutex_unlock(&card_list_lock); | 541 | mutex_unlock(&card_list_lock); |
541 | } | 542 | } |
542 | 543 | ||
543 | static void azx_del_card_list(struct azx *chip) | 544 | static void azx_del_card_list(struct azx *chip) |
544 | { | 545 | { |
545 | mutex_lock(&card_list_lock); | 546 | mutex_lock(&card_list_lock); |
546 | list_del_init(&chip->list); | 547 | list_del_init(&chip->list); |
547 | mutex_unlock(&card_list_lock); | 548 | mutex_unlock(&card_list_lock); |
548 | } | 549 | } |
549 | 550 | ||
550 | /* trigger power-save check at writing parameter */ | 551 | /* trigger power-save check at writing parameter */ |
551 | static int param_set_xint(const char *val, const struct kernel_param *kp) | 552 | static int param_set_xint(const char *val, const struct kernel_param *kp) |
552 | { | 553 | { |
553 | struct azx *chip; | 554 | struct azx *chip; |
554 | struct hda_codec *c; | 555 | struct hda_codec *c; |
555 | int prev = power_save; | 556 | int prev = power_save; |
556 | int ret = param_set_int(val, kp); | 557 | int ret = param_set_int(val, kp); |
557 | 558 | ||
558 | if (ret || prev == power_save) | 559 | if (ret || prev == power_save) |
559 | return ret; | 560 | return ret; |
560 | 561 | ||
561 | mutex_lock(&card_list_lock); | 562 | mutex_lock(&card_list_lock); |
562 | list_for_each_entry(chip, &card_list, list) { | 563 | list_for_each_entry(chip, &card_list, list) { |
563 | if (!chip->bus || chip->disabled) | 564 | if (!chip->bus || chip->disabled) |
564 | continue; | 565 | continue; |
565 | list_for_each_entry(c, &chip->bus->codec_list, list) | 566 | list_for_each_entry(c, &chip->bus->codec_list, list) |
566 | snd_hda_power_sync(c); | 567 | snd_hda_power_sync(c); |
567 | } | 568 | } |
568 | mutex_unlock(&card_list_lock); | 569 | mutex_unlock(&card_list_lock); |
569 | return 0; | 570 | return 0; |
570 | } | 571 | } |
571 | #else | 572 | #else |
572 | #define azx_add_card_list(chip) /* NOP */ | 573 | #define azx_add_card_list(chip) /* NOP */ |
573 | #define azx_del_card_list(chip) /* NOP */ | 574 | #define azx_del_card_list(chip) /* NOP */ |
574 | #endif /* CONFIG_PM */ | 575 | #endif /* CONFIG_PM */ |
575 | 576 | ||
576 | #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO) | 577 | #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO) |
577 | /* | 578 | /* |
578 | * power management | 579 | * power management |
579 | */ | 580 | */ |
580 | static int azx_suspend(struct device *dev) | 581 | static int azx_suspend(struct device *dev) |
581 | { | 582 | { |
582 | struct pci_dev *pci = to_pci_dev(dev); | 583 | struct pci_dev *pci = to_pci_dev(dev); |
583 | struct snd_card *card = dev_get_drvdata(dev); | 584 | struct snd_card *card = dev_get_drvdata(dev); |
584 | struct azx *chip = card->private_data; | 585 | struct azx *chip = card->private_data; |
585 | struct azx_pcm *p; | 586 | struct azx_pcm *p; |
586 | 587 | ||
587 | if (chip->disabled) | 588 | if (chip->disabled) |
588 | return 0; | 589 | return 0; |
589 | 590 | ||
590 | snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); | 591 | snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); |
591 | azx_clear_irq_pending(chip); | 592 | azx_clear_irq_pending(chip); |
592 | list_for_each_entry(p, &chip->pcm_list, list) | 593 | list_for_each_entry(p, &chip->pcm_list, list) |
593 | snd_pcm_suspend_all(p->pcm); | 594 | snd_pcm_suspend_all(p->pcm); |
594 | if (chip->initialized) | 595 | if (chip->initialized) |
595 | snd_hda_suspend(chip->bus); | 596 | snd_hda_suspend(chip->bus); |
596 | azx_stop_chip(chip); | 597 | azx_stop_chip(chip); |
597 | azx_enter_link_reset(chip); | 598 | azx_enter_link_reset(chip); |
598 | if (chip->irq >= 0) { | 599 | if (chip->irq >= 0) { |
599 | free_irq(chip->irq, chip); | 600 | free_irq(chip->irq, chip); |
600 | chip->irq = -1; | 601 | chip->irq = -1; |
601 | } | 602 | } |
602 | if (chip->msi) | 603 | if (chip->msi) |
603 | pci_disable_msi(chip->pci); | 604 | pci_disable_msi(chip->pci); |
604 | pci_disable_device(pci); | 605 | pci_disable_device(pci); |
605 | pci_save_state(pci); | 606 | pci_save_state(pci); |
606 | pci_set_power_state(pci, PCI_D3hot); | 607 | pci_set_power_state(pci, PCI_D3hot); |
607 | if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) | 608 | if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) |
608 | hda_display_power(false); | 609 | hda_display_power(false); |
609 | return 0; | 610 | return 0; |
610 | } | 611 | } |
611 | 612 | ||
612 | static int azx_resume(struct device *dev) | 613 | static int azx_resume(struct device *dev) |
613 | { | 614 | { |
614 | struct pci_dev *pci = to_pci_dev(dev); | 615 | struct pci_dev *pci = to_pci_dev(dev); |
615 | struct snd_card *card = dev_get_drvdata(dev); | 616 | struct snd_card *card = dev_get_drvdata(dev); |
616 | struct azx *chip = card->private_data; | 617 | struct azx *chip = card->private_data; |
617 | 618 | ||
618 | if (chip->disabled) | 619 | if (chip->disabled) |
619 | return 0; | 620 | return 0; |
620 | 621 | ||
621 | if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) | 622 | if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) |
622 | hda_display_power(true); | 623 | hda_display_power(true); |
623 | pci_set_power_state(pci, PCI_D0); | 624 | pci_set_power_state(pci, PCI_D0); |
624 | pci_restore_state(pci); | 625 | pci_restore_state(pci); |
625 | if (pci_enable_device(pci) < 0) { | 626 | if (pci_enable_device(pci) < 0) { |
626 | dev_err(chip->card->dev, | 627 | dev_err(chip->card->dev, |
627 | "pci_enable_device failed, disabling device\n"); | 628 | "pci_enable_device failed, disabling device\n"); |
628 | snd_card_disconnect(card); | 629 | snd_card_disconnect(card); |
629 | return -EIO; | 630 | return -EIO; |
630 | } | 631 | } |
631 | pci_set_master(pci); | 632 | pci_set_master(pci); |
632 | if (chip->msi) | 633 | if (chip->msi) |
633 | if (pci_enable_msi(pci) < 0) | 634 | if (pci_enable_msi(pci) < 0) |
634 | chip->msi = 0; | 635 | chip->msi = 0; |
635 | if (azx_acquire_irq(chip, 1) < 0) | 636 | if (azx_acquire_irq(chip, 1) < 0) |
636 | return -EIO; | 637 | return -EIO; |
637 | azx_init_pci(chip); | 638 | azx_init_pci(chip); |
638 | 639 | ||
639 | azx_init_chip(chip, true); | 640 | azx_init_chip(chip, true); |
640 | 641 | ||
641 | snd_hda_resume(chip->bus); | 642 | snd_hda_resume(chip->bus); |
642 | snd_power_change_state(card, SNDRV_CTL_POWER_D0); | 643 | snd_power_change_state(card, SNDRV_CTL_POWER_D0); |
643 | return 0; | 644 | return 0; |
644 | } | 645 | } |
645 | #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */ | 646 | #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */ |
646 | 647 | ||
647 | #ifdef CONFIG_PM_RUNTIME | 648 | #ifdef CONFIG_PM_RUNTIME |
648 | static int azx_runtime_suspend(struct device *dev) | 649 | static int azx_runtime_suspend(struct device *dev) |
649 | { | 650 | { |
650 | struct snd_card *card = dev_get_drvdata(dev); | 651 | struct snd_card *card = dev_get_drvdata(dev); |
651 | struct azx *chip = card->private_data; | 652 | struct azx *chip = card->private_data; |
652 | 653 | ||
653 | if (chip->disabled) | 654 | if (chip->disabled) |
654 | return 0; | 655 | return 0; |
655 | 656 | ||
656 | if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME)) | 657 | if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME)) |
657 | return 0; | 658 | return 0; |
658 | 659 | ||
659 | /* enable controller wake up event */ | 660 | /* enable controller wake up event */ |
660 | azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | | 661 | azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | |
661 | STATESTS_INT_MASK); | 662 | STATESTS_INT_MASK); |
662 | 663 | ||
663 | azx_stop_chip(chip); | 664 | azx_stop_chip(chip); |
664 | azx_enter_link_reset(chip); | 665 | azx_enter_link_reset(chip); |
665 | azx_clear_irq_pending(chip); | 666 | azx_clear_irq_pending(chip); |
666 | if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) | 667 | if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) |
667 | hda_display_power(false); | 668 | hda_display_power(false); |
668 | return 0; | 669 | return 0; |
669 | } | 670 | } |
670 | 671 | ||
671 | static int azx_runtime_resume(struct device *dev) | 672 | static int azx_runtime_resume(struct device *dev) |
672 | { | 673 | { |
673 | struct snd_card *card = dev_get_drvdata(dev); | 674 | struct snd_card *card = dev_get_drvdata(dev); |
674 | struct azx *chip = card->private_data; | 675 | struct azx *chip = card->private_data; |
675 | struct hda_bus *bus; | 676 | struct hda_bus *bus; |
676 | struct hda_codec *codec; | 677 | struct hda_codec *codec; |
677 | int status; | 678 | int status; |
678 | 679 | ||
679 | if (chip->disabled) | 680 | if (chip->disabled) |
680 | return 0; | 681 | return 0; |
681 | 682 | ||
682 | if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME)) | 683 | if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME)) |
683 | return 0; | 684 | return 0; |
684 | 685 | ||
685 | if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) | 686 | if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) |
686 | hda_display_power(true); | 687 | hda_display_power(true); |
687 | 688 | ||
688 | /* Read STATESTS before controller reset */ | 689 | /* Read STATESTS before controller reset */ |
689 | status = azx_readw(chip, STATESTS); | 690 | status = azx_readw(chip, STATESTS); |
690 | 691 | ||
691 | azx_init_pci(chip); | 692 | azx_init_pci(chip); |
692 | azx_init_chip(chip, true); | 693 | azx_init_chip(chip, true); |
693 | 694 | ||
694 | bus = chip->bus; | 695 | bus = chip->bus; |
695 | if (status && bus) { | 696 | if (status && bus) { |
696 | list_for_each_entry(codec, &bus->codec_list, list) | 697 | list_for_each_entry(codec, &bus->codec_list, list) |
697 | if (status & (1 << codec->addr)) | 698 | if (status & (1 << codec->addr)) |
698 | queue_delayed_work(codec->bus->workq, | 699 | queue_delayed_work(codec->bus->workq, |
699 | &codec->jackpoll_work, codec->jackpoll_interval); | 700 | &codec->jackpoll_work, codec->jackpoll_interval); |
700 | } | 701 | } |
701 | 702 | ||
702 | /* disable controller Wake Up event*/ | 703 | /* disable controller Wake Up event*/ |
703 | azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & | 704 | azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & |
704 | ~STATESTS_INT_MASK); | 705 | ~STATESTS_INT_MASK); |
705 | 706 | ||
706 | return 0; | 707 | return 0; |
707 | } | 708 | } |
708 | 709 | ||
709 | static int azx_runtime_idle(struct device *dev) | 710 | static int azx_runtime_idle(struct device *dev) |
710 | { | 711 | { |
711 | struct snd_card *card = dev_get_drvdata(dev); | 712 | struct snd_card *card = dev_get_drvdata(dev); |
712 | struct azx *chip = card->private_data; | 713 | struct azx *chip = card->private_data; |
713 | 714 | ||
714 | if (chip->disabled) | 715 | if (chip->disabled) |
715 | return 0; | 716 | return 0; |
716 | 717 | ||
717 | if (!power_save_controller || | 718 | if (!power_save_controller || |
718 | !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME)) | 719 | !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME)) |
719 | return -EBUSY; | 720 | return -EBUSY; |
720 | 721 | ||
721 | return 0; | 722 | return 0; |
722 | } | 723 | } |
723 | 724 | ||
724 | #endif /* CONFIG_PM_RUNTIME */ | 725 | #endif /* CONFIG_PM_RUNTIME */ |
725 | 726 | ||
726 | #ifdef CONFIG_PM | 727 | #ifdef CONFIG_PM |
727 | static const struct dev_pm_ops azx_pm = { | 728 | static const struct dev_pm_ops azx_pm = { |
728 | SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) | 729 | SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) |
729 | SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) | 730 | SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) |
730 | }; | 731 | }; |
731 | 732 | ||
732 | #define AZX_PM_OPS &azx_pm | 733 | #define AZX_PM_OPS &azx_pm |
733 | #else | 734 | #else |
734 | #define AZX_PM_OPS NULL | 735 | #define AZX_PM_OPS NULL |
735 | #endif /* CONFIG_PM */ | 736 | #endif /* CONFIG_PM */ |
736 | 737 | ||
737 | 738 | ||
738 | /* | 739 | /* |
739 | * reboot notifier for hang-up problem at power-down | 740 | * reboot notifier for hang-up problem at power-down |
740 | */ | 741 | */ |
741 | static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf) | 742 | static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf) |
742 | { | 743 | { |
743 | struct azx *chip = container_of(nb, struct azx, reboot_notifier); | 744 | struct azx *chip = container_of(nb, struct azx, reboot_notifier); |
744 | snd_hda_bus_reboot_notify(chip->bus); | 745 | snd_hda_bus_reboot_notify(chip->bus); |
745 | azx_stop_chip(chip); | 746 | azx_stop_chip(chip); |
746 | return NOTIFY_OK; | 747 | return NOTIFY_OK; |
747 | } | 748 | } |
748 | 749 | ||
749 | static void azx_notifier_register(struct azx *chip) | 750 | static void azx_notifier_register(struct azx *chip) |
750 | { | 751 | { |
751 | chip->reboot_notifier.notifier_call = azx_halt; | 752 | chip->reboot_notifier.notifier_call = azx_halt; |
752 | register_reboot_notifier(&chip->reboot_notifier); | 753 | register_reboot_notifier(&chip->reboot_notifier); |
753 | } | 754 | } |
754 | 755 | ||
755 | static void azx_notifier_unregister(struct azx *chip) | 756 | static void azx_notifier_unregister(struct azx *chip) |
756 | { | 757 | { |
757 | if (chip->reboot_notifier.notifier_call) | 758 | if (chip->reboot_notifier.notifier_call) |
758 | unregister_reboot_notifier(&chip->reboot_notifier); | 759 | unregister_reboot_notifier(&chip->reboot_notifier); |
759 | } | 760 | } |
760 | 761 | ||
761 | static int azx_probe_continue(struct azx *chip); | 762 | static int azx_probe_continue(struct azx *chip); |
762 | 763 | ||
763 | #ifdef SUPPORT_VGA_SWITCHEROO | 764 | #ifdef SUPPORT_VGA_SWITCHEROO |
764 | static struct pci_dev *get_bound_vga(struct pci_dev *pci); | 765 | static struct pci_dev *get_bound_vga(struct pci_dev *pci); |
765 | 766 | ||
766 | static void azx_vs_set_state(struct pci_dev *pci, | 767 | static void azx_vs_set_state(struct pci_dev *pci, |
767 | enum vga_switcheroo_state state) | 768 | enum vga_switcheroo_state state) |
768 | { | 769 | { |
769 | struct snd_card *card = pci_get_drvdata(pci); | 770 | struct snd_card *card = pci_get_drvdata(pci); |
770 | struct azx *chip = card->private_data; | 771 | struct azx *chip = card->private_data; |
771 | bool disabled; | 772 | bool disabled; |
772 | 773 | ||
773 | wait_for_completion(&chip->probe_wait); | 774 | wait_for_completion(&chip->probe_wait); |
774 | if (chip->init_failed) | 775 | if (chip->init_failed) |
775 | return; | 776 | return; |
776 | 777 | ||
777 | disabled = (state == VGA_SWITCHEROO_OFF); | 778 | disabled = (state == VGA_SWITCHEROO_OFF); |
778 | if (chip->disabled == disabled) | 779 | if (chip->disabled == disabled) |
779 | return; | 780 | return; |
780 | 781 | ||
781 | if (!chip->bus) { | 782 | if (!chip->bus) { |
782 | chip->disabled = disabled; | 783 | chip->disabled = disabled; |
783 | if (!disabled) { | 784 | if (!disabled) { |
784 | dev_info(chip->card->dev, | 785 | dev_info(chip->card->dev, |
785 | "Start delayed initialization\n"); | 786 | "Start delayed initialization\n"); |
786 | if (azx_probe_continue(chip) < 0) { | 787 | if (azx_probe_continue(chip) < 0) { |
787 | dev_err(chip->card->dev, "initialization error\n"); | 788 | dev_err(chip->card->dev, "initialization error\n"); |
788 | chip->init_failed = true; | 789 | chip->init_failed = true; |
789 | } | 790 | } |
790 | } | 791 | } |
791 | } else { | 792 | } else { |
792 | dev_info(chip->card->dev, "%s via VGA-switcheroo\n", | 793 | dev_info(chip->card->dev, "%s via VGA-switcheroo\n", |
793 | disabled ? "Disabling" : "Enabling"); | 794 | disabled ? "Disabling" : "Enabling"); |
794 | if (disabled) { | 795 | if (disabled) { |
795 | pm_runtime_put_sync_suspend(card->dev); | 796 | pm_runtime_put_sync_suspend(card->dev); |
796 | azx_suspend(card->dev); | 797 | azx_suspend(card->dev); |
797 | /* when we get suspended by vga switcheroo we end up in D3cold, | 798 | /* when we get suspended by vga switcheroo we end up in D3cold, |
798 | * however we have no ACPI handle, so pci/acpi can't put us there, | 799 | * however we have no ACPI handle, so pci/acpi can't put us there, |
799 | * put ourselves there */ | 800 | * put ourselves there */ |
800 | pci->current_state = PCI_D3cold; | 801 | pci->current_state = PCI_D3cold; |
801 | chip->disabled = true; | 802 | chip->disabled = true; |
802 | if (snd_hda_lock_devices(chip->bus)) | 803 | if (snd_hda_lock_devices(chip->bus)) |
803 | dev_warn(chip->card->dev, | 804 | dev_warn(chip->card->dev, |
804 | "Cannot lock devices!\n"); | 805 | "Cannot lock devices!\n"); |
805 | } else { | 806 | } else { |
806 | snd_hda_unlock_devices(chip->bus); | 807 | snd_hda_unlock_devices(chip->bus); |
807 | pm_runtime_get_noresume(card->dev); | 808 | pm_runtime_get_noresume(card->dev); |
808 | chip->disabled = false; | 809 | chip->disabled = false; |
809 | azx_resume(card->dev); | 810 | azx_resume(card->dev); |
810 | } | 811 | } |
811 | } | 812 | } |
812 | } | 813 | } |
813 | 814 | ||
814 | static bool azx_vs_can_switch(struct pci_dev *pci) | 815 | static bool azx_vs_can_switch(struct pci_dev *pci) |
815 | { | 816 | { |
816 | struct snd_card *card = pci_get_drvdata(pci); | 817 | struct snd_card *card = pci_get_drvdata(pci); |
817 | struct azx *chip = card->private_data; | 818 | struct azx *chip = card->private_data; |
818 | 819 | ||
819 | wait_for_completion(&chip->probe_wait); | 820 | wait_for_completion(&chip->probe_wait); |
820 | if (chip->init_failed) | 821 | if (chip->init_failed) |
821 | return false; | 822 | return false; |
822 | if (chip->disabled || !chip->bus) | 823 | if (chip->disabled || !chip->bus) |
823 | return true; | 824 | return true; |
824 | if (snd_hda_lock_devices(chip->bus)) | 825 | if (snd_hda_lock_devices(chip->bus)) |
825 | return false; | 826 | return false; |
826 | snd_hda_unlock_devices(chip->bus); | 827 | snd_hda_unlock_devices(chip->bus); |
827 | return true; | 828 | return true; |
828 | } | 829 | } |
829 | 830 | ||
830 | static void init_vga_switcheroo(struct azx *chip) | 831 | static void init_vga_switcheroo(struct azx *chip) |
831 | { | 832 | { |
832 | struct pci_dev *p = get_bound_vga(chip->pci); | 833 | struct pci_dev *p = get_bound_vga(chip->pci); |
833 | if (p) { | 834 | if (p) { |
834 | dev_info(chip->card->dev, | 835 | dev_info(chip->card->dev, |
835 | "Handle VGA-switcheroo audio client\n"); | 836 | "Handle VGA-switcheroo audio client\n"); |
836 | chip->use_vga_switcheroo = 1; | 837 | chip->use_vga_switcheroo = 1; |
837 | pci_dev_put(p); | 838 | pci_dev_put(p); |
838 | } | 839 | } |
839 | } | 840 | } |
840 | 841 | ||
841 | static const struct vga_switcheroo_client_ops azx_vs_ops = { | 842 | static const struct vga_switcheroo_client_ops azx_vs_ops = { |
842 | .set_gpu_state = azx_vs_set_state, | 843 | .set_gpu_state = azx_vs_set_state, |
843 | .can_switch = azx_vs_can_switch, | 844 | .can_switch = azx_vs_can_switch, |
844 | }; | 845 | }; |
845 | 846 | ||
846 | static int register_vga_switcheroo(struct azx *chip) | 847 | static int register_vga_switcheroo(struct azx *chip) |
847 | { | 848 | { |
848 | int err; | 849 | int err; |
849 | 850 | ||
850 | if (!chip->use_vga_switcheroo) | 851 | if (!chip->use_vga_switcheroo) |
851 | return 0; | 852 | return 0; |
852 | /* FIXME: currently only handling DIS controller | 853 | /* FIXME: currently only handling DIS controller |
853 | * is there any machine with two switchable HDMI audio controllers? | 854 | * is there any machine with two switchable HDMI audio controllers? |
854 | */ | 855 | */ |
855 | err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, | 856 | err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, |
856 | VGA_SWITCHEROO_DIS, | 857 | VGA_SWITCHEROO_DIS, |
857 | chip->bus != NULL); | 858 | chip->bus != NULL); |
858 | if (err < 0) | 859 | if (err < 0) |
859 | return err; | 860 | return err; |
860 | chip->vga_switcheroo_registered = 1; | 861 | chip->vga_switcheroo_registered = 1; |
861 | 862 | ||
862 | /* register as an optimus hdmi audio power domain */ | 863 | /* register as an optimus hdmi audio power domain */ |
863 | vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev, | 864 | vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev, |
864 | &chip->hdmi_pm_domain); | 865 | &chip->hdmi_pm_domain); |
865 | return 0; | 866 | return 0; |
866 | } | 867 | } |
867 | #else | 868 | #else |
868 | #define init_vga_switcheroo(chip) /* NOP */ | 869 | #define init_vga_switcheroo(chip) /* NOP */ |
869 | #define register_vga_switcheroo(chip) 0 | 870 | #define register_vga_switcheroo(chip) 0 |
870 | #define check_hdmi_disabled(pci) false | 871 | #define check_hdmi_disabled(pci) false |
871 | #endif /* SUPPORT_VGA_SWITCHER */ | 872 | #endif /* SUPPORT_VGA_SWITCHER */ |
872 | 873 | ||
873 | /* | 874 | /* |
874 | * destructor | 875 | * destructor |
875 | */ | 876 | */ |
876 | static int azx_free(struct azx *chip) | 877 | static int azx_free(struct azx *chip) |
877 | { | 878 | { |
878 | struct pci_dev *pci = chip->pci; | 879 | struct pci_dev *pci = chip->pci; |
879 | int i; | 880 | int i; |
880 | 881 | ||
881 | if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) | 882 | if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) |
882 | && chip->running) | 883 | && chip->running) |
883 | pm_runtime_get_noresume(&pci->dev); | 884 | pm_runtime_get_noresume(&pci->dev); |
884 | 885 | ||
885 | azx_del_card_list(chip); | 886 | azx_del_card_list(chip); |
886 | 887 | ||
887 | azx_notifier_unregister(chip); | 888 | azx_notifier_unregister(chip); |
888 | 889 | ||
889 | chip->init_failed = 1; /* to be sure */ | 890 | chip->init_failed = 1; /* to be sure */ |
890 | complete_all(&chip->probe_wait); | 891 | complete_all(&chip->probe_wait); |
891 | 892 | ||
892 | if (use_vga_switcheroo(chip)) { | 893 | if (use_vga_switcheroo(chip)) { |
893 | if (chip->disabled && chip->bus) | 894 | if (chip->disabled && chip->bus) |
894 | snd_hda_unlock_devices(chip->bus); | 895 | snd_hda_unlock_devices(chip->bus); |
895 | if (chip->vga_switcheroo_registered) | 896 | if (chip->vga_switcheroo_registered) |
896 | vga_switcheroo_unregister_client(chip->pci); | 897 | vga_switcheroo_unregister_client(chip->pci); |
897 | } | 898 | } |
898 | 899 | ||
899 | if (chip->initialized) { | 900 | if (chip->initialized) { |
900 | azx_clear_irq_pending(chip); | 901 | azx_clear_irq_pending(chip); |
901 | for (i = 0; i < chip->num_streams; i++) | 902 | for (i = 0; i < chip->num_streams; i++) |
902 | azx_stream_stop(chip, &chip->azx_dev[i]); | 903 | azx_stream_stop(chip, &chip->azx_dev[i]); |
903 | azx_stop_chip(chip); | 904 | azx_stop_chip(chip); |
904 | } | 905 | } |
905 | 906 | ||
906 | if (chip->irq >= 0) | 907 | if (chip->irq >= 0) |
907 | free_irq(chip->irq, (void*)chip); | 908 | free_irq(chip->irq, (void*)chip); |
908 | if (chip->msi) | 909 | if (chip->msi) |
909 | pci_disable_msi(chip->pci); | 910 | pci_disable_msi(chip->pci); |
910 | if (chip->remap_addr) | 911 | if (chip->remap_addr) |
911 | iounmap(chip->remap_addr); | 912 | iounmap(chip->remap_addr); |
912 | 913 | ||
913 | azx_free_stream_pages(chip); | 914 | azx_free_stream_pages(chip); |
914 | if (chip->region_requested) | 915 | if (chip->region_requested) |
915 | pci_release_regions(chip->pci); | 916 | pci_release_regions(chip->pci); |
916 | pci_disable_device(chip->pci); | 917 | pci_disable_device(chip->pci); |
917 | kfree(chip->azx_dev); | 918 | kfree(chip->azx_dev); |
918 | #ifdef CONFIG_SND_HDA_PATCH_LOADER | 919 | #ifdef CONFIG_SND_HDA_PATCH_LOADER |
919 | if (chip->fw) | 920 | if (chip->fw) |
920 | release_firmware(chip->fw); | 921 | release_firmware(chip->fw); |
921 | #endif | 922 | #endif |
922 | if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { | 923 | if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { |
923 | hda_display_power(false); | 924 | hda_display_power(false); |
924 | hda_i915_exit(); | 925 | hda_i915_exit(); |
925 | } | 926 | } |
926 | kfree(chip); | 927 | kfree(chip); |
927 | 928 | ||
928 | return 0; | 929 | return 0; |
929 | } | 930 | } |
930 | 931 | ||
931 | static int azx_dev_free(struct snd_device *device) | 932 | static int azx_dev_free(struct snd_device *device) |
932 | { | 933 | { |
933 | return azx_free(device->device_data); | 934 | return azx_free(device->device_data); |
934 | } | 935 | } |
935 | 936 | ||
936 | #ifdef SUPPORT_VGA_SWITCHEROO | 937 | #ifdef SUPPORT_VGA_SWITCHEROO |
937 | /* | 938 | /* |
938 | * Check of disabled HDMI controller by vga-switcheroo | 939 | * Check of disabled HDMI controller by vga-switcheroo |
939 | */ | 940 | */ |
940 | static struct pci_dev *get_bound_vga(struct pci_dev *pci) | 941 | static struct pci_dev *get_bound_vga(struct pci_dev *pci) |
941 | { | 942 | { |
942 | struct pci_dev *p; | 943 | struct pci_dev *p; |
943 | 944 | ||
944 | /* check only discrete GPU */ | 945 | /* check only discrete GPU */ |
945 | switch (pci->vendor) { | 946 | switch (pci->vendor) { |
946 | case PCI_VENDOR_ID_ATI: | 947 | case PCI_VENDOR_ID_ATI: |
947 | case PCI_VENDOR_ID_AMD: | 948 | case PCI_VENDOR_ID_AMD: |
948 | case PCI_VENDOR_ID_NVIDIA: | 949 | case PCI_VENDOR_ID_NVIDIA: |
949 | if (pci->devfn == 1) { | 950 | if (pci->devfn == 1) { |
950 | p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), | 951 | p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), |
951 | pci->bus->number, 0); | 952 | pci->bus->number, 0); |
952 | if (p) { | 953 | if (p) { |
953 | if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA) | 954 | if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA) |
954 | return p; | 955 | return p; |
955 | pci_dev_put(p); | 956 | pci_dev_put(p); |
956 | } | 957 | } |
957 | } | 958 | } |
958 | break; | 959 | break; |
959 | } | 960 | } |
960 | return NULL; | 961 | return NULL; |
961 | } | 962 | } |
962 | 963 | ||
963 | static bool check_hdmi_disabled(struct pci_dev *pci) | 964 | static bool check_hdmi_disabled(struct pci_dev *pci) |
964 | { | 965 | { |
965 | bool vga_inactive = false; | 966 | bool vga_inactive = false; |
966 | struct pci_dev *p = get_bound_vga(pci); | 967 | struct pci_dev *p = get_bound_vga(pci); |
967 | 968 | ||
968 | if (p) { | 969 | if (p) { |
969 | if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) | 970 | if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) |
970 | vga_inactive = true; | 971 | vga_inactive = true; |
971 | pci_dev_put(p); | 972 | pci_dev_put(p); |
972 | } | 973 | } |
973 | return vga_inactive; | 974 | return vga_inactive; |
974 | } | 975 | } |
975 | #endif /* SUPPORT_VGA_SWITCHEROO */ | 976 | #endif /* SUPPORT_VGA_SWITCHEROO */ |
976 | 977 | ||
977 | /* | 978 | /* |
978 | * white/black-listing for position_fix | 979 | * white/black-listing for position_fix |
979 | */ | 980 | */ |
980 | static struct snd_pci_quirk position_fix_list[] = { | 981 | static struct snd_pci_quirk position_fix_list[] = { |
981 | SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), | 982 | SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), |
982 | SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), | 983 | SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), |
983 | SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), | 984 | SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), |
984 | SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), | 985 | SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), |
985 | SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), | 986 | SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), |
986 | SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), | 987 | SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), |
987 | SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), | 988 | SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), |
988 | SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), | 989 | SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), |
989 | SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), | 990 | SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), |
990 | SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), | 991 | SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), |
991 | SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), | 992 | SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), |
992 | SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), | 993 | SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), |
993 | SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), | 994 | SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), |
994 | SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), | 995 | SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), |
995 | {} | 996 | {} |
996 | }; | 997 | }; |
997 | 998 | ||
998 | static int check_position_fix(struct azx *chip, int fix) | 999 | static int check_position_fix(struct azx *chip, int fix) |
999 | { | 1000 | { |
1000 | const struct snd_pci_quirk *q; | 1001 | const struct snd_pci_quirk *q; |
1001 | 1002 | ||
1002 | switch (fix) { | 1003 | switch (fix) { |
1003 | case POS_FIX_AUTO: | 1004 | case POS_FIX_AUTO: |
1004 | case POS_FIX_LPIB: | 1005 | case POS_FIX_LPIB: |
1005 | case POS_FIX_POSBUF: | 1006 | case POS_FIX_POSBUF: |
1006 | case POS_FIX_VIACOMBO: | 1007 | case POS_FIX_VIACOMBO: |
1007 | case POS_FIX_COMBO: | 1008 | case POS_FIX_COMBO: |
1008 | return fix; | 1009 | return fix; |
1009 | } | 1010 | } |
1010 | 1011 | ||
1011 | q = snd_pci_quirk_lookup(chip->pci, position_fix_list); | 1012 | q = snd_pci_quirk_lookup(chip->pci, position_fix_list); |
1012 | if (q) { | 1013 | if (q) { |
1013 | dev_info(chip->card->dev, | 1014 | dev_info(chip->card->dev, |
1014 | "position_fix set to %d for device %04x:%04x\n", | 1015 | "position_fix set to %d for device %04x:%04x\n", |
1015 | q->value, q->subvendor, q->subdevice); | 1016 | q->value, q->subvendor, q->subdevice); |
1016 | return q->value; | 1017 | return q->value; |
1017 | } | 1018 | } |
1018 | 1019 | ||
1019 | /* Check VIA/ATI HD Audio Controller exist */ | 1020 | /* Check VIA/ATI HD Audio Controller exist */ |
1020 | if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) { | 1021 | if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) { |
1021 | dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); | 1022 | dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); |
1022 | return POS_FIX_VIACOMBO; | 1023 | return POS_FIX_VIACOMBO; |
1023 | } | 1024 | } |
1024 | if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { | 1025 | if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { |
1025 | dev_dbg(chip->card->dev, "Using LPIB position fix\n"); | 1026 | dev_dbg(chip->card->dev, "Using LPIB position fix\n"); |
1026 | return POS_FIX_LPIB; | 1027 | return POS_FIX_LPIB; |
1027 | } | 1028 | } |
1028 | return POS_FIX_AUTO; | 1029 | return POS_FIX_AUTO; |
1029 | } | 1030 | } |
1030 | 1031 | ||
1031 | /* | 1032 | /* |
1032 | * black-lists for probe_mask | 1033 | * black-lists for probe_mask |
1033 | */ | 1034 | */ |
1034 | static struct snd_pci_quirk probe_mask_list[] = { | 1035 | static struct snd_pci_quirk probe_mask_list[] = { |
1035 | /* Thinkpad often breaks the controller communication when accessing | 1036 | /* Thinkpad often breaks the controller communication when accessing |
1036 | * to the non-working (or non-existing) modem codec slot. | 1037 | * to the non-working (or non-existing) modem codec slot. |
1037 | */ | 1038 | */ |
1038 | SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), | 1039 | SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), |
1039 | SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), | 1040 | SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), |
1040 | SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), | 1041 | SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), |
1041 | /* broken BIOS */ | 1042 | /* broken BIOS */ |
1042 | SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), | 1043 | SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), |
1043 | /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ | 1044 | /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ |
1044 | SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), | 1045 | SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), |
1045 | /* forced codec slots */ | 1046 | /* forced codec slots */ |
1046 | SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), | 1047 | SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), |
1047 | SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), | 1048 | SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), |
1048 | /* WinFast VP200 H (Teradici) user reported broken communication */ | 1049 | /* WinFast VP200 H (Teradici) user reported broken communication */ |
1049 | SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), | 1050 | SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), |
1050 | {} | 1051 | {} |
1051 | }; | 1052 | }; |
1052 | 1053 | ||
1053 | #define AZX_FORCE_CODEC_MASK 0x100 | 1054 | #define AZX_FORCE_CODEC_MASK 0x100 |
1054 | 1055 | ||
1055 | static void check_probe_mask(struct azx *chip, int dev) | 1056 | static void check_probe_mask(struct azx *chip, int dev) |
1056 | { | 1057 | { |
1057 | const struct snd_pci_quirk *q; | 1058 | const struct snd_pci_quirk *q; |
1058 | 1059 | ||
1059 | chip->codec_probe_mask = probe_mask[dev]; | 1060 | chip->codec_probe_mask = probe_mask[dev]; |
1060 | if (chip->codec_probe_mask == -1) { | 1061 | if (chip->codec_probe_mask == -1) { |
1061 | q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); | 1062 | q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); |
1062 | if (q) { | 1063 | if (q) { |
1063 | dev_info(chip->card->dev, | 1064 | dev_info(chip->card->dev, |
1064 | "probe_mask set to 0x%x for device %04x:%04x\n", | 1065 | "probe_mask set to 0x%x for device %04x:%04x\n", |
1065 | q->value, q->subvendor, q->subdevice); | 1066 | q->value, q->subvendor, q->subdevice); |
1066 | chip->codec_probe_mask = q->value; | 1067 | chip->codec_probe_mask = q->value; |
1067 | } | 1068 | } |
1068 | } | 1069 | } |
1069 | 1070 | ||
1070 | /* check forced option */ | 1071 | /* check forced option */ |
1071 | if (chip->codec_probe_mask != -1 && | 1072 | if (chip->codec_probe_mask != -1 && |
1072 | (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { | 1073 | (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { |
1073 | chip->codec_mask = chip->codec_probe_mask & 0xff; | 1074 | chip->codec_mask = chip->codec_probe_mask & 0xff; |
1074 | dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", | 1075 | dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", |
1075 | chip->codec_mask); | 1076 | chip->codec_mask); |
1076 | } | 1077 | } |
1077 | } | 1078 | } |
1078 | 1079 | ||
1079 | /* | 1080 | /* |
1080 | * white/black-list for enable_msi | 1081 | * white/black-list for enable_msi |
1081 | */ | 1082 | */ |
1082 | static struct snd_pci_quirk msi_black_list[] = { | 1083 | static struct snd_pci_quirk msi_black_list[] = { |
1083 | SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ | 1084 | SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ |
1084 | SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ | 1085 | SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ |
1085 | SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ | 1086 | SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ |
1086 | SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ | 1087 | SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ |
1087 | SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ | 1088 | SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ |
1088 | SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ | 1089 | SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ |
1089 | SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ | 1090 | SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ |
1090 | SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ | 1091 | SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ |
1091 | SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ | 1092 | SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ |
1092 | SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ | 1093 | SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ |
1093 | {} | 1094 | {} |
1094 | }; | 1095 | }; |
1095 | 1096 | ||
1096 | static void check_msi(struct azx *chip) | 1097 | static void check_msi(struct azx *chip) |
1097 | { | 1098 | { |
1098 | const struct snd_pci_quirk *q; | 1099 | const struct snd_pci_quirk *q; |
1099 | 1100 | ||
1100 | if (enable_msi >= 0) { | 1101 | if (enable_msi >= 0) { |
1101 | chip->msi = !!enable_msi; | 1102 | chip->msi = !!enable_msi; |
1102 | return; | 1103 | return; |
1103 | } | 1104 | } |
1104 | chip->msi = 1; /* enable MSI as default */ | 1105 | chip->msi = 1; /* enable MSI as default */ |
1105 | q = snd_pci_quirk_lookup(chip->pci, msi_black_list); | 1106 | q = snd_pci_quirk_lookup(chip->pci, msi_black_list); |
1106 | if (q) { | 1107 | if (q) { |
1107 | dev_info(chip->card->dev, | 1108 | dev_info(chip->card->dev, |
1108 | "msi for device %04x:%04x set to %d\n", | 1109 | "msi for device %04x:%04x set to %d\n", |
1109 | q->subvendor, q->subdevice, q->value); | 1110 | q->subvendor, q->subdevice, q->value); |
1110 | chip->msi = q->value; | 1111 | chip->msi = q->value; |
1111 | return; | 1112 | return; |
1112 | } | 1113 | } |
1113 | 1114 | ||
1114 | /* NVidia chipsets seem to cause troubles with MSI */ | 1115 | /* NVidia chipsets seem to cause troubles with MSI */ |
1115 | if (chip->driver_caps & AZX_DCAPS_NO_MSI) { | 1116 | if (chip->driver_caps & AZX_DCAPS_NO_MSI) { |
1116 | dev_info(chip->card->dev, "Disabling MSI\n"); | 1117 | dev_info(chip->card->dev, "Disabling MSI\n"); |
1117 | chip->msi = 0; | 1118 | chip->msi = 0; |
1118 | } | 1119 | } |
1119 | } | 1120 | } |
1120 | 1121 | ||
1121 | /* check the snoop mode availability */ | 1122 | /* check the snoop mode availability */ |
1122 | static void azx_check_snoop_available(struct azx *chip) | 1123 | static void azx_check_snoop_available(struct azx *chip) |
1123 | { | 1124 | { |
1124 | bool snoop = chip->snoop; | 1125 | bool snoop = chip->snoop; |
1125 | 1126 | ||
1126 | switch (chip->driver_type) { | 1127 | switch (chip->driver_type) { |
1127 | case AZX_DRIVER_VIA: | 1128 | case AZX_DRIVER_VIA: |
1128 | /* force to non-snoop mode for a new VIA controller | 1129 | /* force to non-snoop mode for a new VIA controller |
1129 | * when BIOS is set | 1130 | * when BIOS is set |
1130 | */ | 1131 | */ |
1131 | if (snoop) { | 1132 | if (snoop) { |
1132 | u8 val; | 1133 | u8 val; |
1133 | pci_read_config_byte(chip->pci, 0x42, &val); | 1134 | pci_read_config_byte(chip->pci, 0x42, &val); |
1134 | if (!(val & 0x80) && chip->pci->revision == 0x30) | 1135 | if (!(val & 0x80) && chip->pci->revision == 0x30) |
1135 | snoop = false; | 1136 | snoop = false; |
1136 | } | 1137 | } |
1137 | break; | 1138 | break; |
1138 | case AZX_DRIVER_ATIHDMI_NS: | 1139 | case AZX_DRIVER_ATIHDMI_NS: |
1139 | /* new ATI HDMI requires non-snoop */ | 1140 | /* new ATI HDMI requires non-snoop */ |
1140 | snoop = false; | 1141 | snoop = false; |
1141 | break; | 1142 | break; |
1142 | case AZX_DRIVER_CTHDA: | 1143 | case AZX_DRIVER_CTHDA: |
1143 | snoop = false; | 1144 | snoop = false; |
1144 | break; | 1145 | break; |
1145 | } | 1146 | } |
1146 | 1147 | ||
1147 | if (snoop != chip->snoop) { | 1148 | if (snoop != chip->snoop) { |
1148 | dev_info(chip->card->dev, "Force to %s mode\n", | 1149 | dev_info(chip->card->dev, "Force to %s mode\n", |
1149 | snoop ? "snoop" : "non-snoop"); | 1150 | snoop ? "snoop" : "non-snoop"); |
1150 | chip->snoop = snoop; | 1151 | chip->snoop = snoop; |
1151 | } | 1152 | } |
1152 | } | 1153 | } |
1153 | 1154 | ||
1154 | static void azx_probe_work(struct work_struct *work) | 1155 | static void azx_probe_work(struct work_struct *work) |
1155 | { | 1156 | { |
1156 | azx_probe_continue(container_of(work, struct azx, probe_work)); | 1157 | azx_probe_continue(container_of(work, struct azx, probe_work)); |
1157 | } | 1158 | } |
1158 | 1159 | ||
1159 | /* | 1160 | /* |
1160 | * constructor | 1161 | * constructor |
1161 | */ | 1162 | */ |
1162 | static int azx_create(struct snd_card *card, struct pci_dev *pci, | 1163 | static int azx_create(struct snd_card *card, struct pci_dev *pci, |
1163 | int dev, unsigned int driver_caps, | 1164 | int dev, unsigned int driver_caps, |
1164 | const struct hda_controller_ops *hda_ops, | 1165 | const struct hda_controller_ops *hda_ops, |
1165 | struct azx **rchip) | 1166 | struct azx **rchip) |
1166 | { | 1167 | { |
1167 | static struct snd_device_ops ops = { | 1168 | static struct snd_device_ops ops = { |
1168 | .dev_free = azx_dev_free, | 1169 | .dev_free = azx_dev_free, |
1169 | }; | 1170 | }; |
1170 | struct azx *chip; | 1171 | struct azx *chip; |
1171 | int err; | 1172 | int err; |
1172 | 1173 | ||
1173 | *rchip = NULL; | 1174 | *rchip = NULL; |
1174 | 1175 | ||
1175 | err = pci_enable_device(pci); | 1176 | err = pci_enable_device(pci); |
1176 | if (err < 0) | 1177 | if (err < 0) |
1177 | return err; | 1178 | return err; |
1178 | 1179 | ||
1179 | chip = kzalloc(sizeof(*chip), GFP_KERNEL); | 1180 | chip = kzalloc(sizeof(*chip), GFP_KERNEL); |
1180 | if (!chip) { | 1181 | if (!chip) { |
1181 | dev_err(card->dev, "Cannot allocate chip\n"); | 1182 | dev_err(card->dev, "Cannot allocate chip\n"); |
1182 | pci_disable_device(pci); | 1183 | pci_disable_device(pci); |
1183 | return -ENOMEM; | 1184 | return -ENOMEM; |
1184 | } | 1185 | } |
1185 | 1186 | ||
1186 | spin_lock_init(&chip->reg_lock); | 1187 | spin_lock_init(&chip->reg_lock); |
1187 | mutex_init(&chip->open_mutex); | 1188 | mutex_init(&chip->open_mutex); |
1188 | chip->card = card; | 1189 | chip->card = card; |
1189 | chip->pci = pci; | 1190 | chip->pci = pci; |
1190 | chip->ops = hda_ops; | 1191 | chip->ops = hda_ops; |
1191 | chip->irq = -1; | 1192 | chip->irq = -1; |
1192 | chip->driver_caps = driver_caps; | 1193 | chip->driver_caps = driver_caps; |
1193 | chip->driver_type = driver_caps & 0xff; | 1194 | chip->driver_type = driver_caps & 0xff; |
1194 | check_msi(chip); | 1195 | check_msi(chip); |
1195 | chip->dev_index = dev; | 1196 | chip->dev_index = dev; |
1196 | chip->jackpoll_ms = jackpoll_ms; | 1197 | chip->jackpoll_ms = jackpoll_ms; |
1197 | INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work); | 1198 | INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work); |
1198 | INIT_LIST_HEAD(&chip->pcm_list); | 1199 | INIT_LIST_HEAD(&chip->pcm_list); |
1199 | INIT_LIST_HEAD(&chip->list); | 1200 | INIT_LIST_HEAD(&chip->list); |
1200 | init_vga_switcheroo(chip); | 1201 | init_vga_switcheroo(chip); |
1201 | init_completion(&chip->probe_wait); | 1202 | init_completion(&chip->probe_wait); |
1202 | 1203 | ||
1203 | chip->position_fix[0] = chip->position_fix[1] = | 1204 | chip->position_fix[0] = chip->position_fix[1] = |
1204 | check_position_fix(chip, position_fix[dev]); | 1205 | check_position_fix(chip, position_fix[dev]); |
1205 | /* combo mode uses LPIB for playback */ | 1206 | /* combo mode uses LPIB for playback */ |
1206 | if (chip->position_fix[0] == POS_FIX_COMBO) { | 1207 | if (chip->position_fix[0] == POS_FIX_COMBO) { |
1207 | chip->position_fix[0] = POS_FIX_LPIB; | 1208 | chip->position_fix[0] = POS_FIX_LPIB; |
1208 | chip->position_fix[1] = POS_FIX_AUTO; | 1209 | chip->position_fix[1] = POS_FIX_AUTO; |
1209 | } | 1210 | } |
1210 | 1211 | ||
1211 | check_probe_mask(chip, dev); | 1212 | check_probe_mask(chip, dev); |
1212 | 1213 | ||
1213 | chip->single_cmd = single_cmd; | 1214 | chip->single_cmd = single_cmd; |
1214 | chip->snoop = hda_snoop; | 1215 | chip->snoop = hda_snoop; |
1215 | azx_check_snoop_available(chip); | 1216 | azx_check_snoop_available(chip); |
1216 | 1217 | ||
1217 | if (bdl_pos_adj[dev] < 0) { | 1218 | if (bdl_pos_adj[dev] < 0) { |
1218 | switch (chip->driver_type) { | 1219 | switch (chip->driver_type) { |
1219 | case AZX_DRIVER_ICH: | 1220 | case AZX_DRIVER_ICH: |
1220 | case AZX_DRIVER_PCH: | 1221 | case AZX_DRIVER_PCH: |
1221 | bdl_pos_adj[dev] = 1; | 1222 | bdl_pos_adj[dev] = 1; |
1222 | break; | 1223 | break; |
1223 | default: | 1224 | default: |
1224 | bdl_pos_adj[dev] = 32; | 1225 | bdl_pos_adj[dev] = 32; |
1225 | break; | 1226 | break; |
1226 | } | 1227 | } |
1227 | } | 1228 | } |
1228 | chip->bdl_pos_adj = bdl_pos_adj; | 1229 | chip->bdl_pos_adj = bdl_pos_adj; |
1229 | 1230 | ||
1230 | err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); | 1231 | err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); |
1231 | if (err < 0) { | 1232 | if (err < 0) { |
1232 | dev_err(card->dev, "Error creating device [card]!\n"); | 1233 | dev_err(card->dev, "Error creating device [card]!\n"); |
1233 | azx_free(chip); | 1234 | azx_free(chip); |
1234 | return err; | 1235 | return err; |
1235 | } | 1236 | } |
1236 | 1237 | ||
1237 | /* continue probing in work context as may trigger request module */ | 1238 | /* continue probing in work context as may trigger request module */ |
1238 | INIT_WORK(&chip->probe_work, azx_probe_work); | 1239 | INIT_WORK(&chip->probe_work, azx_probe_work); |
1239 | 1240 | ||
1240 | *rchip = chip; | 1241 | *rchip = chip; |
1241 | 1242 | ||
1242 | return 0; | 1243 | return 0; |
1243 | } | 1244 | } |
1244 | 1245 | ||
1245 | static int azx_first_init(struct azx *chip) | 1246 | static int azx_first_init(struct azx *chip) |
1246 | { | 1247 | { |
1247 | int dev = chip->dev_index; | 1248 | int dev = chip->dev_index; |
1248 | struct pci_dev *pci = chip->pci; | 1249 | struct pci_dev *pci = chip->pci; |
1249 | struct snd_card *card = chip->card; | 1250 | struct snd_card *card = chip->card; |
1250 | int err; | 1251 | int err; |
1251 | unsigned short gcap; | 1252 | unsigned short gcap; |
1252 | 1253 | ||
1253 | #if BITS_PER_LONG != 64 | 1254 | #if BITS_PER_LONG != 64 |
1254 | /* Fix up base address on ULI M5461 */ | 1255 | /* Fix up base address on ULI M5461 */ |
1255 | if (chip->driver_type == AZX_DRIVER_ULI) { | 1256 | if (chip->driver_type == AZX_DRIVER_ULI) { |
1256 | u16 tmp3; | 1257 | u16 tmp3; |
1257 | pci_read_config_word(pci, 0x40, &tmp3); | 1258 | pci_read_config_word(pci, 0x40, &tmp3); |
1258 | pci_write_config_word(pci, 0x40, tmp3 | 0x10); | 1259 | pci_write_config_word(pci, 0x40, tmp3 | 0x10); |
1259 | pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); | 1260 | pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); |
1260 | } | 1261 | } |
1261 | #endif | 1262 | #endif |
1262 | 1263 | ||
1263 | err = pci_request_regions(pci, "ICH HD audio"); | 1264 | err = pci_request_regions(pci, "ICH HD audio"); |
1264 | if (err < 0) | 1265 | if (err < 0) |
1265 | return err; | 1266 | return err; |
1266 | chip->region_requested = 1; | 1267 | chip->region_requested = 1; |
1267 | 1268 | ||
1268 | chip->addr = pci_resource_start(pci, 0); | 1269 | chip->addr = pci_resource_start(pci, 0); |
1269 | chip->remap_addr = pci_ioremap_bar(pci, 0); | 1270 | chip->remap_addr = pci_ioremap_bar(pci, 0); |
1270 | if (chip->remap_addr == NULL) { | 1271 | if (chip->remap_addr == NULL) { |
1271 | dev_err(card->dev, "ioremap error\n"); | 1272 | dev_err(card->dev, "ioremap error\n"); |
1272 | return -ENXIO; | 1273 | return -ENXIO; |
1273 | } | 1274 | } |
1274 | 1275 | ||
1275 | if (chip->msi) | 1276 | if (chip->msi) |
1276 | if (pci_enable_msi(pci) < 0) | 1277 | if (pci_enable_msi(pci) < 0) |
1277 | chip->msi = 0; | 1278 | chip->msi = 0; |
1278 | 1279 | ||
1279 | if (azx_acquire_irq(chip, 0) < 0) | 1280 | if (azx_acquire_irq(chip, 0) < 0) |
1280 | return -EBUSY; | 1281 | return -EBUSY; |
1281 | 1282 | ||
1282 | pci_set_master(pci); | 1283 | pci_set_master(pci); |
1283 | synchronize_irq(chip->irq); | 1284 | synchronize_irq(chip->irq); |
1284 | 1285 | ||
1285 | gcap = azx_readw(chip, GCAP); | 1286 | gcap = azx_readw(chip, GCAP); |
1286 | dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); | 1287 | dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); |
1287 | 1288 | ||
1288 | /* disable SB600 64bit support for safety */ | 1289 | /* disable SB600 64bit support for safety */ |
1289 | if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { | 1290 | if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { |
1290 | struct pci_dev *p_smbus; | 1291 | struct pci_dev *p_smbus; |
1291 | p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, | 1292 | p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, |
1292 | PCI_DEVICE_ID_ATI_SBX00_SMBUS, | 1293 | PCI_DEVICE_ID_ATI_SBX00_SMBUS, |
1293 | NULL); | 1294 | NULL); |
1294 | if (p_smbus) { | 1295 | if (p_smbus) { |
1295 | if (p_smbus->revision < 0x30) | 1296 | if (p_smbus->revision < 0x30) |
1296 | gcap &= ~ICH6_GCAP_64OK; | 1297 | gcap &= ~ICH6_GCAP_64OK; |
1297 | pci_dev_put(p_smbus); | 1298 | pci_dev_put(p_smbus); |
1298 | } | 1299 | } |
1299 | } | 1300 | } |
1300 | 1301 | ||
1301 | /* disable 64bit DMA address on some devices */ | 1302 | /* disable 64bit DMA address on some devices */ |
1302 | if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { | 1303 | if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { |
1303 | dev_dbg(card->dev, "Disabling 64bit DMA\n"); | 1304 | dev_dbg(card->dev, "Disabling 64bit DMA\n"); |
1304 | gcap &= ~ICH6_GCAP_64OK; | 1305 | gcap &= ~ICH6_GCAP_64OK; |
1305 | } | 1306 | } |
1306 | 1307 | ||
1307 | /* disable buffer size rounding to 128-byte multiples if supported */ | 1308 | /* disable buffer size rounding to 128-byte multiples if supported */ |
1308 | if (align_buffer_size >= 0) | 1309 | if (align_buffer_size >= 0) |
1309 | chip->align_buffer_size = !!align_buffer_size; | 1310 | chip->align_buffer_size = !!align_buffer_size; |
1310 | else { | 1311 | else { |
1311 | if (chip->driver_caps & AZX_DCAPS_BUFSIZE) | 1312 | if (chip->driver_caps & AZX_DCAPS_BUFSIZE) |
1312 | chip->align_buffer_size = 0; | 1313 | chip->align_buffer_size = 0; |
1313 | else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE) | 1314 | else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE) |
1314 | chip->align_buffer_size = 1; | 1315 | chip->align_buffer_size = 1; |
1315 | else | 1316 | else |
1316 | chip->align_buffer_size = 1; | 1317 | chip->align_buffer_size = 1; |
1317 | } | 1318 | } |
1318 | 1319 | ||
1319 | /* allow 64bit DMA address if supported by H/W */ | 1320 | /* allow 64bit DMA address if supported by H/W */ |
1320 | if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64))) | 1321 | if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64))) |
1321 | pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64)); | 1322 | pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64)); |
1322 | else { | 1323 | else { |
1323 | pci_set_dma_mask(pci, DMA_BIT_MASK(32)); | 1324 | pci_set_dma_mask(pci, DMA_BIT_MASK(32)); |
1324 | pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32)); | 1325 | pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32)); |
1325 | } | 1326 | } |
1326 | 1327 | ||
1327 | /* read number of streams from GCAP register instead of using | 1328 | /* read number of streams from GCAP register instead of using |
1328 | * hardcoded value | 1329 | * hardcoded value |
1329 | */ | 1330 | */ |
1330 | chip->capture_streams = (gcap >> 8) & 0x0f; | 1331 | chip->capture_streams = (gcap >> 8) & 0x0f; |
1331 | chip->playback_streams = (gcap >> 12) & 0x0f; | 1332 | chip->playback_streams = (gcap >> 12) & 0x0f; |
1332 | if (!chip->playback_streams && !chip->capture_streams) { | 1333 | if (!chip->playback_streams && !chip->capture_streams) { |
1333 | /* gcap didn't give any info, switching to old method */ | 1334 | /* gcap didn't give any info, switching to old method */ |
1334 | 1335 | ||
1335 | switch (chip->driver_type) { | 1336 | switch (chip->driver_type) { |
1336 | case AZX_DRIVER_ULI: | 1337 | case AZX_DRIVER_ULI: |
1337 | chip->playback_streams = ULI_NUM_PLAYBACK; | 1338 | chip->playback_streams = ULI_NUM_PLAYBACK; |
1338 | chip->capture_streams = ULI_NUM_CAPTURE; | 1339 | chip->capture_streams = ULI_NUM_CAPTURE; |
1339 | break; | 1340 | break; |
1340 | case AZX_DRIVER_ATIHDMI: | 1341 | case AZX_DRIVER_ATIHDMI: |
1341 | case AZX_DRIVER_ATIHDMI_NS: | 1342 | case AZX_DRIVER_ATIHDMI_NS: |
1342 | chip->playback_streams = ATIHDMI_NUM_PLAYBACK; | 1343 | chip->playback_streams = ATIHDMI_NUM_PLAYBACK; |
1343 | chip->capture_streams = ATIHDMI_NUM_CAPTURE; | 1344 | chip->capture_streams = ATIHDMI_NUM_CAPTURE; |
1344 | break; | 1345 | break; |
1345 | case AZX_DRIVER_GENERIC: | 1346 | case AZX_DRIVER_GENERIC: |
1346 | default: | 1347 | default: |
1347 | chip->playback_streams = ICH6_NUM_PLAYBACK; | 1348 | chip->playback_streams = ICH6_NUM_PLAYBACK; |
1348 | chip->capture_streams = ICH6_NUM_CAPTURE; | 1349 | chip->capture_streams = ICH6_NUM_CAPTURE; |
1349 | break; | 1350 | break; |
1350 | } | 1351 | } |
1351 | } | 1352 | } |
1352 | chip->capture_index_offset = 0; | 1353 | chip->capture_index_offset = 0; |
1353 | chip->playback_index_offset = chip->capture_streams; | 1354 | chip->playback_index_offset = chip->capture_streams; |
1354 | chip->num_streams = chip->playback_streams + chip->capture_streams; | 1355 | chip->num_streams = chip->playback_streams + chip->capture_streams; |
1355 | chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev), | 1356 | chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev), |
1356 | GFP_KERNEL); | 1357 | GFP_KERNEL); |
1357 | if (!chip->azx_dev) { | 1358 | if (!chip->azx_dev) { |
1358 | dev_err(card->dev, "cannot malloc azx_dev\n"); | 1359 | dev_err(card->dev, "cannot malloc azx_dev\n"); |
1359 | return -ENOMEM; | 1360 | return -ENOMEM; |
1360 | } | 1361 | } |
1361 | 1362 | ||
1362 | err = azx_alloc_stream_pages(chip); | 1363 | err = azx_alloc_stream_pages(chip); |
1363 | if (err < 0) | 1364 | if (err < 0) |
1364 | return err; | 1365 | return err; |
1365 | 1366 | ||
1366 | /* initialize streams */ | 1367 | /* initialize streams */ |
1367 | azx_init_stream(chip); | 1368 | azx_init_stream(chip); |
1368 | 1369 | ||
1369 | /* initialize chip */ | 1370 | /* initialize chip */ |
1370 | azx_init_pci(chip); | 1371 | azx_init_pci(chip); |
1371 | azx_init_chip(chip, (probe_only[dev] & 2) == 0); | 1372 | azx_init_chip(chip, (probe_only[dev] & 2) == 0); |
1372 | 1373 | ||
1373 | /* codec detection */ | 1374 | /* codec detection */ |
1374 | if (!chip->codec_mask) { | 1375 | if (!chip->codec_mask) { |
1375 | dev_err(card->dev, "no codecs found!\n"); | 1376 | dev_err(card->dev, "no codecs found!\n"); |
1376 | return -ENODEV; | 1377 | return -ENODEV; |
1377 | } | 1378 | } |
1378 | 1379 | ||
1379 | strcpy(card->driver, "HDA-Intel"); | 1380 | strcpy(card->driver, "HDA-Intel"); |
1380 | strlcpy(card->shortname, driver_short_names[chip->driver_type], | 1381 | strlcpy(card->shortname, driver_short_names[chip->driver_type], |
1381 | sizeof(card->shortname)); | 1382 | sizeof(card->shortname)); |
1382 | snprintf(card->longname, sizeof(card->longname), | 1383 | snprintf(card->longname, sizeof(card->longname), |
1383 | "%s at 0x%lx irq %i", | 1384 | "%s at 0x%lx irq %i", |
1384 | card->shortname, chip->addr, chip->irq); | 1385 | card->shortname, chip->addr, chip->irq); |
1385 | 1386 | ||
1386 | return 0; | 1387 | return 0; |
1387 | } | 1388 | } |
1388 | 1389 | ||
1389 | static void power_down_all_codecs(struct azx *chip) | 1390 | static void power_down_all_codecs(struct azx *chip) |
1390 | { | 1391 | { |
1391 | #ifdef CONFIG_PM | 1392 | #ifdef CONFIG_PM |
1392 | /* The codecs were powered up in snd_hda_codec_new(). | 1393 | /* The codecs were powered up in snd_hda_codec_new(). |
1393 | * Now all initialization done, so turn them down if possible | 1394 | * Now all initialization done, so turn them down if possible |
1394 | */ | 1395 | */ |
1395 | struct hda_codec *codec; | 1396 | struct hda_codec *codec; |
1396 | list_for_each_entry(codec, &chip->bus->codec_list, list) { | 1397 | list_for_each_entry(codec, &chip->bus->codec_list, list) { |
1397 | snd_hda_power_down(codec); | 1398 | snd_hda_power_down(codec); |
1398 | } | 1399 | } |
1399 | #endif | 1400 | #endif |
1400 | } | 1401 | } |
1401 | 1402 | ||
1402 | #ifdef CONFIG_SND_HDA_PATCH_LOADER | 1403 | #ifdef CONFIG_SND_HDA_PATCH_LOADER |
1403 | /* callback from request_firmware_nowait() */ | 1404 | /* callback from request_firmware_nowait() */ |
1404 | static void azx_firmware_cb(const struct firmware *fw, void *context) | 1405 | static void azx_firmware_cb(const struct firmware *fw, void *context) |
1405 | { | 1406 | { |
1406 | struct snd_card *card = context; | 1407 | struct snd_card *card = context; |
1407 | struct azx *chip = card->private_data; | 1408 | struct azx *chip = card->private_data; |
1408 | struct pci_dev *pci = chip->pci; | 1409 | struct pci_dev *pci = chip->pci; |
1409 | 1410 | ||
1410 | if (!fw) { | 1411 | if (!fw) { |
1411 | dev_err(card->dev, "Cannot load firmware, aborting\n"); | 1412 | dev_err(card->dev, "Cannot load firmware, aborting\n"); |
1412 | goto error; | 1413 | goto error; |
1413 | } | 1414 | } |
1414 | 1415 | ||
1415 | chip->fw = fw; | 1416 | chip->fw = fw; |
1416 | if (!chip->disabled) { | 1417 | if (!chip->disabled) { |
1417 | /* continue probing */ | 1418 | /* continue probing */ |
1418 | if (azx_probe_continue(chip)) | 1419 | if (azx_probe_continue(chip)) |
1419 | goto error; | 1420 | goto error; |
1420 | } | 1421 | } |
1421 | return; /* OK */ | 1422 | return; /* OK */ |
1422 | 1423 | ||
1423 | error: | 1424 | error: |
1424 | snd_card_free(card); | 1425 | snd_card_free(card); |
1425 | pci_set_drvdata(pci, NULL); | 1426 | pci_set_drvdata(pci, NULL); |
1426 | } | 1427 | } |
1427 | #endif | 1428 | #endif |
1428 | 1429 | ||
1429 | /* | 1430 | /* |
1430 | * HDA controller ops. | 1431 | * HDA controller ops. |
1431 | */ | 1432 | */ |
1432 | 1433 | ||
1433 | /* PCI register access. */ | 1434 | /* PCI register access. */ |
1434 | static void pci_azx_writel(u32 value, u32 __iomem *addr) | 1435 | static void pci_azx_writel(u32 value, u32 __iomem *addr) |
1435 | { | 1436 | { |
1436 | writel(value, addr); | 1437 | writel(value, addr); |
1437 | } | 1438 | } |
1438 | 1439 | ||
1439 | static u32 pci_azx_readl(u32 __iomem *addr) | 1440 | static u32 pci_azx_readl(u32 __iomem *addr) |
1440 | { | 1441 | { |
1441 | return readl(addr); | 1442 | return readl(addr); |
1442 | } | 1443 | } |
1443 | 1444 | ||
1444 | static void pci_azx_writew(u16 value, u16 __iomem *addr) | 1445 | static void pci_azx_writew(u16 value, u16 __iomem *addr) |
1445 | { | 1446 | { |
1446 | writew(value, addr); | 1447 | writew(value, addr); |
1447 | } | 1448 | } |
1448 | 1449 | ||
1449 | static u16 pci_azx_readw(u16 __iomem *addr) | 1450 | static u16 pci_azx_readw(u16 __iomem *addr) |
1450 | { | 1451 | { |
1451 | return readw(addr); | 1452 | return readw(addr); |
1452 | } | 1453 | } |
1453 | 1454 | ||
1454 | static void pci_azx_writeb(u8 value, u8 __iomem *addr) | 1455 | static void pci_azx_writeb(u8 value, u8 __iomem *addr) |
1455 | { | 1456 | { |
1456 | writeb(value, addr); | 1457 | writeb(value, addr); |
1457 | } | 1458 | } |
1458 | 1459 | ||
1459 | static u8 pci_azx_readb(u8 __iomem *addr) | 1460 | static u8 pci_azx_readb(u8 __iomem *addr) |
1460 | { | 1461 | { |
1461 | return readb(addr); | 1462 | return readb(addr); |
1462 | } | 1463 | } |
1463 | 1464 | ||
1464 | static int disable_msi_reset_irq(struct azx *chip) | 1465 | static int disable_msi_reset_irq(struct azx *chip) |
1465 | { | 1466 | { |
1466 | int err; | 1467 | int err; |
1467 | 1468 | ||
1468 | free_irq(chip->irq, chip); | 1469 | free_irq(chip->irq, chip); |
1469 | chip->irq = -1; | 1470 | chip->irq = -1; |
1470 | pci_disable_msi(chip->pci); | 1471 | pci_disable_msi(chip->pci); |
1471 | chip->msi = 0; | 1472 | chip->msi = 0; |
1472 | err = azx_acquire_irq(chip, 1); | 1473 | err = azx_acquire_irq(chip, 1); |
1473 | if (err < 0) | 1474 | if (err < 0) |
1474 | return err; | 1475 | return err; |
1475 | 1476 | ||
1476 | return 0; | 1477 | return 0; |
1477 | } | 1478 | } |
1478 | 1479 | ||
1479 | /* DMA page allocation helpers. */ | 1480 | /* DMA page allocation helpers. */ |
1480 | static int dma_alloc_pages(struct azx *chip, | 1481 | static int dma_alloc_pages(struct azx *chip, |
1481 | int type, | 1482 | int type, |
1482 | size_t size, | 1483 | size_t size, |
1483 | struct snd_dma_buffer *buf) | 1484 | struct snd_dma_buffer *buf) |
1484 | { | 1485 | { |
1485 | int err; | 1486 | int err; |
1486 | 1487 | ||
1487 | err = snd_dma_alloc_pages(type, | 1488 | err = snd_dma_alloc_pages(type, |
1488 | chip->card->dev, | 1489 | chip->card->dev, |
1489 | size, buf); | 1490 | size, buf); |
1490 | if (err < 0) | 1491 | if (err < 0) |
1491 | return err; | 1492 | return err; |
1492 | mark_pages_wc(chip, buf, true); | 1493 | mark_pages_wc(chip, buf, true); |
1493 | return 0; | 1494 | return 0; |
1494 | } | 1495 | } |
1495 | 1496 | ||
1496 | static void dma_free_pages(struct azx *chip, struct snd_dma_buffer *buf) | 1497 | static void dma_free_pages(struct azx *chip, struct snd_dma_buffer *buf) |
1497 | { | 1498 | { |
1498 | mark_pages_wc(chip, buf, false); | 1499 | mark_pages_wc(chip, buf, false); |
1499 | snd_dma_free_pages(buf); | 1500 | snd_dma_free_pages(buf); |
1500 | } | 1501 | } |
1501 | 1502 | ||
1502 | static int substream_alloc_pages(struct azx *chip, | 1503 | static int substream_alloc_pages(struct azx *chip, |
1503 | struct snd_pcm_substream *substream, | 1504 | struct snd_pcm_substream *substream, |
1504 | size_t size) | 1505 | size_t size) |
1505 | { | 1506 | { |
1506 | struct azx_dev *azx_dev = get_azx_dev(substream); | 1507 | struct azx_dev *azx_dev = get_azx_dev(substream); |
1507 | int ret; | 1508 | int ret; |
1508 | 1509 | ||
1509 | mark_runtime_wc(chip, azx_dev, substream, false); | 1510 | mark_runtime_wc(chip, azx_dev, substream, false); |
1510 | azx_dev->bufsize = 0; | 1511 | azx_dev->bufsize = 0; |
1511 | azx_dev->period_bytes = 0; | 1512 | azx_dev->period_bytes = 0; |
1512 | azx_dev->format_val = 0; | 1513 | azx_dev->format_val = 0; |
1513 | ret = snd_pcm_lib_malloc_pages(substream, size); | 1514 | ret = snd_pcm_lib_malloc_pages(substream, size); |
1514 | if (ret < 0) | 1515 | if (ret < 0) |
1515 | return ret; | 1516 | return ret; |
1516 | mark_runtime_wc(chip, azx_dev, substream, true); | 1517 | mark_runtime_wc(chip, azx_dev, substream, true); |
1517 | return 0; | 1518 | return 0; |
1518 | } | 1519 | } |
1519 | 1520 | ||
1520 | static int substream_free_pages(struct azx *chip, | 1521 | static int substream_free_pages(struct azx *chip, |
1521 | struct snd_pcm_substream *substream) | 1522 | struct snd_pcm_substream *substream) |
1522 | { | 1523 | { |
1523 | struct azx_dev *azx_dev = get_azx_dev(substream); | 1524 | struct azx_dev *azx_dev = get_azx_dev(substream); |
1524 | mark_runtime_wc(chip, azx_dev, substream, false); | 1525 | mark_runtime_wc(chip, azx_dev, substream, false); |
1525 | return snd_pcm_lib_free_pages(substream); | 1526 | return snd_pcm_lib_free_pages(substream); |
1526 | } | 1527 | } |
1527 | 1528 | ||
1528 | static void pcm_mmap_prepare(struct snd_pcm_substream *substream, | 1529 | static void pcm_mmap_prepare(struct snd_pcm_substream *substream, |
1529 | struct vm_area_struct *area) | 1530 | struct vm_area_struct *area) |
1530 | { | 1531 | { |
1531 | #ifdef CONFIG_X86 | 1532 | #ifdef CONFIG_X86 |
1532 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | 1533 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); |
1533 | struct azx *chip = apcm->chip; | 1534 | struct azx *chip = apcm->chip; |
1534 | if (!azx_snoop(chip)) | 1535 | if (!azx_snoop(chip)) |
1535 | area->vm_page_prot = pgprot_writecombine(area->vm_page_prot); | 1536 | area->vm_page_prot = pgprot_writecombine(area->vm_page_prot); |
1536 | #endif | 1537 | #endif |
1537 | } | 1538 | } |
1538 | 1539 | ||
1539 | static const struct hda_controller_ops pci_hda_ops = { | 1540 | static const struct hda_controller_ops pci_hda_ops = { |
1540 | .reg_writel = pci_azx_writel, | 1541 | .reg_writel = pci_azx_writel, |
1541 | .reg_readl = pci_azx_readl, | 1542 | .reg_readl = pci_azx_readl, |
1542 | .reg_writew = pci_azx_writew, | 1543 | .reg_writew = pci_azx_writew, |
1543 | .reg_readw = pci_azx_readw, | 1544 | .reg_readw = pci_azx_readw, |
1544 | .reg_writeb = pci_azx_writeb, | 1545 | .reg_writeb = pci_azx_writeb, |
1545 | .reg_readb = pci_azx_readb, | 1546 | .reg_readb = pci_azx_readb, |
1546 | .disable_msi_reset_irq = disable_msi_reset_irq, | 1547 | .disable_msi_reset_irq = disable_msi_reset_irq, |
1547 | .dma_alloc_pages = dma_alloc_pages, | 1548 | .dma_alloc_pages = dma_alloc_pages, |
1548 | .dma_free_pages = dma_free_pages, | 1549 | .dma_free_pages = dma_free_pages, |
1549 | .substream_alloc_pages = substream_alloc_pages, | 1550 | .substream_alloc_pages = substream_alloc_pages, |
1550 | .substream_free_pages = substream_free_pages, | 1551 | .substream_free_pages = substream_free_pages, |
1551 | .pcm_mmap_prepare = pcm_mmap_prepare, | 1552 | .pcm_mmap_prepare = pcm_mmap_prepare, |
1552 | .position_check = azx_position_check, | 1553 | .position_check = azx_position_check, |
1553 | }; | 1554 | }; |
1554 | 1555 | ||
1555 | static int azx_probe(struct pci_dev *pci, | 1556 | static int azx_probe(struct pci_dev *pci, |
1556 | const struct pci_device_id *pci_id) | 1557 | const struct pci_device_id *pci_id) |
1557 | { | 1558 | { |
1558 | static int dev; | 1559 | static int dev; |
1559 | struct snd_card *card; | 1560 | struct snd_card *card; |
1560 | struct azx *chip; | 1561 | struct azx *chip; |
1561 | bool schedule_probe; | 1562 | bool schedule_probe; |
1562 | int err; | 1563 | int err; |
1563 | 1564 | ||
1564 | if (dev >= SNDRV_CARDS) | 1565 | if (dev >= SNDRV_CARDS) |
1565 | return -ENODEV; | 1566 | return -ENODEV; |
1566 | if (!enable[dev]) { | 1567 | if (!enable[dev]) { |
1567 | dev++; | 1568 | dev++; |
1568 | return -ENOENT; | 1569 | return -ENOENT; |
1569 | } | 1570 | } |
1570 | 1571 | ||
1571 | err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, | 1572 | err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, |
1572 | 0, &card); | 1573 | 0, &card); |
1573 | if (err < 0) { | 1574 | if (err < 0) { |
1574 | dev_err(&pci->dev, "Error creating card!\n"); | 1575 | dev_err(&pci->dev, "Error creating card!\n"); |
1575 | return err; | 1576 | return err; |
1576 | } | 1577 | } |
1577 | 1578 | ||
1578 | err = azx_create(card, pci, dev, pci_id->driver_data, | 1579 | err = azx_create(card, pci, dev, pci_id->driver_data, |
1579 | &pci_hda_ops, &chip); | 1580 | &pci_hda_ops, &chip); |
1580 | if (err < 0) | 1581 | if (err < 0) |
1581 | goto out_free; | 1582 | goto out_free; |
1582 | card->private_data = chip; | 1583 | card->private_data = chip; |
1583 | 1584 | ||
1584 | pci_set_drvdata(pci, card); | 1585 | pci_set_drvdata(pci, card); |
1585 | 1586 | ||
1586 | err = register_vga_switcheroo(chip); | 1587 | err = register_vga_switcheroo(chip); |
1587 | if (err < 0) { | 1588 | if (err < 0) { |
1588 | dev_err(card->dev, "Error registering VGA-switcheroo client\n"); | 1589 | dev_err(card->dev, "Error registering VGA-switcheroo client\n"); |
1589 | goto out_free; | 1590 | goto out_free; |
1590 | } | 1591 | } |
1591 | 1592 | ||
1592 | if (check_hdmi_disabled(pci)) { | 1593 | if (check_hdmi_disabled(pci)) { |
1593 | dev_info(card->dev, "VGA controller is disabled\n"); | 1594 | dev_info(card->dev, "VGA controller is disabled\n"); |
1594 | dev_info(card->dev, "Delaying initialization\n"); | 1595 | dev_info(card->dev, "Delaying initialization\n"); |
1595 | chip->disabled = true; | 1596 | chip->disabled = true; |
1596 | } | 1597 | } |
1597 | 1598 | ||
1598 | schedule_probe = !chip->disabled; | 1599 | schedule_probe = !chip->disabled; |
1599 | 1600 | ||
1600 | #ifdef CONFIG_SND_HDA_PATCH_LOADER | 1601 | #ifdef CONFIG_SND_HDA_PATCH_LOADER |
1601 | if (patch[dev] && *patch[dev]) { | 1602 | if (patch[dev] && *patch[dev]) { |
1602 | dev_info(card->dev, "Applying patch firmware '%s'\n", | 1603 | dev_info(card->dev, "Applying patch firmware '%s'\n", |
1603 | patch[dev]); | 1604 | patch[dev]); |
1604 | err = request_firmware_nowait(THIS_MODULE, true, patch[dev], | 1605 | err = request_firmware_nowait(THIS_MODULE, true, patch[dev], |
1605 | &pci->dev, GFP_KERNEL, card, | 1606 | &pci->dev, GFP_KERNEL, card, |
1606 | azx_firmware_cb); | 1607 | azx_firmware_cb); |
1607 | if (err < 0) | 1608 | if (err < 0) |
1608 | goto out_free; | 1609 | goto out_free; |
1609 | schedule_probe = false; /* continued in azx_firmware_cb() */ | 1610 | schedule_probe = false; /* continued in azx_firmware_cb() */ |
1610 | } | 1611 | } |
1611 | #endif /* CONFIG_SND_HDA_PATCH_LOADER */ | 1612 | #endif /* CONFIG_SND_HDA_PATCH_LOADER */ |
1612 | 1613 | ||
1613 | #ifndef CONFIG_SND_HDA_I915 | 1614 | #ifndef CONFIG_SND_HDA_I915 |
1614 | if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) | 1615 | if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) |
1615 | dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n"); | 1616 | dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n"); |
1616 | #endif | 1617 | #endif |
1617 | 1618 | ||
1618 | if (schedule_probe) | 1619 | if (schedule_probe) |
1619 | schedule_work(&chip->probe_work); | 1620 | schedule_work(&chip->probe_work); |
1620 | 1621 | ||
1621 | dev++; | 1622 | dev++; |
1622 | if (chip->disabled) | 1623 | if (chip->disabled) |
1623 | complete_all(&chip->probe_wait); | 1624 | complete_all(&chip->probe_wait); |
1624 | return 0; | 1625 | return 0; |
1625 | 1626 | ||
1626 | out_free: | 1627 | out_free: |
1627 | snd_card_free(card); | 1628 | snd_card_free(card); |
1628 | return err; | 1629 | return err; |
1629 | } | 1630 | } |
1630 | 1631 | ||
1631 | /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ | 1632 | /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ |
1632 | static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { | 1633 | static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { |
1633 | [AZX_DRIVER_NVIDIA] = 8, | 1634 | [AZX_DRIVER_NVIDIA] = 8, |
1634 | [AZX_DRIVER_TERA] = 1, | 1635 | [AZX_DRIVER_TERA] = 1, |
1635 | }; | 1636 | }; |
1636 | 1637 | ||
1637 | static int azx_probe_continue(struct azx *chip) | 1638 | static int azx_probe_continue(struct azx *chip) |
1638 | { | 1639 | { |
1639 | struct pci_dev *pci = chip->pci; | 1640 | struct pci_dev *pci = chip->pci; |
1640 | int dev = chip->dev_index; | 1641 | int dev = chip->dev_index; |
1641 | int err; | 1642 | int err; |
1642 | 1643 | ||
1643 | /* Request power well for Haswell HDA controller and codec */ | 1644 | /* Request power well for Haswell HDA controller and codec */ |
1644 | if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { | 1645 | if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { |
1645 | #ifdef CONFIG_SND_HDA_I915 | 1646 | #ifdef CONFIG_SND_HDA_I915 |
1646 | err = hda_i915_init(); | 1647 | err = hda_i915_init(); |
1647 | if (err < 0) { | 1648 | if (err < 0) { |
1648 | dev_err(chip->card->dev, | 1649 | dev_err(chip->card->dev, |
1649 | "Error request power-well from i915\n"); | 1650 | "Error request power-well from i915\n"); |
1650 | goto out_free; | 1651 | goto out_free; |
1651 | } | 1652 | } |
1652 | #endif | 1653 | #endif |
1653 | hda_display_power(true); | 1654 | hda_display_power(true); |
1654 | } | 1655 | } |
1655 | 1656 | ||
1656 | err = azx_first_init(chip); | 1657 | err = azx_first_init(chip); |
1657 | if (err < 0) | 1658 | if (err < 0) |
1658 | goto out_free; | 1659 | goto out_free; |
1659 | 1660 | ||
1660 | #ifdef CONFIG_SND_HDA_INPUT_BEEP | 1661 | #ifdef CONFIG_SND_HDA_INPUT_BEEP |
1661 | chip->beep_mode = beep_mode[dev]; | 1662 | chip->beep_mode = beep_mode[dev]; |
1662 | #endif | 1663 | #endif |
1663 | 1664 | ||
1664 | /* create codec instances */ | 1665 | /* create codec instances */ |
1665 | err = azx_codec_create(chip, model[dev], | 1666 | err = azx_codec_create(chip, model[dev], |
1666 | azx_max_codecs[chip->driver_type], | 1667 | azx_max_codecs[chip->driver_type], |
1667 | power_save_addr); | 1668 | power_save_addr); |
1668 | 1669 | ||
1669 | if (err < 0) | 1670 | if (err < 0) |
1670 | goto out_free; | 1671 | goto out_free; |
1671 | #ifdef CONFIG_SND_HDA_PATCH_LOADER | 1672 | #ifdef CONFIG_SND_HDA_PATCH_LOADER |
1672 | if (chip->fw) { | 1673 | if (chip->fw) { |
1673 | err = snd_hda_load_patch(chip->bus, chip->fw->size, | 1674 | err = snd_hda_load_patch(chip->bus, chip->fw->size, |
1674 | chip->fw->data); | 1675 | chip->fw->data); |
1675 | if (err < 0) | 1676 | if (err < 0) |
1676 | goto out_free; | 1677 | goto out_free; |
1677 | #ifndef CONFIG_PM | 1678 | #ifndef CONFIG_PM |
1678 | release_firmware(chip->fw); /* no longer needed */ | 1679 | release_firmware(chip->fw); /* no longer needed */ |
1679 | chip->fw = NULL; | 1680 | chip->fw = NULL; |
1680 | #endif | 1681 | #endif |
1681 | } | 1682 | } |
1682 | #endif | 1683 | #endif |
1683 | if ((probe_only[dev] & 1) == 0) { | 1684 | if ((probe_only[dev] & 1) == 0) { |
1684 | err = azx_codec_configure(chip); | 1685 | err = azx_codec_configure(chip); |
1685 | if (err < 0) | 1686 | if (err < 0) |
1686 | goto out_free; | 1687 | goto out_free; |
1687 | } | 1688 | } |
1688 | 1689 | ||
1689 | /* create PCM streams */ | 1690 | /* create PCM streams */ |
1690 | err = snd_hda_build_pcms(chip->bus); | 1691 | err = snd_hda_build_pcms(chip->bus); |
1691 | if (err < 0) | 1692 | if (err < 0) |
1692 | goto out_free; | 1693 | goto out_free; |
1693 | 1694 | ||
1694 | /* create mixer controls */ | 1695 | /* create mixer controls */ |
1695 | err = azx_mixer_create(chip); | 1696 | err = azx_mixer_create(chip); |
1696 | if (err < 0) | 1697 | if (err < 0) |
1697 | goto out_free; | 1698 | goto out_free; |
1698 | 1699 | ||
1699 | err = snd_card_register(chip->card); | 1700 | err = snd_card_register(chip->card); |
1700 | if (err < 0) | 1701 | if (err < 0) |
1701 | goto out_free; | 1702 | goto out_free; |
1702 | 1703 | ||
1703 | chip->running = 1; | 1704 | chip->running = 1; |
1704 | power_down_all_codecs(chip); | 1705 | power_down_all_codecs(chip); |
1705 | azx_notifier_register(chip); | 1706 | azx_notifier_register(chip); |
1706 | azx_add_card_list(chip); | 1707 | azx_add_card_list(chip); |
1707 | if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || chip->use_vga_switcheroo) | 1708 | if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || chip->use_vga_switcheroo) |
1708 | pm_runtime_put_noidle(&pci->dev); | 1709 | pm_runtime_put_noidle(&pci->dev); |
1709 | 1710 | ||
1710 | out_free: | 1711 | out_free: |
1711 | if (err < 0) | 1712 | if (err < 0) |
1712 | chip->init_failed = 1; | 1713 | chip->init_failed = 1; |
1713 | complete_all(&chip->probe_wait); | 1714 | complete_all(&chip->probe_wait); |
1714 | return err; | 1715 | return err; |
1715 | } | 1716 | } |
1716 | 1717 | ||
1717 | static void azx_remove(struct pci_dev *pci) | 1718 | static void azx_remove(struct pci_dev *pci) |
1718 | { | 1719 | { |
1719 | struct snd_card *card = pci_get_drvdata(pci); | 1720 | struct snd_card *card = pci_get_drvdata(pci); |
1720 | 1721 | ||
1721 | if (card) | 1722 | if (card) |
1722 | snd_card_free(card); | 1723 | snd_card_free(card); |
1723 | } | 1724 | } |
1724 | 1725 | ||
1725 | /* PCI IDs */ | 1726 | /* PCI IDs */ |
1726 | static DEFINE_PCI_DEVICE_TABLE(azx_ids) = { | 1727 | static DEFINE_PCI_DEVICE_TABLE(azx_ids) = { |
1727 | /* CPT */ | 1728 | /* CPT */ |
1728 | { PCI_DEVICE(0x8086, 0x1c20), | 1729 | { PCI_DEVICE(0x8086, 0x1c20), |
1729 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, | 1730 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, |
1730 | /* PBG */ | 1731 | /* PBG */ |
1731 | { PCI_DEVICE(0x8086, 0x1d20), | 1732 | { PCI_DEVICE(0x8086, 0x1d20), |
1732 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, | 1733 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, |
1733 | /* Panther Point */ | 1734 | /* Panther Point */ |
1734 | { PCI_DEVICE(0x8086, 0x1e20), | 1735 | { PCI_DEVICE(0x8086, 0x1e20), |
1735 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, | 1736 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, |
1736 | /* Lynx Point */ | 1737 | /* Lynx Point */ |
1737 | { PCI_DEVICE(0x8086, 0x8c20), | 1738 | { PCI_DEVICE(0x8086, 0x8c20), |
1738 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, | 1739 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, |
1739 | /* Wellsburg */ | 1740 | /* Wellsburg */ |
1740 | { PCI_DEVICE(0x8086, 0x8d20), | 1741 | { PCI_DEVICE(0x8086, 0x8d20), |
1741 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, | 1742 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, |
1742 | { PCI_DEVICE(0x8086, 0x8d21), | 1743 | { PCI_DEVICE(0x8086, 0x8d21), |
1743 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, | 1744 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, |
1744 | /* Lynx Point-LP */ | 1745 | /* Lynx Point-LP */ |
1745 | { PCI_DEVICE(0x8086, 0x9c20), | 1746 | { PCI_DEVICE(0x8086, 0x9c20), |
1746 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, | 1747 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, |
1747 | /* Lynx Point-LP */ | 1748 | /* Lynx Point-LP */ |
1748 | { PCI_DEVICE(0x8086, 0x9c21), | 1749 | { PCI_DEVICE(0x8086, 0x9c21), |
1749 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, | 1750 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, |
1750 | /* Wildcat Point-LP */ | 1751 | /* Wildcat Point-LP */ |
1751 | { PCI_DEVICE(0x8086, 0x9ca0), | 1752 | { PCI_DEVICE(0x8086, 0x9ca0), |
1752 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, | 1753 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, |
1753 | /* Haswell */ | 1754 | /* Haswell */ |
1754 | { PCI_DEVICE(0x8086, 0x0a0c), | 1755 | { PCI_DEVICE(0x8086, 0x0a0c), |
1755 | .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, | 1756 | .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, |
1756 | { PCI_DEVICE(0x8086, 0x0c0c), | 1757 | { PCI_DEVICE(0x8086, 0x0c0c), |
1757 | .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, | 1758 | .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, |
1758 | { PCI_DEVICE(0x8086, 0x0d0c), | 1759 | { PCI_DEVICE(0x8086, 0x0d0c), |
1759 | .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, | 1760 | .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, |
1760 | /* Broadwell */ | 1761 | /* Broadwell */ |
1761 | { PCI_DEVICE(0x8086, 0x160c), | 1762 | { PCI_DEVICE(0x8086, 0x160c), |
1762 | .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, | 1763 | .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, |
1763 | /* 5 Series/3400 */ | 1764 | /* 5 Series/3400 */ |
1764 | { PCI_DEVICE(0x8086, 0x3b56), | 1765 | { PCI_DEVICE(0x8086, 0x3b56), |
1765 | .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, | 1766 | .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, |
1766 | /* Poulsbo */ | 1767 | /* Poulsbo */ |
1767 | { PCI_DEVICE(0x8086, 0x811b), | 1768 | { PCI_DEVICE(0x8086, 0x811b), |
1768 | .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, | 1769 | .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, |
1769 | /* Oaktrail */ | 1770 | /* Oaktrail */ |
1770 | { PCI_DEVICE(0x8086, 0x080a), | 1771 | { PCI_DEVICE(0x8086, 0x080a), |
1771 | .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, | 1772 | .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, |
1772 | /* BayTrail */ | 1773 | /* BayTrail */ |
1773 | { PCI_DEVICE(0x8086, 0x0f04), | 1774 | { PCI_DEVICE(0x8086, 0x0f04), |
1774 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, | 1775 | .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, |
1775 | /* ICH */ | 1776 | /* ICH */ |
1776 | { PCI_DEVICE(0x8086, 0x2668), | 1777 | { PCI_DEVICE(0x8086, 0x2668), |
1777 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | | 1778 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | |
1778 | AZX_DCAPS_BUFSIZE }, /* ICH6 */ | 1779 | AZX_DCAPS_BUFSIZE }, /* ICH6 */ |
1779 | { PCI_DEVICE(0x8086, 0x27d8), | 1780 | { PCI_DEVICE(0x8086, 0x27d8), |
1780 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | | 1781 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | |
1781 | AZX_DCAPS_BUFSIZE }, /* ICH7 */ | 1782 | AZX_DCAPS_BUFSIZE }, /* ICH7 */ |
1782 | { PCI_DEVICE(0x8086, 0x269a), | 1783 | { PCI_DEVICE(0x8086, 0x269a), |
1783 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | | 1784 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | |
1784 | AZX_DCAPS_BUFSIZE }, /* ESB2 */ | 1785 | AZX_DCAPS_BUFSIZE }, /* ESB2 */ |
1785 | { PCI_DEVICE(0x8086, 0x284b), | 1786 | { PCI_DEVICE(0x8086, 0x284b), |
1786 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | | 1787 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | |
1787 | AZX_DCAPS_BUFSIZE }, /* ICH8 */ | 1788 | AZX_DCAPS_BUFSIZE }, /* ICH8 */ |
1788 | { PCI_DEVICE(0x8086, 0x293e), | 1789 | { PCI_DEVICE(0x8086, 0x293e), |
1789 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | | 1790 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | |
1790 | AZX_DCAPS_BUFSIZE }, /* ICH9 */ | 1791 | AZX_DCAPS_BUFSIZE }, /* ICH9 */ |
1791 | { PCI_DEVICE(0x8086, 0x293f), | 1792 | { PCI_DEVICE(0x8086, 0x293f), |
1792 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | | 1793 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | |
1793 | AZX_DCAPS_BUFSIZE }, /* ICH9 */ | 1794 | AZX_DCAPS_BUFSIZE }, /* ICH9 */ |
1794 | { PCI_DEVICE(0x8086, 0x3a3e), | 1795 | { PCI_DEVICE(0x8086, 0x3a3e), |
1795 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | | 1796 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | |
1796 | AZX_DCAPS_BUFSIZE }, /* ICH10 */ | 1797 | AZX_DCAPS_BUFSIZE }, /* ICH10 */ |
1797 | { PCI_DEVICE(0x8086, 0x3a6e), | 1798 | { PCI_DEVICE(0x8086, 0x3a6e), |
1798 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | | 1799 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | |
1799 | AZX_DCAPS_BUFSIZE }, /* ICH10 */ | 1800 | AZX_DCAPS_BUFSIZE }, /* ICH10 */ |
1800 | /* Generic Intel */ | 1801 | /* Generic Intel */ |
1801 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), | 1802 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), |
1802 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, | 1803 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, |
1803 | .class_mask = 0xffffff, | 1804 | .class_mask = 0xffffff, |
1804 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE }, | 1805 | .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE }, |
1805 | /* ATI SB 450/600/700/800/900 */ | 1806 | /* ATI SB 450/600/700/800/900 */ |
1806 | { PCI_DEVICE(0x1002, 0x437b), | 1807 | { PCI_DEVICE(0x1002, 0x437b), |
1807 | .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, | 1808 | .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, |
1808 | { PCI_DEVICE(0x1002, 0x4383), | 1809 | { PCI_DEVICE(0x1002, 0x4383), |
1809 | .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, | 1810 | .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, |
1810 | /* AMD Hudson */ | 1811 | /* AMD Hudson */ |
1811 | { PCI_DEVICE(0x1022, 0x780d), | 1812 | { PCI_DEVICE(0x1022, 0x780d), |
1812 | .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, | 1813 | .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, |
1813 | /* ATI HDMI */ | 1814 | /* ATI HDMI */ |
1814 | { PCI_DEVICE(0x1002, 0x793b), | 1815 | { PCI_DEVICE(0x1002, 0x793b), |
1815 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | 1816 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
1816 | { PCI_DEVICE(0x1002, 0x7919), | 1817 | { PCI_DEVICE(0x1002, 0x7919), |
1817 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | 1818 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
1818 | { PCI_DEVICE(0x1002, 0x960f), | 1819 | { PCI_DEVICE(0x1002, 0x960f), |
1819 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | 1820 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
1820 | { PCI_DEVICE(0x1002, 0x970f), | 1821 | { PCI_DEVICE(0x1002, 0x970f), |
1821 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | 1822 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
1822 | { PCI_DEVICE(0x1002, 0xaa00), | 1823 | { PCI_DEVICE(0x1002, 0xaa00), |
1823 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | 1824 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
1824 | { PCI_DEVICE(0x1002, 0xaa08), | 1825 | { PCI_DEVICE(0x1002, 0xaa08), |
1825 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | 1826 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
1826 | { PCI_DEVICE(0x1002, 0xaa10), | 1827 | { PCI_DEVICE(0x1002, 0xaa10), |
1827 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | 1828 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
1828 | { PCI_DEVICE(0x1002, 0xaa18), | 1829 | { PCI_DEVICE(0x1002, 0xaa18), |
1829 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | 1830 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
1830 | { PCI_DEVICE(0x1002, 0xaa20), | 1831 | { PCI_DEVICE(0x1002, 0xaa20), |
1831 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | 1832 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
1832 | { PCI_DEVICE(0x1002, 0xaa28), | 1833 | { PCI_DEVICE(0x1002, 0xaa28), |
1833 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | 1834 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
1834 | { PCI_DEVICE(0x1002, 0xaa30), | 1835 | { PCI_DEVICE(0x1002, 0xaa30), |
1835 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | 1836 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
1836 | { PCI_DEVICE(0x1002, 0xaa38), | 1837 | { PCI_DEVICE(0x1002, 0xaa38), |
1837 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | 1838 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
1838 | { PCI_DEVICE(0x1002, 0xaa40), | 1839 | { PCI_DEVICE(0x1002, 0xaa40), |
1839 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | 1840 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
1840 | { PCI_DEVICE(0x1002, 0xaa48), | 1841 | { PCI_DEVICE(0x1002, 0xaa48), |
1841 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | 1842 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
1842 | { PCI_DEVICE(0x1002, 0xaa50), | 1843 | { PCI_DEVICE(0x1002, 0xaa50), |
1843 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | 1844 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
1844 | { PCI_DEVICE(0x1002, 0xaa58), | 1845 | { PCI_DEVICE(0x1002, 0xaa58), |
1845 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | 1846 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
1846 | { PCI_DEVICE(0x1002, 0xaa60), | 1847 | { PCI_DEVICE(0x1002, 0xaa60), |
1847 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | 1848 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
1848 | { PCI_DEVICE(0x1002, 0xaa68), | 1849 | { PCI_DEVICE(0x1002, 0xaa68), |
1849 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | 1850 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
1850 | { PCI_DEVICE(0x1002, 0xaa80), | 1851 | { PCI_DEVICE(0x1002, 0xaa80), |
1851 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | 1852 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
1852 | { PCI_DEVICE(0x1002, 0xaa88), | 1853 | { PCI_DEVICE(0x1002, 0xaa88), |
1853 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | 1854 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
1854 | { PCI_DEVICE(0x1002, 0xaa90), | 1855 | { PCI_DEVICE(0x1002, 0xaa90), |
1855 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | 1856 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
1856 | { PCI_DEVICE(0x1002, 0xaa98), | 1857 | { PCI_DEVICE(0x1002, 0xaa98), |
1857 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, | 1858 | .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, |
1858 | { PCI_DEVICE(0x1002, 0x9902), | 1859 | { PCI_DEVICE(0x1002, 0x9902), |
1859 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI }, | 1860 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI }, |
1860 | { PCI_DEVICE(0x1002, 0xaaa0), | 1861 | { PCI_DEVICE(0x1002, 0xaaa0), |
1861 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI }, | 1862 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI }, |
1862 | { PCI_DEVICE(0x1002, 0xaaa8), | 1863 | { PCI_DEVICE(0x1002, 0xaaa8), |
1863 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI }, | 1864 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI }, |
1864 | { PCI_DEVICE(0x1002, 0xaab0), | 1865 | { PCI_DEVICE(0x1002, 0xaab0), |
1865 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI }, | 1866 | .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI }, |
1866 | /* VIA VT8251/VT8237A */ | 1867 | /* VIA VT8251/VT8237A */ |
1867 | { PCI_DEVICE(0x1106, 0x3288), | 1868 | { PCI_DEVICE(0x1106, 0x3288), |
1868 | .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA }, | 1869 | .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA }, |
1869 | /* VIA GFX VT7122/VX900 */ | 1870 | /* VIA GFX VT7122/VX900 */ |
1870 | { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, | 1871 | { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, |
1871 | /* VIA GFX VT6122/VX11 */ | 1872 | /* VIA GFX VT6122/VX11 */ |
1872 | { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, | 1873 | { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, |
1873 | /* SIS966 */ | 1874 | /* SIS966 */ |
1874 | { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, | 1875 | { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, |
1875 | /* ULI M5461 */ | 1876 | /* ULI M5461 */ |
1876 | { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, | 1877 | { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, |
1877 | /* NVIDIA MCP */ | 1878 | /* NVIDIA MCP */ |
1878 | { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), | 1879 | { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), |
1879 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, | 1880 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, |
1880 | .class_mask = 0xffffff, | 1881 | .class_mask = 0xffffff, |
1881 | .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, | 1882 | .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, |
1882 | /* Teradici */ | 1883 | /* Teradici */ |
1883 | { PCI_DEVICE(0x6549, 0x1200), | 1884 | { PCI_DEVICE(0x6549, 0x1200), |
1884 | .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, | 1885 | .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, |
1885 | { PCI_DEVICE(0x6549, 0x2200), | 1886 | { PCI_DEVICE(0x6549, 0x2200), |
1886 | .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, | 1887 | .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, |
1887 | /* Creative X-Fi (CA0110-IBG) */ | 1888 | /* Creative X-Fi (CA0110-IBG) */ |
1888 | /* CTHDA chips */ | 1889 | /* CTHDA chips */ |
1889 | { PCI_DEVICE(0x1102, 0x0010), | 1890 | { PCI_DEVICE(0x1102, 0x0010), |
1890 | .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, | 1891 | .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, |
1891 | { PCI_DEVICE(0x1102, 0x0012), | 1892 | { PCI_DEVICE(0x1102, 0x0012), |
1892 | .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, | 1893 | .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, |
1893 | #if !IS_ENABLED(CONFIG_SND_CTXFI) | 1894 | #if !IS_ENABLED(CONFIG_SND_CTXFI) |
1894 | /* the following entry conflicts with snd-ctxfi driver, | 1895 | /* the following entry conflicts with snd-ctxfi driver, |
1895 | * as ctxfi driver mutates from HD-audio to native mode with | 1896 | * as ctxfi driver mutates from HD-audio to native mode with |
1896 | * a special command sequence. | 1897 | * a special command sequence. |
1897 | */ | 1898 | */ |
1898 | { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), | 1899 | { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), |
1899 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, | 1900 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, |
1900 | .class_mask = 0xffffff, | 1901 | .class_mask = 0xffffff, |
1901 | .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | | 1902 | .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | |
1902 | AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB }, | 1903 | AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB }, |
1903 | #else | 1904 | #else |
1904 | /* this entry seems still valid -- i.e. without emu20kx chip */ | 1905 | /* this entry seems still valid -- i.e. without emu20kx chip */ |
1905 | { PCI_DEVICE(0x1102, 0x0009), | 1906 | { PCI_DEVICE(0x1102, 0x0009), |
1906 | .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | | 1907 | .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | |
1907 | AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB }, | 1908 | AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB }, |
1908 | #endif | 1909 | #endif |
1909 | /* Vortex86MX */ | 1910 | /* Vortex86MX */ |
1910 | { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, | 1911 | { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, |
1911 | /* VMware HDAudio */ | 1912 | /* VMware HDAudio */ |
1912 | { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, | 1913 | { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, |
1913 | /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ | 1914 | /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ |
1914 | { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), | 1915 | { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), |
1915 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, | 1916 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, |
1916 | .class_mask = 0xffffff, | 1917 | .class_mask = 0xffffff, |
1917 | .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, | 1918 | .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, |
1918 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), | 1919 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), |
1919 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, | 1920 | .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, |
1920 | .class_mask = 0xffffff, | 1921 | .class_mask = 0xffffff, |
1921 | .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, | 1922 | .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, |
1922 | { 0, } | 1923 | { 0, } |
1923 | }; | 1924 | }; |
1924 | MODULE_DEVICE_TABLE(pci, azx_ids); | 1925 | MODULE_DEVICE_TABLE(pci, azx_ids); |
1925 | 1926 | ||
1926 | /* pci_driver definition */ | 1927 | /* pci_driver definition */ |
1927 | static struct pci_driver azx_driver = { | 1928 | static struct pci_driver azx_driver = { |
1928 | .name = KBUILD_MODNAME, | 1929 | .name = KBUILD_MODNAME, |
1929 | .id_table = azx_ids, | 1930 | .id_table = azx_ids, |
1930 | .probe = azx_probe, | 1931 | .probe = azx_probe, |
1931 | .remove = azx_remove, | 1932 | .remove = azx_remove, |
1932 | .driver = { | 1933 | .driver = { |
1933 | .pm = AZX_PM_OPS, | 1934 | .pm = AZX_PM_OPS, |
1934 | }, | 1935 | }, |
1935 | }; | 1936 | }; |
1936 | 1937 | ||
1937 | module_pci_driver(azx_driver); | 1938 | module_pci_driver(azx_driver); |
1938 | 1939 |
sound/pci/hda/hda_priv.h
1 | /* | 1 | /* |
2 | * Common defines for the alsa driver code base for HD Audio. | 2 | * Common defines for the alsa driver code base for HD Audio. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms of the GNU General Public License as published by the Free | 5 | * under the terms of the GNU General Public License as published by the Free |
6 | * Software Foundation; either version 2 of the License, or (at your option) | 6 | * Software Foundation; either version 2 of the License, or (at your option) |
7 | * any later version. | 7 | * any later version. |
8 | * | 8 | * |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | 9 | * This program is distributed in the hope that it will be useful, but WITHOUT |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
12 | * more details. | 12 | * more details. |
13 | */ | 13 | */ |
14 | 14 | ||
15 | #ifndef __SOUND_HDA_PRIV_H | 15 | #ifndef __SOUND_HDA_PRIV_H |
16 | #define __SOUND_HDA_PRIV_H | 16 | #define __SOUND_HDA_PRIV_H |
17 | 17 | ||
18 | #include <linux/clocksource.h> | 18 | #include <linux/clocksource.h> |
19 | #include <sound/core.h> | 19 | #include <sound/core.h> |
20 | #include <sound/pcm.h> | 20 | #include <sound/pcm.h> |
21 | 21 | ||
22 | /* | 22 | /* |
23 | * registers | 23 | * registers |
24 | */ | 24 | */ |
25 | #define ICH6_REG_GCAP 0x00 | 25 | #define ICH6_REG_GCAP 0x00 |
26 | #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */ | 26 | #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */ |
27 | #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */ | 27 | #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */ |
28 | #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */ | 28 | #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */ |
29 | #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */ | 29 | #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */ |
30 | #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */ | 30 | #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */ |
31 | #define ICH6_REG_VMIN 0x02 | 31 | #define ICH6_REG_VMIN 0x02 |
32 | #define ICH6_REG_VMAJ 0x03 | 32 | #define ICH6_REG_VMAJ 0x03 |
33 | #define ICH6_REG_OUTPAY 0x04 | 33 | #define ICH6_REG_OUTPAY 0x04 |
34 | #define ICH6_REG_INPAY 0x06 | 34 | #define ICH6_REG_INPAY 0x06 |
35 | #define ICH6_REG_GCTL 0x08 | 35 | #define ICH6_REG_GCTL 0x08 |
36 | #define ICH6_GCTL_RESET (1 << 0) /* controller reset */ | 36 | #define ICH6_GCTL_RESET (1 << 0) /* controller reset */ |
37 | #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */ | 37 | #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */ |
38 | #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */ | 38 | #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */ |
39 | #define ICH6_REG_WAKEEN 0x0c | 39 | #define ICH6_REG_WAKEEN 0x0c |
40 | #define ICH6_REG_STATESTS 0x0e | 40 | #define ICH6_REG_STATESTS 0x0e |
41 | #define ICH6_REG_GSTS 0x10 | 41 | #define ICH6_REG_GSTS 0x10 |
42 | #define ICH6_GSTS_FSTS (1 << 1) /* flush status */ | 42 | #define ICH6_GSTS_FSTS (1 << 1) /* flush status */ |
43 | #define ICH6_REG_INTCTL 0x20 | 43 | #define ICH6_REG_INTCTL 0x20 |
44 | #define ICH6_REG_INTSTS 0x24 | 44 | #define ICH6_REG_INTSTS 0x24 |
45 | #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */ | 45 | #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */ |
46 | #define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */ | 46 | #define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */ |
47 | #define ICH6_REG_SSYNC 0x38 | 47 | #define ICH6_REG_SSYNC 0x38 |
48 | #define ICH6_REG_CORBLBASE 0x40 | 48 | #define ICH6_REG_CORBLBASE 0x40 |
49 | #define ICH6_REG_CORBUBASE 0x44 | 49 | #define ICH6_REG_CORBUBASE 0x44 |
50 | #define ICH6_REG_CORBWP 0x48 | 50 | #define ICH6_REG_CORBWP 0x48 |
51 | #define ICH6_REG_CORBRP 0x4a | 51 | #define ICH6_REG_CORBRP 0x4a |
52 | #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */ | 52 | #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */ |
53 | #define ICH6_REG_CORBCTL 0x4c | 53 | #define ICH6_REG_CORBCTL 0x4c |
54 | #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */ | 54 | #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */ |
55 | #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */ | 55 | #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */ |
56 | #define ICH6_REG_CORBSTS 0x4d | 56 | #define ICH6_REG_CORBSTS 0x4d |
57 | #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */ | 57 | #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */ |
58 | #define ICH6_REG_CORBSIZE 0x4e | 58 | #define ICH6_REG_CORBSIZE 0x4e |
59 | 59 | ||
60 | #define ICH6_REG_RIRBLBASE 0x50 | 60 | #define ICH6_REG_RIRBLBASE 0x50 |
61 | #define ICH6_REG_RIRBUBASE 0x54 | 61 | #define ICH6_REG_RIRBUBASE 0x54 |
62 | #define ICH6_REG_RIRBWP 0x58 | 62 | #define ICH6_REG_RIRBWP 0x58 |
63 | #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */ | 63 | #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */ |
64 | #define ICH6_REG_RINTCNT 0x5a | 64 | #define ICH6_REG_RINTCNT 0x5a |
65 | #define ICH6_REG_RIRBCTL 0x5c | 65 | #define ICH6_REG_RIRBCTL 0x5c |
66 | #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */ | 66 | #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */ |
67 | #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */ | 67 | #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */ |
68 | #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */ | 68 | #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */ |
69 | #define ICH6_REG_RIRBSTS 0x5d | 69 | #define ICH6_REG_RIRBSTS 0x5d |
70 | #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */ | 70 | #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */ |
71 | #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */ | 71 | #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */ |
72 | #define ICH6_REG_RIRBSIZE 0x5e | 72 | #define ICH6_REG_RIRBSIZE 0x5e |
73 | 73 | ||
74 | #define ICH6_REG_IC 0x60 | 74 | #define ICH6_REG_IC 0x60 |
75 | #define ICH6_REG_IR 0x64 | 75 | #define ICH6_REG_IR 0x64 |
76 | #define ICH6_REG_IRS 0x68 | 76 | #define ICH6_REG_IRS 0x68 |
77 | #define ICH6_IRS_VALID (1<<1) | 77 | #define ICH6_IRS_VALID (1<<1) |
78 | #define ICH6_IRS_BUSY (1<<0) | 78 | #define ICH6_IRS_BUSY (1<<0) |
79 | 79 | ||
80 | #define ICH6_REG_DPLBASE 0x70 | 80 | #define ICH6_REG_DPLBASE 0x70 |
81 | #define ICH6_REG_DPUBASE 0x74 | 81 | #define ICH6_REG_DPUBASE 0x74 |
82 | #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */ | 82 | #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */ |
83 | 83 | ||
84 | /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ | 84 | /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ |
85 | enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; | 85 | enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; |
86 | 86 | ||
87 | /* stream register offsets from stream base */ | 87 | /* stream register offsets from stream base */ |
88 | #define ICH6_REG_SD_CTL 0x00 | 88 | #define ICH6_REG_SD_CTL 0x00 |
89 | #define ICH6_REG_SD_STS 0x03 | 89 | #define ICH6_REG_SD_STS 0x03 |
90 | #define ICH6_REG_SD_LPIB 0x04 | 90 | #define ICH6_REG_SD_LPIB 0x04 |
91 | #define ICH6_REG_SD_CBL 0x08 | 91 | #define ICH6_REG_SD_CBL 0x08 |
92 | #define ICH6_REG_SD_LVI 0x0c | 92 | #define ICH6_REG_SD_LVI 0x0c |
93 | #define ICH6_REG_SD_FIFOW 0x0e | 93 | #define ICH6_REG_SD_FIFOW 0x0e |
94 | #define ICH6_REG_SD_FIFOSIZE 0x10 | 94 | #define ICH6_REG_SD_FIFOSIZE 0x10 |
95 | #define ICH6_REG_SD_FORMAT 0x12 | 95 | #define ICH6_REG_SD_FORMAT 0x12 |
96 | #define ICH6_REG_SD_BDLPL 0x18 | 96 | #define ICH6_REG_SD_BDLPL 0x18 |
97 | #define ICH6_REG_SD_BDLPU 0x1c | 97 | #define ICH6_REG_SD_BDLPU 0x1c |
98 | 98 | ||
99 | /* PCI space */ | 99 | /* PCI space */ |
100 | #define ICH6_PCIREG_TCSEL 0x44 | 100 | #define ICH6_PCIREG_TCSEL 0x44 |
101 | 101 | ||
102 | /* | 102 | /* |
103 | * other constants | 103 | * other constants |
104 | */ | 104 | */ |
105 | 105 | ||
106 | /* max number of SDs */ | 106 | /* max number of SDs */ |
107 | /* ICH, ATI and VIA have 4 playback and 4 capture */ | 107 | /* ICH, ATI and VIA have 4 playback and 4 capture */ |
108 | #define ICH6_NUM_CAPTURE 4 | 108 | #define ICH6_NUM_CAPTURE 4 |
109 | #define ICH6_NUM_PLAYBACK 4 | 109 | #define ICH6_NUM_PLAYBACK 4 |
110 | 110 | ||
111 | /* ULI has 6 playback and 5 capture */ | 111 | /* ULI has 6 playback and 5 capture */ |
112 | #define ULI_NUM_CAPTURE 5 | 112 | #define ULI_NUM_CAPTURE 5 |
113 | #define ULI_NUM_PLAYBACK 6 | 113 | #define ULI_NUM_PLAYBACK 6 |
114 | 114 | ||
115 | /* ATI HDMI may have up to 8 playbacks and 0 capture */ | 115 | /* ATI HDMI may have up to 8 playbacks and 0 capture */ |
116 | #define ATIHDMI_NUM_CAPTURE 0 | 116 | #define ATIHDMI_NUM_CAPTURE 0 |
117 | #define ATIHDMI_NUM_PLAYBACK 8 | 117 | #define ATIHDMI_NUM_PLAYBACK 8 |
118 | 118 | ||
119 | /* TERA has 4 playback and 3 capture */ | 119 | /* TERA has 4 playback and 3 capture */ |
120 | #define TERA_NUM_CAPTURE 3 | 120 | #define TERA_NUM_CAPTURE 3 |
121 | #define TERA_NUM_PLAYBACK 4 | 121 | #define TERA_NUM_PLAYBACK 4 |
122 | 122 | ||
123 | /* this number is statically defined for simplicity */ | 123 | /* this number is statically defined for simplicity */ |
124 | #define MAX_AZX_DEV 16 | 124 | #define MAX_AZX_DEV 16 |
125 | 125 | ||
126 | /* max number of fragments - we may use more if allocating more pages for BDL */ | 126 | /* max number of fragments - we may use more if allocating more pages for BDL */ |
127 | #define BDL_SIZE 4096 | 127 | #define BDL_SIZE 4096 |
128 | #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16) | 128 | #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16) |
129 | #define AZX_MAX_FRAG 32 | 129 | #define AZX_MAX_FRAG 32 |
130 | /* max buffer size - no h/w limit, you can increase as you like */ | 130 | /* max buffer size - no h/w limit, you can increase as you like */ |
131 | #define AZX_MAX_BUF_SIZE (1024*1024*1024) | 131 | #define AZX_MAX_BUF_SIZE (1024*1024*1024) |
132 | 132 | ||
133 | /* RIRB int mask: overrun[2], response[0] */ | 133 | /* RIRB int mask: overrun[2], response[0] */ |
134 | #define RIRB_INT_RESPONSE 0x01 | 134 | #define RIRB_INT_RESPONSE 0x01 |
135 | #define RIRB_INT_OVERRUN 0x04 | 135 | #define RIRB_INT_OVERRUN 0x04 |
136 | #define RIRB_INT_MASK 0x05 | 136 | #define RIRB_INT_MASK 0x05 |
137 | 137 | ||
138 | /* STATESTS int mask: S3,SD2,SD1,SD0 */ | 138 | /* STATESTS int mask: S3,SD2,SD1,SD0 */ |
139 | #define AZX_MAX_CODECS 8 | 139 | #define AZX_MAX_CODECS 8 |
140 | #define AZX_DEFAULT_CODECS 4 | 140 | #define AZX_DEFAULT_CODECS 4 |
141 | #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1) | 141 | #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1) |
142 | 142 | ||
143 | /* SD_CTL bits */ | 143 | /* SD_CTL bits */ |
144 | #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */ | 144 | #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */ |
145 | #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */ | 145 | #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */ |
146 | #define SD_CTL_STRIPE (3 << 16) /* stripe control */ | 146 | #define SD_CTL_STRIPE (3 << 16) /* stripe control */ |
147 | #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */ | 147 | #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */ |
148 | #define SD_CTL_DIR (1 << 19) /* bi-directional stream */ | 148 | #define SD_CTL_DIR (1 << 19) /* bi-directional stream */ |
149 | #define SD_CTL_STREAM_TAG_MASK (0xf << 20) | 149 | #define SD_CTL_STREAM_TAG_MASK (0xf << 20) |
150 | #define SD_CTL_STREAM_TAG_SHIFT 20 | 150 | #define SD_CTL_STREAM_TAG_SHIFT 20 |
151 | 151 | ||
152 | /* SD_CTL and SD_STS */ | 152 | /* SD_CTL and SD_STS */ |
153 | #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */ | 153 | #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */ |
154 | #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */ | 154 | #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */ |
155 | #define SD_INT_COMPLETE 0x04 /* completion interrupt */ | 155 | #define SD_INT_COMPLETE 0x04 /* completion interrupt */ |
156 | #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\ | 156 | #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\ |
157 | SD_INT_COMPLETE) | 157 | SD_INT_COMPLETE) |
158 | 158 | ||
159 | /* SD_STS */ | 159 | /* SD_STS */ |
160 | #define SD_STS_FIFO_READY 0x20 /* FIFO ready */ | 160 | #define SD_STS_FIFO_READY 0x20 /* FIFO ready */ |
161 | 161 | ||
162 | /* INTCTL and INTSTS */ | 162 | /* INTCTL and INTSTS */ |
163 | #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */ | 163 | #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */ |
164 | #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */ | 164 | #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */ |
165 | #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */ | 165 | #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */ |
166 | 166 | ||
167 | /* below are so far hardcoded - should read registers in future */ | 167 | /* below are so far hardcoded - should read registers in future */ |
168 | #define ICH6_MAX_CORB_ENTRIES 256 | 168 | #define ICH6_MAX_CORB_ENTRIES 256 |
169 | #define ICH6_MAX_RIRB_ENTRIES 256 | 169 | #define ICH6_MAX_RIRB_ENTRIES 256 |
170 | 170 | ||
171 | /* driver quirks (capabilities) */ | 171 | /* driver quirks (capabilities) */ |
172 | /* bits 0-7 are used for indicating driver type */ | 172 | /* bits 0-7 are used for indicating driver type */ |
173 | #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */ | 173 | #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */ |
174 | #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */ | 174 | #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */ |
175 | #define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */ | 175 | #define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */ |
176 | #define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */ | 176 | #define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */ |
177 | #define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */ | 177 | #define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */ |
178 | #define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */ | 178 | #define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */ |
179 | #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */ | 179 | #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */ |
180 | #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */ | 180 | #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */ |
181 | #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */ | 181 | #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */ |
182 | #define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */ | 182 | #define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */ |
183 | #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */ | 183 | #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */ |
184 | #define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */ | 184 | #define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */ |
185 | #define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */ | 185 | #define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */ |
186 | #define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */ | 186 | #define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */ |
187 | #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */ | 187 | #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */ |
188 | #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */ | 188 | #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */ |
189 | #define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */ | 189 | #define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */ |
190 | #define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */ | 190 | #define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */ |
191 | #define AZX_DCAPS_I915_POWERWELL (1 << 27) /* HSW i915 powerwell support */ | 191 | #define AZX_DCAPS_I915_POWERWELL (1 << 27) /* HSW i915 powerwell support */ |
192 | #define AZX_DCAPS_CORBRP_SELF_CLEAR (1 << 28) /* CORBRP clears itself after reset */ | ||
192 | 193 | ||
193 | /* position fix mode */ | 194 | /* position fix mode */ |
194 | enum { | 195 | enum { |
195 | POS_FIX_AUTO, | 196 | POS_FIX_AUTO, |
196 | POS_FIX_LPIB, | 197 | POS_FIX_LPIB, |
197 | POS_FIX_POSBUF, | 198 | POS_FIX_POSBUF, |
198 | POS_FIX_VIACOMBO, | 199 | POS_FIX_VIACOMBO, |
199 | POS_FIX_COMBO, | 200 | POS_FIX_COMBO, |
200 | }; | 201 | }; |
201 | 202 | ||
202 | /* Defines for ATI HD Audio support in SB450 south bridge */ | 203 | /* Defines for ATI HD Audio support in SB450 south bridge */ |
203 | #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 | 204 | #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 |
204 | #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 | 205 | #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 |
205 | 206 | ||
206 | /* Defines for Nvidia HDA support */ | 207 | /* Defines for Nvidia HDA support */ |
207 | #define NVIDIA_HDA_TRANSREG_ADDR 0x4e | 208 | #define NVIDIA_HDA_TRANSREG_ADDR 0x4e |
208 | #define NVIDIA_HDA_ENABLE_COHBITS 0x0f | 209 | #define NVIDIA_HDA_ENABLE_COHBITS 0x0f |
209 | #define NVIDIA_HDA_ISTRM_COH 0x4d | 210 | #define NVIDIA_HDA_ISTRM_COH 0x4d |
210 | #define NVIDIA_HDA_OSTRM_COH 0x4c | 211 | #define NVIDIA_HDA_OSTRM_COH 0x4c |
211 | #define NVIDIA_HDA_ENABLE_COHBIT 0x01 | 212 | #define NVIDIA_HDA_ENABLE_COHBIT 0x01 |
212 | 213 | ||
213 | /* Defines for Intel SCH HDA snoop control */ | 214 | /* Defines for Intel SCH HDA snoop control */ |
214 | #define INTEL_SCH_HDA_DEVC 0x78 | 215 | #define INTEL_SCH_HDA_DEVC 0x78 |
215 | #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) | 216 | #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) |
216 | 217 | ||
217 | /* Define IN stream 0 FIFO size offset in VIA controller */ | 218 | /* Define IN stream 0 FIFO size offset in VIA controller */ |
218 | #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90 | 219 | #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90 |
219 | /* Define VIA HD Audio Device ID*/ | 220 | /* Define VIA HD Audio Device ID*/ |
220 | #define VIA_HDAC_DEVICE_ID 0x3288 | 221 | #define VIA_HDAC_DEVICE_ID 0x3288 |
221 | 222 | ||
222 | /* HD Audio class code */ | 223 | /* HD Audio class code */ |
223 | #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403 | 224 | #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403 |
224 | 225 | ||
225 | struct azx_dev { | 226 | struct azx_dev { |
226 | struct snd_dma_buffer bdl; /* BDL buffer */ | 227 | struct snd_dma_buffer bdl; /* BDL buffer */ |
227 | u32 *posbuf; /* position buffer pointer */ | 228 | u32 *posbuf; /* position buffer pointer */ |
228 | 229 | ||
229 | unsigned int bufsize; /* size of the play buffer in bytes */ | 230 | unsigned int bufsize; /* size of the play buffer in bytes */ |
230 | unsigned int period_bytes; /* size of the period in bytes */ | 231 | unsigned int period_bytes; /* size of the period in bytes */ |
231 | unsigned int frags; /* number for period in the play buffer */ | 232 | unsigned int frags; /* number for period in the play buffer */ |
232 | unsigned int fifo_size; /* FIFO size */ | 233 | unsigned int fifo_size; /* FIFO size */ |
233 | unsigned long start_wallclk; /* start + minimum wallclk */ | 234 | unsigned long start_wallclk; /* start + minimum wallclk */ |
234 | unsigned long period_wallclk; /* wallclk for period */ | 235 | unsigned long period_wallclk; /* wallclk for period */ |
235 | 236 | ||
236 | void __iomem *sd_addr; /* stream descriptor pointer */ | 237 | void __iomem *sd_addr; /* stream descriptor pointer */ |
237 | 238 | ||
238 | u32 sd_int_sta_mask; /* stream int status mask */ | 239 | u32 sd_int_sta_mask; /* stream int status mask */ |
239 | 240 | ||
240 | /* pcm support */ | 241 | /* pcm support */ |
241 | struct snd_pcm_substream *substream; /* assigned substream, | 242 | struct snd_pcm_substream *substream; /* assigned substream, |
242 | * set in PCM open | 243 | * set in PCM open |
243 | */ | 244 | */ |
244 | unsigned int format_val; /* format value to be set in the | 245 | unsigned int format_val; /* format value to be set in the |
245 | * controller and the codec | 246 | * controller and the codec |
246 | */ | 247 | */ |
247 | unsigned char stream_tag; /* assigned stream */ | 248 | unsigned char stream_tag; /* assigned stream */ |
248 | unsigned char index; /* stream index */ | 249 | unsigned char index; /* stream index */ |
249 | int assigned_key; /* last device# key assigned to */ | 250 | int assigned_key; /* last device# key assigned to */ |
250 | 251 | ||
251 | unsigned int opened:1; | 252 | unsigned int opened:1; |
252 | unsigned int running:1; | 253 | unsigned int running:1; |
253 | unsigned int irq_pending:1; | 254 | unsigned int irq_pending:1; |
254 | unsigned int prepared:1; | 255 | unsigned int prepared:1; |
255 | unsigned int locked:1; | 256 | unsigned int locked:1; |
256 | /* | 257 | /* |
257 | * For VIA: | 258 | * For VIA: |
258 | * A flag to ensure DMA position is 0 | 259 | * A flag to ensure DMA position is 0 |
259 | * when link position is not greater than FIFO size | 260 | * when link position is not greater than FIFO size |
260 | */ | 261 | */ |
261 | unsigned int insufficient:1; | 262 | unsigned int insufficient:1; |
262 | unsigned int wc_marked:1; | 263 | unsigned int wc_marked:1; |
263 | unsigned int no_period_wakeup:1; | 264 | unsigned int no_period_wakeup:1; |
264 | 265 | ||
265 | struct timecounter azx_tc; | 266 | struct timecounter azx_tc; |
266 | struct cyclecounter azx_cc; | 267 | struct cyclecounter azx_cc; |
267 | 268 | ||
268 | int delay_negative_threshold; | 269 | int delay_negative_threshold; |
269 | 270 | ||
270 | #ifdef CONFIG_SND_HDA_DSP_LOADER | 271 | #ifdef CONFIG_SND_HDA_DSP_LOADER |
271 | /* Allows dsp load to have sole access to the playback stream. */ | 272 | /* Allows dsp load to have sole access to the playback stream. */ |
272 | struct mutex dsp_mutex; | 273 | struct mutex dsp_mutex; |
273 | #endif | 274 | #endif |
274 | }; | 275 | }; |
275 | 276 | ||
276 | /* CORB/RIRB */ | 277 | /* CORB/RIRB */ |
277 | struct azx_rb { | 278 | struct azx_rb { |
278 | u32 *buf; /* CORB/RIRB buffer | 279 | u32 *buf; /* CORB/RIRB buffer |
279 | * Each CORB entry is 4byte, RIRB is 8byte | 280 | * Each CORB entry is 4byte, RIRB is 8byte |
280 | */ | 281 | */ |
281 | dma_addr_t addr; /* physical address of CORB/RIRB buffer */ | 282 | dma_addr_t addr; /* physical address of CORB/RIRB buffer */ |
282 | /* for RIRB */ | 283 | /* for RIRB */ |
283 | unsigned short rp, wp; /* read/write pointers */ | 284 | unsigned short rp, wp; /* read/write pointers */ |
284 | int cmds[AZX_MAX_CODECS]; /* number of pending requests */ | 285 | int cmds[AZX_MAX_CODECS]; /* number of pending requests */ |
285 | u32 res[AZX_MAX_CODECS]; /* last read value */ | 286 | u32 res[AZX_MAX_CODECS]; /* last read value */ |
286 | }; | 287 | }; |
287 | 288 | ||
288 | struct azx; | 289 | struct azx; |
289 | 290 | ||
290 | /* Functions to read/write to hda registers. */ | 291 | /* Functions to read/write to hda registers. */ |
291 | struct hda_controller_ops { | 292 | struct hda_controller_ops { |
292 | /* Register Access */ | 293 | /* Register Access */ |
293 | void (*reg_writel)(u32 value, u32 __iomem *addr); | 294 | void (*reg_writel)(u32 value, u32 __iomem *addr); |
294 | u32 (*reg_readl)(u32 __iomem *addr); | 295 | u32 (*reg_readl)(u32 __iomem *addr); |
295 | void (*reg_writew)(u16 value, u16 __iomem *addr); | 296 | void (*reg_writew)(u16 value, u16 __iomem *addr); |
296 | u16 (*reg_readw)(u16 __iomem *addr); | 297 | u16 (*reg_readw)(u16 __iomem *addr); |
297 | void (*reg_writeb)(u8 value, u8 __iomem *addr); | 298 | void (*reg_writeb)(u8 value, u8 __iomem *addr); |
298 | u8 (*reg_readb)(u8 __iomem *addr); | 299 | u8 (*reg_readb)(u8 __iomem *addr); |
299 | /* Disable msi if supported, PCI only */ | 300 | /* Disable msi if supported, PCI only */ |
300 | int (*disable_msi_reset_irq)(struct azx *); | 301 | int (*disable_msi_reset_irq)(struct azx *); |
301 | /* Allocation ops */ | 302 | /* Allocation ops */ |
302 | int (*dma_alloc_pages)(struct azx *chip, | 303 | int (*dma_alloc_pages)(struct azx *chip, |
303 | int type, | 304 | int type, |
304 | size_t size, | 305 | size_t size, |
305 | struct snd_dma_buffer *buf); | 306 | struct snd_dma_buffer *buf); |
306 | void (*dma_free_pages)(struct azx *chip, struct snd_dma_buffer *buf); | 307 | void (*dma_free_pages)(struct azx *chip, struct snd_dma_buffer *buf); |
307 | int (*substream_alloc_pages)(struct azx *chip, | 308 | int (*substream_alloc_pages)(struct azx *chip, |
308 | struct snd_pcm_substream *substream, | 309 | struct snd_pcm_substream *substream, |
309 | size_t size); | 310 | size_t size); |
310 | int (*substream_free_pages)(struct azx *chip, | 311 | int (*substream_free_pages)(struct azx *chip, |
311 | struct snd_pcm_substream *substream); | 312 | struct snd_pcm_substream *substream); |
312 | void (*pcm_mmap_prepare)(struct snd_pcm_substream *substream, | 313 | void (*pcm_mmap_prepare)(struct snd_pcm_substream *substream, |
313 | struct vm_area_struct *area); | 314 | struct vm_area_struct *area); |
314 | /* Check if current position is acceptable */ | 315 | /* Check if current position is acceptable */ |
315 | int (*position_check)(struct azx *chip, struct azx_dev *azx_dev); | 316 | int (*position_check)(struct azx *chip, struct azx_dev *azx_dev); |
316 | }; | 317 | }; |
317 | 318 | ||
318 | struct azx_pcm { | 319 | struct azx_pcm { |
319 | struct azx *chip; | 320 | struct azx *chip; |
320 | struct snd_pcm *pcm; | 321 | struct snd_pcm *pcm; |
321 | struct hda_codec *codec; | 322 | struct hda_codec *codec; |
322 | struct hda_pcm_stream *hinfo[2]; | 323 | struct hda_pcm_stream *hinfo[2]; |
323 | struct list_head list; | 324 | struct list_head list; |
324 | }; | 325 | }; |
325 | 326 | ||
326 | struct azx { | 327 | struct azx { |
327 | struct snd_card *card; | 328 | struct snd_card *card; |
328 | struct pci_dev *pci; | 329 | struct pci_dev *pci; |
329 | int dev_index; | 330 | int dev_index; |
330 | 331 | ||
331 | /* chip type specific */ | 332 | /* chip type specific */ |
332 | int driver_type; | 333 | int driver_type; |
333 | unsigned int driver_caps; | 334 | unsigned int driver_caps; |
334 | int playback_streams; | 335 | int playback_streams; |
335 | int playback_index_offset; | 336 | int playback_index_offset; |
336 | int capture_streams; | 337 | int capture_streams; |
337 | int capture_index_offset; | 338 | int capture_index_offset; |
338 | int num_streams; | 339 | int num_streams; |
339 | const int *jackpoll_ms; /* per-card jack poll interval */ | 340 | const int *jackpoll_ms; /* per-card jack poll interval */ |
340 | 341 | ||
341 | /* Register interaction. */ | 342 | /* Register interaction. */ |
342 | const struct hda_controller_ops *ops; | 343 | const struct hda_controller_ops *ops; |
343 | 344 | ||
344 | /* pci resources */ | 345 | /* pci resources */ |
345 | unsigned long addr; | 346 | unsigned long addr; |
346 | void __iomem *remap_addr; | 347 | void __iomem *remap_addr; |
347 | int irq; | 348 | int irq; |
348 | 349 | ||
349 | /* locks */ | 350 | /* locks */ |
350 | spinlock_t reg_lock; | 351 | spinlock_t reg_lock; |
351 | struct mutex open_mutex; /* Prevents concurrent open/close operations */ | 352 | struct mutex open_mutex; /* Prevents concurrent open/close operations */ |
352 | struct completion probe_wait; | 353 | struct completion probe_wait; |
353 | 354 | ||
354 | /* streams (x num_streams) */ | 355 | /* streams (x num_streams) */ |
355 | struct azx_dev *azx_dev; | 356 | struct azx_dev *azx_dev; |
356 | 357 | ||
357 | /* PCM */ | 358 | /* PCM */ |
358 | struct list_head pcm_list; /* azx_pcm list */ | 359 | struct list_head pcm_list; /* azx_pcm list */ |
359 | 360 | ||
360 | /* HD codec */ | 361 | /* HD codec */ |
361 | unsigned short codec_mask; | 362 | unsigned short codec_mask; |
362 | int codec_probe_mask; /* copied from probe_mask option */ | 363 | int codec_probe_mask; /* copied from probe_mask option */ |
363 | struct hda_bus *bus; | 364 | struct hda_bus *bus; |
364 | unsigned int beep_mode; | 365 | unsigned int beep_mode; |
365 | 366 | ||
366 | /* CORB/RIRB */ | 367 | /* CORB/RIRB */ |
367 | struct azx_rb corb; | 368 | struct azx_rb corb; |
368 | struct azx_rb rirb; | 369 | struct azx_rb rirb; |
369 | 370 | ||
370 | /* CORB/RIRB and position buffers */ | 371 | /* CORB/RIRB and position buffers */ |
371 | struct snd_dma_buffer rb; | 372 | struct snd_dma_buffer rb; |
372 | struct snd_dma_buffer posbuf; | 373 | struct snd_dma_buffer posbuf; |
373 | 374 | ||
374 | #ifdef CONFIG_SND_HDA_PATCH_LOADER | 375 | #ifdef CONFIG_SND_HDA_PATCH_LOADER |
375 | const struct firmware *fw; | 376 | const struct firmware *fw; |
376 | #endif | 377 | #endif |
377 | 378 | ||
378 | /* flags */ | 379 | /* flags */ |
379 | int position_fix[2]; /* for both playback/capture streams */ | 380 | int position_fix[2]; /* for both playback/capture streams */ |
380 | const int *bdl_pos_adj; | 381 | const int *bdl_pos_adj; |
381 | int poll_count; | 382 | int poll_count; |
382 | unsigned int running:1; | 383 | unsigned int running:1; |
383 | unsigned int initialized:1; | 384 | unsigned int initialized:1; |
384 | unsigned int single_cmd:1; | 385 | unsigned int single_cmd:1; |
385 | unsigned int polling_mode:1; | 386 | unsigned int polling_mode:1; |
386 | unsigned int msi:1; | 387 | unsigned int msi:1; |
387 | unsigned int irq_pending_warned:1; | 388 | unsigned int irq_pending_warned:1; |
388 | unsigned int probing:1; /* codec probing phase */ | 389 | unsigned int probing:1; /* codec probing phase */ |
389 | unsigned int snoop:1; | 390 | unsigned int snoop:1; |
390 | unsigned int align_buffer_size:1; | 391 | unsigned int align_buffer_size:1; |
391 | unsigned int region_requested:1; | 392 | unsigned int region_requested:1; |
392 | 393 | ||
393 | /* VGA-switcheroo setup */ | 394 | /* VGA-switcheroo setup */ |
394 | unsigned int use_vga_switcheroo:1; | 395 | unsigned int use_vga_switcheroo:1; |
395 | unsigned int vga_switcheroo_registered:1; | 396 | unsigned int vga_switcheroo_registered:1; |
396 | unsigned int init_failed:1; /* delayed init failed */ | 397 | unsigned int init_failed:1; /* delayed init failed */ |
397 | unsigned int disabled:1; /* disabled by VGA-switcher */ | 398 | unsigned int disabled:1; /* disabled by VGA-switcher */ |
398 | 399 | ||
399 | /* for debugging */ | 400 | /* for debugging */ |
400 | unsigned int last_cmd[AZX_MAX_CODECS]; | 401 | unsigned int last_cmd[AZX_MAX_CODECS]; |
401 | 402 | ||
402 | /* for pending irqs */ | 403 | /* for pending irqs */ |
403 | struct work_struct irq_pending_work; | 404 | struct work_struct irq_pending_work; |
404 | 405 | ||
405 | struct work_struct probe_work; | 406 | struct work_struct probe_work; |
406 | 407 | ||
407 | /* reboot notifier (for mysterious hangup problem at power-down) */ | 408 | /* reboot notifier (for mysterious hangup problem at power-down) */ |
408 | struct notifier_block reboot_notifier; | 409 | struct notifier_block reboot_notifier; |
409 | 410 | ||
410 | /* card list (for power_save trigger) */ | 411 | /* card list (for power_save trigger) */ |
411 | struct list_head list; | 412 | struct list_head list; |
412 | 413 | ||
413 | #ifdef CONFIG_SND_HDA_DSP_LOADER | 414 | #ifdef CONFIG_SND_HDA_DSP_LOADER |
414 | struct azx_dev saved_azx_dev; | 415 | struct azx_dev saved_azx_dev; |
415 | #endif | 416 | #endif |
416 | 417 | ||
417 | /* secondary power domain for hdmi audio under vga device */ | 418 | /* secondary power domain for hdmi audio under vga device */ |
418 | struct dev_pm_domain hdmi_pm_domain; | 419 | struct dev_pm_domain hdmi_pm_domain; |
419 | }; | 420 | }; |
420 | 421 | ||
421 | #ifdef CONFIG_SND_VERBOSE_PRINTK | 422 | #ifdef CONFIG_SND_VERBOSE_PRINTK |
422 | #define SFX /* nop */ | 423 | #define SFX /* nop */ |
423 | #else | 424 | #else |
424 | #define SFX "hda-intel " | 425 | #define SFX "hda-intel " |
425 | #endif | 426 | #endif |
426 | 427 | ||
427 | #ifdef CONFIG_X86 | 428 | #ifdef CONFIG_X86 |
428 | #define azx_snoop(chip) ((chip)->snoop) | 429 | #define azx_snoop(chip) ((chip)->snoop) |
429 | #else | 430 | #else |
430 | #define azx_snoop(chip) true | 431 | #define azx_snoop(chip) true |
431 | #endif | 432 | #endif |
432 | 433 | ||
433 | /* | 434 | /* |
434 | * macros for easy use | 435 | * macros for easy use |
435 | */ | 436 | */ |
436 | 437 | ||
437 | #define azx_writel(chip, reg, value) \ | 438 | #define azx_writel(chip, reg, value) \ |
438 | ((chip)->ops->reg_writel(value, (chip)->remap_addr + ICH6_REG_##reg)) | 439 | ((chip)->ops->reg_writel(value, (chip)->remap_addr + ICH6_REG_##reg)) |
439 | #define azx_readl(chip, reg) \ | 440 | #define azx_readl(chip, reg) \ |
440 | ((chip)->ops->reg_readl((chip)->remap_addr + ICH6_REG_##reg)) | 441 | ((chip)->ops->reg_readl((chip)->remap_addr + ICH6_REG_##reg)) |
441 | #define azx_writew(chip, reg, value) \ | 442 | #define azx_writew(chip, reg, value) \ |
442 | ((chip)->ops->reg_writew(value, (chip)->remap_addr + ICH6_REG_##reg)) | 443 | ((chip)->ops->reg_writew(value, (chip)->remap_addr + ICH6_REG_##reg)) |
443 | #define azx_readw(chip, reg) \ | 444 | #define azx_readw(chip, reg) \ |
444 | ((chip)->ops->reg_readw((chip)->remap_addr + ICH6_REG_##reg)) | 445 | ((chip)->ops->reg_readw((chip)->remap_addr + ICH6_REG_##reg)) |
445 | #define azx_writeb(chip, reg, value) \ | 446 | #define azx_writeb(chip, reg, value) \ |
446 | ((chip)->ops->reg_writeb(value, (chip)->remap_addr + ICH6_REG_##reg)) | 447 | ((chip)->ops->reg_writeb(value, (chip)->remap_addr + ICH6_REG_##reg)) |
447 | #define azx_readb(chip, reg) \ | 448 | #define azx_readb(chip, reg) \ |
448 | ((chip)->ops->reg_readb((chip)->remap_addr + ICH6_REG_##reg)) | 449 | ((chip)->ops->reg_readb((chip)->remap_addr + ICH6_REG_##reg)) |
449 | 450 | ||
450 | #define azx_sd_writel(chip, dev, reg, value) \ | 451 | #define azx_sd_writel(chip, dev, reg, value) \ |
451 | ((chip)->ops->reg_writel(value, (dev)->sd_addr + ICH6_REG_##reg)) | 452 | ((chip)->ops->reg_writel(value, (dev)->sd_addr + ICH6_REG_##reg)) |
452 | #define azx_sd_readl(chip, dev, reg) \ | 453 | #define azx_sd_readl(chip, dev, reg) \ |
453 | ((chip)->ops->reg_readl((dev)->sd_addr + ICH6_REG_##reg)) | 454 | ((chip)->ops->reg_readl((dev)->sd_addr + ICH6_REG_##reg)) |
454 | #define azx_sd_writew(chip, dev, reg, value) \ | 455 | #define azx_sd_writew(chip, dev, reg, value) \ |
455 | ((chip)->ops->reg_writew(value, (dev)->sd_addr + ICH6_REG_##reg)) | 456 | ((chip)->ops->reg_writew(value, (dev)->sd_addr + ICH6_REG_##reg)) |
456 | #define azx_sd_readw(chip, dev, reg) \ | 457 | #define azx_sd_readw(chip, dev, reg) \ |
457 | ((chip)->ops->reg_readw((dev)->sd_addr + ICH6_REG_##reg)) | 458 | ((chip)->ops->reg_readw((dev)->sd_addr + ICH6_REG_##reg)) |
458 | #define azx_sd_writeb(chip, dev, reg, value) \ | 459 | #define azx_sd_writeb(chip, dev, reg, value) \ |
459 | ((chip)->ops->reg_writeb(value, (dev)->sd_addr + ICH6_REG_##reg)) | 460 | ((chip)->ops->reg_writeb(value, (dev)->sd_addr + ICH6_REG_##reg)) |
460 | #define azx_sd_readb(chip, dev, reg) \ | 461 | #define azx_sd_readb(chip, dev, reg) \ |
461 | ((chip)->ops->reg_readb((dev)->sd_addr + ICH6_REG_##reg)) | 462 | ((chip)->ops->reg_readb((dev)->sd_addr + ICH6_REG_##reg)) |
462 | 463 | ||
463 | #endif /* __SOUND_HDA_PRIV_H */ | 464 | #endif /* __SOUND_HDA_PRIV_H */ |
464 | 465 |