Commit 6d4596905b65bf4c63c1a008f50bf385fa49f19b
Exists in
master
and in
13 other branches
Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 fix from Ingo Molnar: "This fixes the preemption-count imbalance crash reported by Owen Kibel" * 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/mce: Fix CMCI preemption bugs
Showing 2 changed files Side-by-side Diff
arch/x86/kernel/cpu/mcheck/mce.c
... | ... | @@ -598,7 +598,6 @@ |
598 | 598 | { |
599 | 599 | struct mce m; |
600 | 600 | int i; |
601 | - unsigned long *v; | |
602 | 601 | |
603 | 602 | this_cpu_inc(mce_poll_count); |
604 | 603 | |
... | ... | @@ -618,8 +617,7 @@ |
618 | 617 | if (!(m.status & MCI_STATUS_VAL)) |
619 | 618 | continue; |
620 | 619 | |
621 | - v = &get_cpu_var(mce_polled_error); | |
622 | - set_bit(0, v); | |
620 | + this_cpu_write(mce_polled_error, 1); | |
623 | 621 | /* |
624 | 622 | * Uncorrected or signalled events are handled by the exception |
625 | 623 | * handler when it is enabled, so don't process those here. |
arch/x86/kernel/cpu/mcheck/mce_intel.c
... | ... | @@ -42,7 +42,7 @@ |
42 | 42 | * cmci_discover_lock protects against parallel discovery attempts |
43 | 43 | * which could race against each other. |
44 | 44 | */ |
45 | -static DEFINE_RAW_SPINLOCK(cmci_discover_lock); | |
45 | +static DEFINE_SPINLOCK(cmci_discover_lock); | |
46 | 46 | |
47 | 47 | #define CMCI_THRESHOLD 1 |
48 | 48 | #define CMCI_POLL_INTERVAL (30 * HZ) |
49 | 49 | |
... | ... | @@ -144,14 +144,14 @@ |
144 | 144 | int bank; |
145 | 145 | u64 val; |
146 | 146 | |
147 | - raw_spin_lock_irqsave(&cmci_discover_lock, flags); | |
147 | + spin_lock_irqsave(&cmci_discover_lock, flags); | |
148 | 148 | owned = __get_cpu_var(mce_banks_owned); |
149 | 149 | for_each_set_bit(bank, owned, MAX_NR_BANKS) { |
150 | 150 | rdmsrl(MSR_IA32_MCx_CTL2(bank), val); |
151 | 151 | val &= ~MCI_CTL2_CMCI_EN; |
152 | 152 | wrmsrl(MSR_IA32_MCx_CTL2(bank), val); |
153 | 153 | } |
154 | - raw_spin_unlock_irqrestore(&cmci_discover_lock, flags); | |
154 | + spin_unlock_irqrestore(&cmci_discover_lock, flags); | |
155 | 155 | } |
156 | 156 | |
157 | 157 | static bool cmci_storm_detect(void) |
... | ... | @@ -211,7 +211,7 @@ |
211 | 211 | int i; |
212 | 212 | int bios_wrong_thresh = 0; |
213 | 213 | |
214 | - raw_spin_lock_irqsave(&cmci_discover_lock, flags); | |
214 | + spin_lock_irqsave(&cmci_discover_lock, flags); | |
215 | 215 | for (i = 0; i < banks; i++) { |
216 | 216 | u64 val; |
217 | 217 | int bios_zero_thresh = 0; |
... | ... | @@ -266,7 +266,7 @@ |
266 | 266 | WARN_ON(!test_bit(i, __get_cpu_var(mce_poll_banks))); |
267 | 267 | } |
268 | 268 | } |
269 | - raw_spin_unlock_irqrestore(&cmci_discover_lock, flags); | |
269 | + spin_unlock_irqrestore(&cmci_discover_lock, flags); | |
270 | 270 | if (mca_cfg.bios_cmci_threshold && bios_wrong_thresh) { |
271 | 271 | pr_info_once( |
272 | 272 | "bios_cmci_threshold: Some banks do not have valid thresholds set\n"); |
273 | 273 | |
... | ... | @@ -316,10 +316,10 @@ |
316 | 316 | |
317 | 317 | if (!cmci_supported(&banks)) |
318 | 318 | return; |
319 | - raw_spin_lock_irqsave(&cmci_discover_lock, flags); | |
319 | + spin_lock_irqsave(&cmci_discover_lock, flags); | |
320 | 320 | for (i = 0; i < banks; i++) |
321 | 321 | __cmci_disable_bank(i); |
322 | - raw_spin_unlock_irqrestore(&cmci_discover_lock, flags); | |
322 | + spin_unlock_irqrestore(&cmci_discover_lock, flags); | |
323 | 323 | } |
324 | 324 | |
325 | 325 | static void cmci_rediscover_work_func(void *arg) |
326 | 326 | |
... | ... | @@ -360,9 +360,9 @@ |
360 | 360 | if (!cmci_supported(&banks)) |
361 | 361 | return; |
362 | 362 | |
363 | - raw_spin_lock_irqsave(&cmci_discover_lock, flags); | |
363 | + spin_lock_irqsave(&cmci_discover_lock, flags); | |
364 | 364 | __cmci_disable_bank(bank); |
365 | - raw_spin_unlock_irqrestore(&cmci_discover_lock, flags); | |
365 | + spin_unlock_irqrestore(&cmci_discover_lock, flags); | |
366 | 366 | } |
367 | 367 | |
368 | 368 | static void intel_init_cmci(void) |