Commit 6dd7f59e7c79d8dd9e5bb1ddfece8aa8e26488ec
1 parent
0de5c3748e
Exists in
smarc-ti-linux-3.12.y
Refine the dts file
Showing 2 changed files with 29 additions and 51 deletions Side-by-side Diff
arch/arm/boot/dts/am335x-smarc-common.dtsi
| ... | ... | @@ -91,25 +91,6 @@ |
| 91 | 91 | cpus { |
| 92 | 92 | cpu@0 { |
| 93 | 93 | cpu0-supply = <&dcdc2_reg>; |
| 94 | - /* | |
| 95 | - * To consider voltage drop between PMIC and SoC, | |
| 96 | - * tolerance value is reduced to 2% from 4% and | |
| 97 | - * voltage value is increased as a precaution. | |
| 98 | - */ | |
| 99 | - operating-points = < | |
| 100 | - /* kHz uV */ | |
| 101 | - 1000000 1325000 | |
| 102 | - 800000 1260000 | |
| 103 | - 720000 1200000 | |
| 104 | - 600000 1100000 | |
| 105 | - 300000 950000 | |
| 106 | - >; | |
| 107 | - compatible = "arm,cortex-a8"; | |
| 108 | - voltage-tolerance = <0x2>; | |
| 109 | - platform-opp-modifier = <&mpu_opp_modifier>; | |
| 110 | - clocks = <&dpll_mpu_ck>; | |
| 111 | - clock-names = "cpu"; | |
| 112 | - clock-latency = <0x493e0>; | |
| 113 | 94 | }; |
| 114 | 95 | }; |
| 115 | 96 | |
| 116 | 97 | |
| ... | ... | @@ -475,9 +456,9 @@ |
| 475 | 456 | 0x02 0x24 0x11 0x86 /* Apply DCDC changes */ |
| 476 | 457 | >; |
| 477 | 458 | |
| 478 | - tps: tps@24 { | |
| 459 | + tps: tps@24 { | |
| 479 | 460 | reg = <0x24>; |
| 480 | - }; | |
| 461 | + }; | |
| 481 | 462 | |
| 482 | 463 | baseboard_eeprom: baseboard_eeprom@50 { |
| 483 | 464 | compatible = "at,24c256"; |
| ... | ... | @@ -704,6 +685,9 @@ |
| 704 | 685 | /include/ "tps65217.dtsi" |
| 705 | 686 | |
| 706 | 687 | &tps { |
| 688 | + compatible = "ti,tps65217"; | |
| 689 | + #address-cells = <1>; | |
| 690 | + #size-cells = <0>; | |
| 707 | 691 | regulators { |
| 708 | 692 | dcdc1_reg: regulator@0 { |
| 709 | 693 | regulator-always-on; |
| 710 | 694 | |
| ... | ... | @@ -711,18 +695,18 @@ |
| 711 | 695 | |
| 712 | 696 | dcdc2_reg: regulator@1 { |
| 713 | 697 | /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ |
| 714 | - regulator-name = "vdd_mpu"; | |
| 715 | - regulator-min-microvolt = <925000>; | |
| 716 | - regulator-max-microvolt = <1325000>; | |
| 698 | + regulator-name = "vdd_mpu"; | |
| 699 | + regulator-min-microvolt = <912500>; | |
| 700 | + regulator-max-microvolt = <1378000>; | |
| 717 | 701 | regulator-boot-on; |
| 718 | 702 | regulator-always-on; |
| 719 | 703 | }; |
| 720 | 704 | |
| 721 | 705 | dcdc3_reg: regulator@2 { |
| 722 | 706 | /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ |
| 723 | - regulator-name = "vdd_core"; | |
| 724 | - regulator-min-microvolt = <925000>; | |
| 725 | - regulator-max-microvolt = <1150000>; | |
| 707 | + regulator-name = "vdd_core"; | |
| 708 | + regulator-min-microvolt = <912500>; | |
| 709 | + regulator-max-microvolt = <1150000>; | |
| 726 | 710 | regulator-boot-on; |
| 727 | 711 | regulator-always-on; |
| 728 | 712 | }; |
| ... | ... | @@ -836,26 +820,20 @@ |
| 836 | 820 | status = "okay"; |
| 837 | 821 | }; |
| 838 | 822 | |
| 839 | -&efuse_sma { | |
| 840 | - compatible = "ti,opp-omap-am3352"; | |
| 841 | - reg = <0x44e107fc 0x04 /* EFUSE_SMA */ | |
| 842 | - 0x44e10600 0x04>; /* DEVICE_ID */ | |
| 843 | - ti,efuse-bit-enable-low; | |
| 844 | - mpu_opp_modifier: mpu_opp_modifier { | |
| 845 | - opp-modifier = < | |
| 846 | - /* kHz Rev offset mask */ | |
| 847 | - 1000000 OPP_REV(2,1) 0 AM33XX_EFUSE_SMA_OPP_NITRO_1GHZ_BIT | |
| 848 | - 800000 OPP_REV(2,1) 0 AM33XX_EFUSE_SMA_OPP_TURBO_800MHZ_BIT | |
| 849 | - 720000 OPP_REV(2,1) 0 AM33XX_EFUSE_SMA_OPP_120_720MHZ_BIT | |
| 850 | - 600000 OPP_REV(2,1) 0 AM33XX_EFUSE_SMA_OPP_100_600MHZ_BIT | |
| 851 | - 300000 (OPP_REV(2,0) | OPP_REV(2,1)) 0 0 | |
| 852 | - 1000000 OPP_REV(2,0) 0 0 | |
| 853 | - 800000 OPP_REV(2,0) 0 0 | |
| 854 | - 720000 (OPP_REV(1,0) | OPP_REV(2,0)) 0 0 | |
| 855 | - 600000 (OPP_REV(1,0) | OPP_REV(2,0)) 0 0 | |
| 856 | - 500000 (OPP_REV(1,0)) 0 0 | |
| 857 | - 275000 (OPP_REV(1,0)) 0 0 | |
| 858 | - >; | |
| 859 | - }; | |
| 860 | -}; | |
| 823 | +&mpu_opp_modifier { | |
| 824 | + opp-modifier = < | |
| 825 | + /* kHz Rev offset mask */ | |
| 826 | + 1000000 OPP_REV(2,1) 0 AM33XX_EFUSE_SMA_OPP_NITRO_1GHZ_BIT | |
| 827 | + 800000 OPP_REV(2,1) 0 AM33XX_EFUSE_SMA_OPP_TURBO_800MHZ_BIT | |
| 828 | + 720000 OPP_REV(2,1) 0 AM33XX_EFUSE_SMA_OPP_120_720MHZ_BIT | |
| 829 | + 600000 OPP_REV(2,1) 0 AM33XX_EFUSE_SMA_OPP_100_600MHZ_BIT | |
| 830 | + 300000 (OPP_REV(2,0) | OPP_REV(2,1)) 0 AM33XX_EFUSE_SMA_OPP_100_300MHZ_BIT | |
| 831 | + 1000000 OPP_REV(2,0) 0 0 | |
| 832 | + 800000 OPP_REV(2,0) 0 0 | |
| 833 | + 720000 (OPP_REV(1,0) | OPP_REV(2,0)) 0 0 | |
| 834 | + 600000 (OPP_REV(1,0) | OPP_REV(2,0)) 0 0 | |
| 835 | + 500000 (OPP_REV(1,0)) 0 0 | |
| 836 | + 275000 (OPP_REV(1,0)) 0 0 | |
| 837 | + >; | |
| 838 | + }; |
arch/arm/configs/smarc_t335x_defconfig
| ... | ... | @@ -612,9 +612,9 @@ |
| 612 | 612 | CONFIG_CPU_FREQ_STAT=y |
| 613 | 613 | CONFIG_CPU_FREQ_STAT_DETAILS=y |
| 614 | 614 | # CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set |
| 615 | -CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y | |
| 615 | +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set | |
| 616 | 616 | # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set |
| 617 | -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set | |
| 617 | +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y | |
| 618 | 618 | # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set |
| 619 | 619 | CONFIG_CPU_FREQ_GOV_PERFORMANCE=y |
| 620 | 620 | CONFIG_CPU_FREQ_GOV_POWERSAVE=y |