Eric Lee / smarc-ti-linux-kernel

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Commit 71a59b12727316f6d3c1cf4335bc2eaecb86da25

Authored by Linus Torvalds
2 parents 80a755545d 4b3415c936
Exists in ti-lsk-linux-4.1.y and in 10 other branches dlt-processor-sdk-linux-03.00.00.04, processor-sdk-linux-02.00.01, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04

Merge tag 'armsoc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC fixes from Olof Johansson:
 "A week's worth of fixes for various ARM platforms.  Diff wise, the
  largest fix is for OMAP to deal with how GIC now registers interrupts
  (irq_domain_add_legacy() -> irq_domain_add_linear() changes).

  Besides this, a few more renesas platforms needed the GIC instatiation
  done for legacy boards.  There's also a fix that disables coherency of
  mvebu due to issues, and a few other smaller fixes"

* tag 'armsoc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  arm64: dts: add baud rate to Juno stdout-path
  ARM: dts: imx25: Fix PWM "per" clocks
  bus: mvebu-mbus: fix support of MBus window 13
  Merge tag 'mvebu-fixes-3.19-3' of git://git.infradead.org/linux-mvebu into fixes
  ARM: mvebu: completely disable hardware I/O coherency
  ARM: OMAP: Work around hardcoded interrupts
  ARM: shmobile: r8a7779: Instantiate GIC from C board code in legacy builds
  ARM: shmobile: r8a7778: Instantiate GIC from C board code in legacy builds
  arm: boot: dts: dra7: enable dwc3 suspend PHY quirk

Showing 17 changed files Side-by-side Diff

arch/arm/boot/dts/dra7.dtsi
Diff comments   View file @ 71a59b1
... ... @@ -1257,6 +1257,8 @@
1257 1257 tx-fifo-resize;
1258 1258 maximum-speed = "super-speed";
1259 1259 dr_mode = "otg";
  1260 + snps,dis_u3_susphy_quirk;
  1261 + snps,dis_u2_susphy_quirk;
1260 1262 };
1261 1263 };
1262 1264  
... ... @@ -1278,6 +1280,8 @@
1278 1280 tx-fifo-resize;
1279 1281 maximum-speed = "high-speed";
1280 1282 dr_mode = "otg";
  1283 + snps,dis_u3_susphy_quirk;
  1284 + snps,dis_u2_susphy_quirk;
1281 1285 };
1282 1286 };
1283 1287  
... ... @@ -1299,6 +1303,8 @@
1299 1303 tx-fifo-resize;
1300 1304 maximum-speed = "high-speed";
1301 1305 dr_mode = "otg";
  1306 + snps,dis_u3_susphy_quirk;
  1307 + snps,dis_u2_susphy_quirk;
1302 1308 };
1303 1309 };
1304 1310  
arch/arm/boot/dts/imx25.dtsi
Diff comments   View file @ 71a59b1
... ... @@ -369,7 +369,7 @@
369 369 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
370 370 #pwm-cells = <2>;
371 371 reg = <0x53fa0000 0x4000>;
372   - clocks = <&clks 106>, <&clks 36>;
  372 + clocks = <&clks 106>, <&clks 52>;
373 373 clock-names = "ipg", "per";
374 374 interrupts = <36>;
375 375 };
... ... @@ -388,7 +388,7 @@
388 388 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
389 389 #pwm-cells = <2>;
390 390 reg = <0x53fa8000 0x4000>;
391   - clocks = <&clks 107>, <&clks 36>;
  391 + clocks = <&clks 107>, <&clks 52>;
392 392 clock-names = "ipg", "per";
393 393 interrupts = <41>;
394 394 };
... ... @@ -429,7 +429,7 @@
429 429 pwm4: pwm@53fc8000 {
430 430 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
431 431 reg = <0x53fc8000 0x4000>;
432   - clocks = <&clks 108>, <&clks 36>;
  432 + clocks = <&clks 108>, <&clks 52>;
433 433 clock-names = "ipg", "per";
434 434 interrupts = <42>;
435 435 };
... ... @@ -476,7 +476,7 @@
476 476 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
477 477 #pwm-cells = <2>;
478 478 reg = <0x53fe0000 0x4000>;
479   - clocks = <&clks 105>, <&clks 36>;
  479 + clocks = <&clks 105>, <&clks 52>;
480 480 clock-names = "ipg", "per";
481 481 interrupts = <26>;
482 482 };
arch/arm/mach-mvebu/coherency.c
Diff comments   View file @ 71a59b1
... ... @@ -246,9 +246,14 @@
246 246 return type;
247 247 }
248 248  
  249 +/*
  250 + * As a precaution, we currently completely disable hardware I/O
  251 + * coherency, until enough testing is done with automatic I/O
  252 + * synchronization barriers to validate that it is a proper solution.
  253 + */
249 254 int coherency_available(void)
250 255 {
251   - return coherency_type() != COHERENCY_FABRIC_TYPE_NONE;
  256 + return false;
252 257 }
253 258  
254 259 int __init coherency_init(void)
arch/arm/mach-omap2/common.h
Diff comments   View file @ 71a59b1
... ... @@ -211,6 +211,7 @@
211 211 extern struct device *omap2_get_l3_device(void);
212 212 extern struct device *omap4_get_dsp_device(void);
213 213  
  214 +unsigned int omap4_xlate_irq(unsigned int hwirq);
214 215 void omap_gic_of_init(void);
215 216  
216 217 #ifdef CONFIG_CACHE_L2X0
arch/arm/mach-omap2/omap4-common.c
Diff comments   View file @ 71a59b1
... ... @@ -256,6 +256,38 @@
256 256 }
257 257 omap_early_initcall(omap4_sar_ram_init);
258 258  
  259 +static struct of_device_id gic_match[] = {
  260 + { .compatible = "arm,cortex-a9-gic", },
  261 + { .compatible = "arm,cortex-a15-gic", },
  262 + { },
  263 +};
  264 +
  265 +static struct device_node *gic_node;
  266 +
  267 +unsigned int omap4_xlate_irq(unsigned int hwirq)
  268 +{
  269 + struct of_phandle_args irq_data;
  270 + unsigned int irq;
  271 +
  272 + if (!gic_node)
  273 + gic_node = of_find_matching_node(NULL, gic_match);
  274 +
  275 + if (WARN_ON(!gic_node))
  276 + return hwirq;
  277 +
  278 + irq_data.np = gic_node;
  279 + irq_data.args_count = 3;
  280 + irq_data.args[0] = 0;
  281 + irq_data.args[1] = hwirq - OMAP44XX_IRQ_GIC_START;
  282 + irq_data.args[2] = IRQ_TYPE_LEVEL_HIGH;
  283 +
  284 + irq = irq_create_of_mapping(&irq_data);
  285 + if (WARN_ON(!irq))
  286 + irq = hwirq;
  287 +
  288 + return irq;
  289 +}
  290 +
259 291 void __init omap_gic_of_init(void)
260 292 {
261 293 struct device_node *np;
arch/arm/mach-omap2/omap_hwmod.c
Diff comments   View file @ 71a59b1
... ... @@ -3534,9 +3534,15 @@
3534 3534  
3535 3535 mpu_irqs_cnt = _count_mpu_irqs(oh);
3536 3536 for (i = 0; i < mpu_irqs_cnt; i++) {
  3537 + unsigned int irq;
  3538 +
  3539 + if (oh->xlate_irq)
  3540 + irq = oh->xlate_irq((oh->mpu_irqs + i)->irq);
  3541 + else
  3542 + irq = (oh->mpu_irqs + i)->irq;
3537 3543 (res + r)->name = (oh->mpu_irqs + i)->name;
3538   - (res + r)->start = (oh->mpu_irqs + i)->irq;
3539   - (res + r)->end = (oh->mpu_irqs + i)->irq;
  3544 + (res + r)->start = irq;
  3545 + (res + r)->end = irq;
3540 3546 (res + r)->flags = IORESOURCE_IRQ;
3541 3547 r++;
3542 3548 }
arch/arm/mach-omap2/omap_hwmod.h
Diff comments   View file @ 71a59b1
... ... @@ -676,6 +676,7 @@
676 676 spinlock_t _lock;
677 677 struct list_head node;
678 678 struct omap_hwmod_ocp_if *_mpu_port;
  679 + unsigned int (*xlate_irq)(unsigned int);
679 680 u16 flags;
680 681 u8 mpu_rt_idx;
681 682 u8 response_lat;
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
Diff comments   View file @ 71a59b1
... ... @@ -479,6 +479,7 @@
479 479 .class = &omap44xx_dma_hwmod_class,
480 480 .clkdm_name = "l3_dma_clkdm",
481 481 .mpu_irqs = omap44xx_dma_system_irqs,
  482 + .xlate_irq = omap4_xlate_irq,
482 483 .main_clk = "l3_div_ck",
483 484 .prcm = {
484 485 .omap4 = {
... ... @@ -640,6 +641,7 @@
640 641 .class = &omap44xx_dispc_hwmod_class,
641 642 .clkdm_name = "l3_dss_clkdm",
642 643 .mpu_irqs = omap44xx_dss_dispc_irqs,
  644 + .xlate_irq = omap4_xlate_irq,
643 645 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
644 646 .main_clk = "dss_dss_clk",
645 647 .prcm = {
... ... @@ -693,6 +695,7 @@
693 695 .class = &omap44xx_dsi_hwmod_class,
694 696 .clkdm_name = "l3_dss_clkdm",
695 697 .mpu_irqs = omap44xx_dss_dsi1_irqs,
  698 + .xlate_irq = omap4_xlate_irq,
696 699 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
697 700 .main_clk = "dss_dss_clk",
698 701 .prcm = {
... ... @@ -726,6 +729,7 @@
726 729 .class = &omap44xx_dsi_hwmod_class,
727 730 .clkdm_name = "l3_dss_clkdm",
728 731 .mpu_irqs = omap44xx_dss_dsi2_irqs,
  732 + .xlate_irq = omap4_xlate_irq,
729 733 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
730 734 .main_clk = "dss_dss_clk",
731 735 .prcm = {
... ... @@ -784,6 +788,7 @@
784 788 */
785 789 .flags = HWMOD_SWSUP_SIDLE,
786 790 .mpu_irqs = omap44xx_dss_hdmi_irqs,
  791 + .xlate_irq = omap4_xlate_irq,
787 792 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
788 793 .main_clk = "dss_48mhz_clk",
789 794 .prcm = {
arch/arm/mach-omap2/omap_hwmod_54xx_data.c
Diff comments   View file @ 71a59b1
... ... @@ -288,6 +288,7 @@
288 288 .class = &omap54xx_dma_hwmod_class,
289 289 .clkdm_name = "dma_clkdm",
290 290 .mpu_irqs = omap54xx_dma_system_irqs,
  291 + .xlate_irq = omap4_xlate_irq,
291 292 .main_clk = "l3_iclk_div",
292 293 .prcm = {
293 294 .omap4 = {
arch/arm/mach-omap2/prcm-common.h
Diff comments   View file @ 71a59b1
... ... @@ -498,6 +498,7 @@
498 498 u8 nr_irqs;
499 499 const struct omap_prcm_irq *irqs;
500 500 int irq;
  501 + unsigned int (*xlate_irq)(unsigned int);
501 502 void (*read_pending_irqs)(unsigned long *events);
502 503 void (*ocp_barrier)(void);
503 504 void (*save_and_clear_irqen)(u32 *saved_mask);
arch/arm/mach-omap2/prm44xx.c
Diff comments   View file @ 71a59b1
... ... @@ -49,6 +49,7 @@
49 49 .irqs = omap4_prcm_irqs,
50 50 .nr_irqs = ARRAY_SIZE(omap4_prcm_irqs),
51 51 .irq = 11 + OMAP44XX_IRQ_GIC_START,
  52 + .xlate_irq = omap4_xlate_irq,
52 53 .read_pending_irqs = &omap44xx_prm_read_pending_irqs,
53 54 .ocp_barrier = &omap44xx_prm_ocp_barrier,
54 55 .save_and_clear_irqen = &omap44xx_prm_save_and_clear_irqen,
55 56  
... ... @@ -751,8 +752,10 @@
751 752 }
752 753  
753 754 /* Once OMAP4 DT is filled as well */
754   - if (irq_num >= 0)
  755 + if (irq_num >= 0) {
755 756 omap4_prcm_irq_setup.irq = irq_num;
  757 + omap4_prcm_irq_setup.xlate_irq = NULL;
  758 + }
756 759 }
757 760  
758 761 omap44xx_prm_enable_io_wakeup();
arch/arm/mach-omap2/prm_common.c
Diff comments   View file @ 71a59b1
... ... @@ -187,6 +187,7 @@
187 187 */
188 188 void omap_prcm_irq_cleanup(void)
189 189 {
  190 + unsigned int irq;
190 191 int i;
191 192  
192 193 if (!prcm_irq_setup) {
... ... @@ -211,7 +212,11 @@
211 212 kfree(prcm_irq_setup->priority_mask);
212 213 prcm_irq_setup->priority_mask = NULL;
213 214  
214   - irq_set_chained_handler(prcm_irq_setup->irq, NULL);
  215 + if (prcm_irq_setup->xlate_irq)
  216 + irq = prcm_irq_setup->xlate_irq(prcm_irq_setup->irq);
  217 + else
  218 + irq = prcm_irq_setup->irq;
  219 + irq_set_chained_handler(irq, NULL);
215 220  
216 221 if (prcm_irq_setup->base_irq > 0)
217 222 irq_free_descs(prcm_irq_setup->base_irq,
... ... @@ -259,6 +264,7 @@
259 264 int offset, i;
260 265 struct irq_chip_generic *gc;
261 266 struct irq_chip_type *ct;
  267 + unsigned int irq;
262 268  
263 269 if (!irq_setup)
264 270 return -EINVAL;
... ... @@ -298,7 +304,11 @@
298 304 1 << (offset & 0x1f);
299 305 }
300 306  
301   - irq_set_chained_handler(irq_setup->irq, omap_prcm_irq_handler);
  307 + if (irq_setup->xlate_irq)
  308 + irq = irq_setup->xlate_irq(irq_setup->irq);
  309 + else
  310 + irq = irq_setup->irq;
  311 + irq_set_chained_handler(irq, omap_prcm_irq_handler);
302 312  
303 313 irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32,
304 314 0);
arch/arm/mach-omap2/twl-common.c
Diff comments   View file @ 71a59b1
... ... @@ -66,19 +66,24 @@
66 66 omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1);
67 67 }
68 68  
  69 +#ifdef CONFIG_ARCH_OMAP4
69 70 void __init omap4_pmic_init(const char *pmic_type,
70 71 struct twl4030_platform_data *pmic_data,
71 72 struct i2c_board_info *devices, int nr_devices)
72 73 {
73 74 /* PMIC part*/
  75 + unsigned int irq;
  76 +
74 77 omap_mux_init_signal("sys_nirq1", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE);
75 78 omap_mux_init_signal("fref_clk0_out.sys_drm_msecure", OMAP_PIN_OUTPUT);
76   - omap_pmic_init(1, 400, pmic_type, 7 + OMAP44XX_IRQ_GIC_START, pmic_data);
  79 + irq = omap4_xlate_irq(7 + OMAP44XX_IRQ_GIC_START);
  80 + omap_pmic_init(1, 400, pmic_type, irq, pmic_data);
77 81  
78 82 /* Register additional devices on i2c1 bus if needed */
79 83 if (devices)
80 84 i2c_register_board_info(1, devices, nr_devices);
81 85 }
  86 +#endif
82 87  
83 88 void __init omap_pmic_late_init(void)
84 89 {
arch/arm/mach-shmobile/setup-r8a7778.c
Diff comments   View file @ 71a59b1
... ... @@ -576,11 +576,18 @@
576 576 void __init r8a7778_init_irq_dt(void)
577 577 {
578 578 void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
  579 +#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
  580 + void __iomem *gic_dist_base = ioremap_nocache(0xfe438000, 0x1000);
  581 + void __iomem *gic_cpu_base = ioremap_nocache(0xfe430000, 0x1000);
  582 +#endif
579 583  
580 584 BUG_ON(!base);
581 585  
  586 +#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
  587 + gic_init(0, 29, gic_dist_base, gic_cpu_base);
  588 +#else
582 589 irqchip_init();
583   -
  590 +#endif
584 591 /* route all interrupts to ARM */
585 592 __raw_writel(0x73ffffff, base + INT2NTSR0);
586 593 __raw_writel(0xffffffff, base + INT2NTSR1);
arch/arm/mach-shmobile/setup-r8a7779.c
Diff comments   View file @ 71a59b1
... ... @@ -720,10 +720,17 @@
720 720  
721 721 void __init r8a7779_init_irq_dt(void)
722 722 {
  723 +#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
  724 + void __iomem *gic_dist_base = ioremap_nocache(0xf0001000, 0x1000);
  725 + void __iomem *gic_cpu_base = ioremap_nocache(0xf0000100, 0x1000);
  726 +#endif
723 727 gic_arch_extn.irq_set_wake = r8a7779_set_wake;
724 728  
  729 +#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
  730 + gic_init(0, 29, gic_dist_base, gic_cpu_base);
  731 +#else
725 732 irqchip_init();
726   -
  733 +#endif
727 734 /* route all interrupts to ARM */
728 735 __raw_writel(0xffffffff, INT2NTSR0);
729 736 __raw_writel(0x3fffffff, INT2NTSR1);
arch/arm64/boot/dts/arm/juno.dts
Diff comments   View file @ 71a59b1
... ... @@ -22,7 +22,7 @@
22 22 };
23 23  
24 24 chosen {
25   - stdout-path = &soc_uart0;
  25 + stdout-path = "serial0:115200n8";
26 26 };
27 27  
28 28 psci {
drivers/bus/mvebu-mbus.c
Diff comments   View file @ 71a59b1
... ... @@ -210,12 +210,25 @@
210 210 }
211 211  
212 212 /* Checks whether the given window number is available */
  213 +
  214 +/* On Armada XP, 375 and 38x the MBus window 13 has the remap
  215 + * capability, like windows 0 to 7. However, the mvebu-mbus driver
  216 + * isn't currently taking into account this special case, which means
  217 + * that when window 13 is actually used, the remap registers are left
  218 + * to 0, making the device using this MBus window unavailable. The
  219 + * quick fix for stable is to not use window 13. A follow up patch
  220 + * will correctly handle this window.
  221 +*/
213 222 static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
214 223 const int win)
215 224 {
216 225 void __iomem *addr = mbus->mbuswins_base +
217 226 mbus->soc->win_cfg_offset(win);
218 227 u32 ctrl = readl(addr + WIN_CTRL_OFF);
  228 +
  229 + if (win == 13)
  230 + return false;
  231 +
219 232 return !(ctrl & WIN_CTRL_ENABLE);
220 233 }
221 234