Commit 7b255436df0543856faaae4704034fe83bc20717
Committed by
Bartlomiej Zolnierkiewicz
1 parent
eee49298dd
Exists in
master
and in
20 other branches
siimage: coding style cleanup (take 2)
Fix 18 errors and several warnings given by checkpatch.pl: - use of C99 // comments; - trailing whitespace; - 'switch' and 'case' not at the same indentation level; - no space before the open parenthesis of the 'if' and 'switch' statements; - space between function name and open parenthesis (though I have introduced such warnins in some places since the code looks prettier with the spaces); - including <asm/io.h> instead of <linux/io.h>; - line over 80 characters. In addition to these changes, also do the following: - make the arrays in sil_set_pio_mode() 'static', and make the arrays in sil_set_dma_mode() 'static const'; - change the string of the 'if' statements into the 'switch' statement in sil_pata_udma_filter(); - drop the needless '==' operators from the 'if' statements where a condition is a mere bit test; - remove needless initializer for the 'tmp' variable in init_chipset_siimage(); - beautify groups of the variable initializers and assignment operators; - add new line after variable definitions; - remove new line between the comment and the statements it refers to; - remove needless curly braces and parentheses; - fix typos, capitalize acronyms, etc. in the comments... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Showing 1 changed file with 113 additions and 119 deletions Side-by-side Diff
drivers/ide/pci/siimage.c
1 | 1 | /* |
2 | 2 | * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org> |
3 | 3 | * Copyright (C) 2003 Red Hat <alan@redhat.com> |
4 | - * Copyright (C) 2007 MontaVista Software, Inc. | |
4 | + * Copyright (C) 2007-2008 MontaVista Software, Inc. | |
5 | 5 | * Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz |
6 | 6 | * |
7 | 7 | * May be copied or modified under the terms of the GNU General Public License |
8 | 8 | |
... | ... | @@ -17,10 +17,10 @@ |
17 | 17 | * |
18 | 18 | * FAQ Items: |
19 | 19 | * If you are using Marvell SATA-IDE adapters with Maxtor drives |
20 | - * ensure the system is set up for ATA100/UDMA5 not UDMA6. | |
20 | + * ensure the system is set up for ATA100/UDMA5, not UDMA6. | |
21 | 21 | * |
22 | 22 | * If you are using WD drives with SATA bridges you must set the |
23 | - * drive to "Single". "Master" will hang | |
23 | + * drive to "Single". "Master" will hang. | |
24 | 24 | * |
25 | 25 | * If you have strange problems with nVidia chipset systems please |
26 | 26 | * see the SI support documentation and update your system BIOS |
27 | 27 | |
28 | 28 | |
29 | 29 | |
30 | 30 | |
... | ... | @@ -42,25 +42,24 @@ |
42 | 42 | #include <linux/hdreg.h> |
43 | 43 | #include <linux/ide.h> |
44 | 44 | #include <linux/init.h> |
45 | +#include <linux/io.h> | |
45 | 46 | |
46 | -#include <asm/io.h> | |
47 | - | |
48 | 47 | /** |
49 | 48 | * pdev_is_sata - check if device is SATA |
50 | 49 | * @pdev: PCI device to check |
51 | - * | |
50 | + * | |
52 | 51 | * Returns true if this is a SATA controller |
53 | 52 | */ |
54 | - | |
53 | + | |
55 | 54 | static int pdev_is_sata(struct pci_dev *pdev) |
56 | 55 | { |
57 | 56 | #ifdef CONFIG_BLK_DEV_IDE_SATA |
58 | - switch(pdev->device) { | |
59 | - case PCI_DEVICE_ID_SII_3112: | |
60 | - case PCI_DEVICE_ID_SII_1210SA: | |
61 | - return 1; | |
62 | - case PCI_DEVICE_ID_SII_680: | |
63 | - return 0; | |
57 | + switch (pdev->device) { | |
58 | + case PCI_DEVICE_ID_SII_3112: | |
59 | + case PCI_DEVICE_ID_SII_1210SA: | |
60 | + return 1; | |
61 | + case PCI_DEVICE_ID_SII_680: | |
62 | + return 0; | |
64 | 63 | } |
65 | 64 | BUG(); |
66 | 65 | #endif |
67 | 66 | |
... | ... | @@ -70,10 +69,10 @@ |
70 | 69 | /** |
71 | 70 | * is_sata - check if hwif is SATA |
72 | 71 | * @hwif: interface to check |
73 | - * | |
72 | + * | |
74 | 73 | * Returns true if this is a SATA controller |
75 | 74 | */ |
76 | - | |
75 | + | |
77 | 76 | static inline int is_sata(ide_hwif_t *hwif) |
78 | 77 | { |
79 | 78 | return pdev_is_sata(to_pci_dev(hwif->dev)); |
80 | 79 | |
81 | 80 | |
82 | 81 | |
83 | 82 | |
84 | 83 | |
... | ... | @@ -86,21 +85,22 @@ |
86 | 85 | * |
87 | 86 | * Turn a config register offset into the right address in either |
88 | 87 | * PCI space or MMIO space to access the control register in question |
89 | - * Thankfully this is a configuration operation so isnt performance | |
90 | - * criticial. | |
88 | + * Thankfully this is a configuration operation, so isn't performance | |
89 | + * critical. | |
91 | 90 | */ |
92 | - | |
91 | + | |
93 | 92 | static unsigned long siimage_selreg(ide_hwif_t *hwif, int r) |
94 | 93 | { |
95 | 94 | unsigned long base = (unsigned long)hwif->hwif_data; |
95 | + | |
96 | 96 | base += 0xA0 + r; |
97 | - if(hwif->mmio) | |
98 | - base += (hwif->channel << 6); | |
97 | + if (hwif->mmio) | |
98 | + base += hwif->channel << 6; | |
99 | 99 | else |
100 | - base += (hwif->channel << 4); | |
100 | + base += hwif->channel << 4; | |
101 | 101 | return base; |
102 | 102 | } |
103 | - | |
103 | + | |
104 | 104 | /** |
105 | 105 | * siimage_seldev - return register base |
106 | 106 | * @hwif: interface |
107 | 107 | |
108 | 108 | |
109 | 109 | |
... | ... | @@ -110,16 +110,17 @@ |
110 | 110 | * PCI space or MMIO space to access the control register in question |
111 | 111 | * including accounting for the unit shift. |
112 | 112 | */ |
113 | - | |
113 | + | |
114 | 114 | static inline unsigned long siimage_seldev(ide_drive_t *drive, int r) |
115 | 115 | { |
116 | 116 | ide_hwif_t *hwif = HWIF(drive); |
117 | - unsigned long base = (unsigned long)hwif->hwif_data; | |
117 | + unsigned long base = (unsigned long)hwif->hwif_data; | |
118 | + | |
118 | 119 | base += 0xA0 + r; |
119 | - if(hwif->mmio) | |
120 | - base += (hwif->channel << 6); | |
120 | + if (hwif->mmio) | |
121 | + base += hwif->channel << 6; | |
121 | 122 | else |
122 | - base += (hwif->channel << 4); | |
123 | + base += hwif->channel << 4; | |
123 | 124 | base |= drive->select.b.unit << drive->select.b.unit; |
124 | 125 | return base; |
125 | 126 | } |
126 | 127 | |
127 | 128 | |
128 | 129 | |
129 | 130 | |
130 | 131 | |
... | ... | @@ -184,21 +185,26 @@ |
184 | 185 | |
185 | 186 | static u8 sil_pata_udma_filter(ide_drive_t *drive) |
186 | 187 | { |
187 | - ide_hwif_t *hwif = drive->hwif; | |
188 | - struct pci_dev *dev = to_pci_dev(hwif->dev); | |
189 | - unsigned long base = (unsigned long) hwif->hwif_data; | |
190 | - u8 mask = 0, scsc; | |
188 | + ide_hwif_t *hwif = drive->hwif; | |
189 | + struct pci_dev *dev = to_pci_dev(hwif->dev); | |
190 | + unsigned long base = (unsigned long)hwif->hwif_data; | |
191 | + u8 scsc, mask = 0; | |
191 | 192 | |
192 | 193 | scsc = sil_ioread8(dev, base + (hwif->mmio ? 0x4A : 0x8A)); |
193 | 194 | |
194 | - if ((scsc & 0x30) == 0x10) /* 133 */ | |
195 | + switch (scsc & 0x30) { | |
196 | + case 0x10: /* 133 */ | |
195 | 197 | mask = ATA_UDMA6; |
196 | - else if ((scsc & 0x30) == 0x20) /* 2xPCI */ | |
198 | + break; | |
199 | + case 0x20: /* 2xPCI */ | |
197 | 200 | mask = ATA_UDMA6; |
198 | - else if ((scsc & 0x30) == 0x00) /* 100 */ | |
201 | + break; | |
202 | + case 0x00: /* 100 */ | |
199 | 203 | mask = ATA_UDMA5; |
200 | - else /* Disabled ? */ | |
204 | + break; | |
205 | + default: /* Disabled ? */ | |
201 | 206 | BUG(); |
207 | + } | |
202 | 208 | |
203 | 209 | return mask; |
204 | 210 | } |
... | ... | @@ -220,8 +226,8 @@ |
220 | 226 | |
221 | 227 | static void sil_set_pio_mode(ide_drive_t *drive, u8 pio) |
222 | 228 | { |
223 | - const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 }; | |
224 | - const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; | |
229 | + static const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 }; | |
230 | + static const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; | |
225 | 231 | |
226 | 232 | ide_hwif_t *hwif = HWIF(drive); |
227 | 233 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
... | ... | @@ -229,7 +235,7 @@ |
229 | 235 | u32 speedt = 0; |
230 | 236 | u16 speedp = 0; |
231 | 237 | unsigned long addr = siimage_seldev(drive, 0x04); |
232 | - unsigned long tfaddr = siimage_selreg(hwif, 0x02); | |
238 | + unsigned long tfaddr = siimage_selreg(hwif, 0x02); | |
233 | 239 | unsigned long base = (unsigned long)hwif->hwif_data; |
234 | 240 | u8 tf_pio = pio; |
235 | 241 | u8 addr_mask = hwif->channel ? (hwif->mmio ? 0xF4 : 0x84) |
... | ... | @@ -261,7 +267,7 @@ |
261 | 267 | |
262 | 268 | mode = sil_ioread8(dev, base + addr_mask); |
263 | 269 | mode &= ~(unit ? 0x30 : 0x03); |
264 | - mode |= (unit ? 0x10 : 0x01); | |
270 | + mode |= unit ? 0x10 : 0x01; | |
265 | 271 | sil_iowrite8(dev, mode, base + addr_mask); |
266 | 272 | } |
267 | 273 | |
268 | 274 | |
269 | 275 | |
270 | 276 | |
271 | 277 | |
272 | 278 | |
273 | 279 | |
... | ... | @@ -275,44 +281,43 @@ |
275 | 281 | |
276 | 282 | static void sil_set_dma_mode(ide_drive_t *drive, const u8 speed) |
277 | 283 | { |
278 | - u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }; | |
279 | - u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 }; | |
280 | - u16 dma[] = { 0x2208, 0x10C2, 0x10C1 }; | |
284 | + static const u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }; | |
285 | + static const u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 }; | |
286 | + static const u16 dma[] = { 0x2208, 0x10C2, 0x10C1 }; | |
281 | 287 | |
282 | 288 | ide_hwif_t *hwif = HWIF(drive); |
283 | 289 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
284 | 290 | u16 ultra = 0, multi = 0; |
285 | 291 | u8 mode = 0, unit = drive->select.b.unit; |
286 | 292 | unsigned long base = (unsigned long)hwif->hwif_data; |
287 | - u8 scsc = 0, addr_mask = ((hwif->channel) ? | |
288 | - ((hwif->mmio) ? 0xF4 : 0x84) : | |
289 | - ((hwif->mmio) ? 0xB4 : 0x80)); | |
290 | - | |
293 | + u8 scsc = 0, addr_mask = hwif->channel ? | |
294 | + (hwif->mmio ? 0xF4 : 0x84) : | |
295 | + (hwif->mmio ? 0xB4 : 0x80); | |
291 | 296 | unsigned long ma = siimage_seldev(drive, 0x08); |
292 | 297 | unsigned long ua = siimage_seldev(drive, 0x0C); |
293 | 298 | |
294 | - scsc = sil_ioread8(dev, base + (hwif->mmio ? 0x4A : 0x8A)); | |
295 | - mode = sil_ioread8(dev, base + addr_mask); | |
299 | + scsc = sil_ioread8 (dev, base + (hwif->mmio ? 0x4A : 0x8A)); | |
300 | + mode = sil_ioread8 (dev, base + addr_mask); | |
296 | 301 | multi = sil_ioread16(dev, ma); |
297 | 302 | ultra = sil_ioread16(dev, ua); |
298 | 303 | |
299 | - mode &= ~((unit) ? 0x30 : 0x03); | |
304 | + mode &= ~(unit ? 0x30 : 0x03); | |
300 | 305 | ultra &= ~0x3F; |
301 | 306 | scsc = ((scsc & 0x30) == 0x00) ? 0 : 1; |
302 | 307 | |
303 | 308 | scsc = is_sata(hwif) ? 1 : scsc; |
304 | 309 | |
305 | 310 | if (speed >= XFER_UDMA_0) { |
306 | - multi = dma[2]; | |
307 | - ultra |= (scsc ? ultra6[speed - XFER_UDMA_0] : | |
308 | - ultra5[speed - XFER_UDMA_0]); | |
309 | - mode |= (unit ? 0x30 : 0x03); | |
311 | + multi = dma[2]; | |
312 | + ultra |= scsc ? ultra6[speed - XFER_UDMA_0] : | |
313 | + ultra5[speed - XFER_UDMA_0]; | |
314 | + mode |= unit ? 0x30 : 0x03; | |
310 | 315 | } else { |
311 | 316 | multi = dma[speed - XFER_MW_DMA_0]; |
312 | - mode |= (unit ? 0x20 : 0x02); | |
317 | + mode |= unit ? 0x20 : 0x02; | |
313 | 318 | } |
314 | 319 | |
315 | - sil_iowrite8(dev, mode, base + addr_mask); | |
320 | + sil_iowrite8 (dev, mode, base + addr_mask); | |
316 | 321 | sil_iowrite16(dev, multi, ma); |
317 | 322 | sil_iowrite16(dev, ultra, ua); |
318 | 323 | } |
319 | 324 | |
... | ... | @@ -326,13 +331,14 @@ |
326 | 331 | unsigned long addr = siimage_selreg(hwif, 1); |
327 | 332 | |
328 | 333 | /* return 1 if INTR asserted */ |
329 | - if ((hwif->INB(hwif->dma_status) & 4) == 4) | |
334 | + if (hwif->INB(hwif->dma_status) & 4) | |
330 | 335 | return 1; |
331 | 336 | |
332 | 337 | /* return 1 if Device INTR asserted */ |
333 | 338 | pci_read_config_byte(dev, addr, &dma_altstat); |
334 | 339 | if (dma_altstat & 8) |
335 | - return 0; //return 1; | |
340 | + return 0; /* return 1; */ | |
341 | + | |
336 | 342 | return 0; |
337 | 343 | } |
338 | 344 | |
... | ... | @@ -352,9 +358,9 @@ |
352 | 358 | = (void __iomem *)hwif->sata_scr[SATA_ERROR_OFFSET]; |
353 | 359 | |
354 | 360 | if (sata_error_addr) { |
355 | - unsigned long base = (unsigned long)hwif->hwif_data; | |
356 | - u32 ext_stat = readl((void __iomem *)(base + 0x10)); | |
357 | - u8 watchdog = 0; | |
361 | + unsigned long base = (unsigned long)hwif->hwif_data; | |
362 | + u32 ext_stat = readl((void __iomem *)(base + 0x10)); | |
363 | + u8 watchdog = 0; | |
358 | 364 | |
359 | 365 | if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) { |
360 | 366 | u32 sata_error = readl(sata_error_addr); |
361 | 367 | |
362 | 368 | |
363 | 369 | |
364 | 370 | |
... | ... | @@ -363,25 +369,22 @@ |
363 | 369 | watchdog = (sata_error & 0x00680000) ? 1 : 0; |
364 | 370 | printk(KERN_WARNING "%s: sata_error = 0x%08x, " |
365 | 371 | "watchdog = %d, %s\n", |
366 | - drive->name, sata_error, watchdog, | |
367 | - __func__); | |
368 | - | |
369 | - } else { | |
372 | + drive->name, sata_error, watchdog, __func__); | |
373 | + } else | |
370 | 374 | watchdog = (ext_stat & 0x8000) ? 1 : 0; |
371 | - } | |
372 | - ext_stat >>= 16; | |
373 | 375 | |
376 | + ext_stat >>= 16; | |
374 | 377 | if (!(ext_stat & 0x0404) && !watchdog) |
375 | 378 | return 0; |
376 | 379 | } |
377 | 380 | |
378 | 381 | /* return 1 if INTR asserted */ |
379 | - if ((readb((void __iomem *)hwif->dma_status) & 0x04) == 0x04) | |
382 | + if (readb((void __iomem *)hwif->dma_status) & 0x04) | |
380 | 383 | return 1; |
381 | 384 | |
382 | 385 | /* return 1 if Device INTR asserted */ |
383 | - if ((readb((void __iomem *)addr) & 8) == 8) | |
384 | - return 0; //return 1; | |
386 | + if (readb((void __iomem *)addr) & 8) | |
387 | + return 0; /* return 1; */ | |
385 | 388 | |
386 | 389 | return 0; |
387 | 390 | } |
388 | 391 | |
389 | 392 | |
390 | 393 | |
391 | 394 | |
392 | 395 | |
... | ... | @@ -440,33 +443,32 @@ |
440 | 443 | } |
441 | 444 | |
442 | 445 | /** |
443 | - * setup_mmio_siimage - switch an SI controller into MMIO | |
446 | + * setup_mmio_siimage - switch controller into MMIO mode | |
444 | 447 | * @dev: PCI device we are configuring |
445 | 448 | * @name: device name |
446 | 449 | * |
447 | - * Attempt to put the device into mmio mode. There are some slight | |
448 | - * complications here with certain systems where the mmio bar isnt | |
449 | - * mapped so we have to be sure we can fall back to I/O. | |
450 | + * Attempt to put the device into MMIO mode. There are some slight | |
451 | + * complications here with certain systems where the MMIO BAR isn't | |
452 | + * mapped, so we have to be sure that we can fall back to I/O. | |
450 | 453 | */ |
451 | - | |
452 | -static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name) | |
454 | + | |
455 | +static unsigned int setup_mmio_siimage(struct pci_dev *dev, const char *name) | |
453 | 456 | { |
454 | 457 | resource_size_t bar5 = pci_resource_start(dev, 5); |
455 | 458 | unsigned long barsize = pci_resource_len(dev, 5); |
456 | 459 | void __iomem *ioaddr; |
457 | 460 | |
458 | 461 | /* |
459 | - * Drop back to PIO if we can't map the mmio. Some | |
460 | - * systems seem to get terminally confused in the PCI | |
461 | - * spaces. | |
462 | + * Drop back to PIO if we can't map the MMIO. Some systems | |
463 | + * seem to get terminally confused in the PCI spaces. | |
462 | 464 | */ |
463 | 465 | if (!request_mem_region(bar5, barsize, name)) { |
464 | - printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n"); | |
466 | + printk(KERN_WARNING "siimage: IDE controller MMIO ports not " | |
467 | + "available.\n"); | |
465 | 468 | return 0; |
466 | 469 | } |
467 | 470 | |
468 | 471 | ioaddr = ioremap(bar5, barsize); |
469 | - | |
470 | 472 | if (ioaddr == NULL) { |
471 | 473 | release_mem_region(bar5, barsize); |
472 | 474 | return 0; |
473 | 475 | |
474 | 476 | |
475 | 477 | |
476 | 478 | |
... | ... | @@ -484,23 +486,23 @@ |
484 | 486 | * @name: device name |
485 | 487 | * |
486 | 488 | * Perform the initial PCI set up for this device. Attempt to switch |
487 | - * to 133MHz clocking if the system isn't already set up to do it. | |
489 | + * to 133 MHz clocking if the system isn't already set up to do it. | |
488 | 490 | */ |
489 | 491 | |
490 | -static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const char *name) | |
492 | +static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, | |
493 | + const char *name) | |
491 | 494 | { |
492 | 495 | unsigned long base, scsc_addr; |
493 | 496 | void __iomem *ioaddr = NULL; |
494 | - u8 rev = dev->revision, tmp = 0, BA5_EN = 0; | |
497 | + u8 rev = dev->revision, tmp, BA5_EN; | |
495 | 498 | |
496 | 499 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255); |
497 | 500 | |
498 | 501 | pci_read_config_byte(dev, 0x8A, &BA5_EN); |
499 | 502 | |
500 | - if ((BA5_EN & 0x01) || pci_resource_start(dev, 5)) { | |
503 | + if ((BA5_EN & 0x01) || pci_resource_start(dev, 5)) | |
501 | 504 | if (setup_mmio_siimage(dev, name)) |
502 | 505 | ioaddr = pci_get_drvdata(dev); |
503 | - } | |
504 | 506 | |
505 | 507 | base = (unsigned long)ioaddr; |
506 | 508 | |
... | ... | @@ -527,7 +529,7 @@ |
527 | 529 | |
528 | 530 | switch (tmp & 0x30) { |
529 | 531 | case 0x00: |
530 | - /* On 100MHz clocking, try and switch to 133MHz */ | |
532 | + /* On 100 MHz clocking, try and switch to 133 MHz */ | |
531 | 533 | sil_iowrite8(dev, tmp | 0x10, scsc_addr); |
532 | 534 | break; |
533 | 535 | case 0x30: |
534 | 536 | |
... | ... | @@ -543,12 +545,12 @@ |
543 | 545 | |
544 | 546 | tmp = sil_ioread8(dev, scsc_addr); |
545 | 547 | |
546 | - sil_iowrite8(dev, 0x72, base + 0xA1); | |
548 | + sil_iowrite8 (dev, 0x72, base + 0xA1); | |
547 | 549 | sil_iowrite16(dev, 0x328A, base + 0xA2); |
548 | 550 | sil_iowrite32(dev, 0x62DD62DD, base + 0xA4); |
549 | 551 | sil_iowrite32(dev, 0x43924392, base + 0xA8); |
550 | 552 | sil_iowrite32(dev, 0x40094009, base + 0xAC); |
551 | - sil_iowrite8(dev, 0x72, base ? (base + 0xE1) : 0xB1); | |
553 | + sil_iowrite8 (dev, 0x72, base ? (base + 0xE1) : 0xB1); | |
552 | 554 | sil_iowrite16(dev, 0x328A, base ? (base + 0xE2) : 0xB2); |
553 | 555 | sil_iowrite32(dev, 0x62DD62DD, base ? (base + 0xE4) : 0xB4); |
554 | 556 | sil_iowrite32(dev, 0x43924392, base ? (base + 0xE8) : 0xB8); |
... | ... | @@ -579,8 +581,7 @@ |
579 | 581 | * |
580 | 582 | * The basic setup here is fairly simple, we can use standard MMIO |
581 | 583 | * operations. However we do have to set the taskfile register offsets |
582 | - * by hand as there isnt a standard defined layout for them this | |
583 | - * time. | |
584 | + * by hand as there isn't a standard defined layout for them this time. | |
584 | 585 | * |
585 | 586 | * The hardware supports buffered taskfiles and also some rather nice |
586 | 587 | * extended PRD tables. For better SI3112 support use the libata driver |
587 | 588 | |
588 | 589 | |
589 | 590 | |
590 | 591 | |
591 | 592 | |
592 | 593 | |
... | ... | @@ -591,24 +592,20 @@ |
591 | 592 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
592 | 593 | void *addr = pci_get_drvdata(dev); |
593 | 594 | u8 ch = hwif->channel; |
594 | - unsigned long base; | |
595 | - | |
596 | 595 | struct ide_io_ports *io_ports = &hwif->io_ports; |
596 | + unsigned long base; | |
597 | 597 | |
598 | 598 | /* |
599 | - * Fill in the basic HWIF bits | |
599 | + * Fill in the basic hwif bits | |
600 | 600 | */ |
601 | - | |
602 | 601 | hwif->host_flags |= IDE_HFLAG_MMIO; |
603 | 602 | default_hwif_mmiops(hwif); |
604 | - hwif->hwif_data = addr; | |
603 | + hwif->hwif_data = addr; | |
605 | 604 | |
606 | 605 | /* |
607 | - * Now set up the hw. We have to do this ourselves as | |
608 | - * the MMIO layout isnt the same as the standard port | |
609 | - * based I/O | |
606 | + * Now set up the hw. We have to do this ourselves as the | |
607 | + * MMIO layout isn't the same as the standard port based I/O. | |
610 | 608 | */ |
611 | - | |
612 | 609 | memset(io_ports, 0, sizeof(*io_ports)); |
613 | 610 | |
614 | 611 | base = (unsigned long)addr; |
... | ... | @@ -618,10 +615,9 @@ |
618 | 615 | base += 0x80; |
619 | 616 | |
620 | 617 | /* |
621 | - * The buffered task file doesn't have status/control | |
622 | - * so we can't currently use it sanely since we want to | |
623 | - * use LBA48 mode. | |
624 | - */ | |
618 | + * The buffered task file doesn't have status/control, so we | |
619 | + * can't currently use it sanely since we want to use LBA48 mode. | |
620 | + */ | |
625 | 621 | io_ports->data_addr = base; |
626 | 622 | io_ports->error_addr = base + 1; |
627 | 623 | io_ports->nsect_addr = base + 2; |
628 | 624 | |
629 | 625 | |
... | ... | @@ -650,19 +646,17 @@ |
650 | 646 | |
651 | 647 | static int is_dev_seagate_sata(ide_drive_t *drive) |
652 | 648 | { |
653 | - const char *s = &drive->id->model[0]; | |
654 | - unsigned len; | |
649 | + const char *s = &drive->id->model[0]; | |
650 | + unsigned len = strnlen(s, sizeof(drive->id->model)); | |
655 | 651 | |
656 | - len = strnlen(s, sizeof(drive->id->model)); | |
657 | - | |
658 | - if ((len > 4) && (!memcmp(s, "ST", 2))) { | |
652 | + if ((len > 4) && (!memcmp(s, "ST", 2))) | |
659 | 653 | if ((!memcmp(s + len - 2, "AS", 2)) || |
660 | 654 | (!memcmp(s + len - 3, "ASL", 3))) { |
661 | 655 | printk(KERN_INFO "%s: applying pessimistic Seagate " |
662 | 656 | "errata fix\n", drive->name); |
663 | 657 | return 1; |
664 | 658 | } |
665 | - } | |
659 | + | |
666 | 660 | return 0; |
667 | 661 | } |
668 | 662 | |
... | ... | @@ -679,7 +673,7 @@ |
679 | 673 | { |
680 | 674 | ide_hwif_t *hwif = drive->hwif; |
681 | 675 | |
682 | - /* Try and raise the rqsize */ | |
676 | + /* Try and rise the rqsize */ | |
683 | 677 | if (!is_sata(hwif) || !is_dev_seagate_sata(drive)) |
684 | 678 | hwif->rqsize = 128; |
685 | 679 | } |
686 | 680 | |
... | ... | @@ -713,15 +707,14 @@ |
713 | 707 | * sil_cable_detect - cable detection |
714 | 708 | * @hwif: interface to check |
715 | 709 | * |
716 | - * Check for the presence of an ATA66 capable cable on the | |
717 | - * interface. | |
710 | + * Check for the presence of an ATA66 capable cable on the interface. | |
718 | 711 | */ |
719 | 712 | |
720 | 713 | static u8 __devinit sil_cable_detect(ide_hwif_t *hwif) |
721 | 714 | { |
722 | - struct pci_dev *dev = to_pci_dev(hwif->dev); | |
723 | - unsigned long addr = siimage_selreg(hwif, 0); | |
724 | - u8 ata66 = sil_ioread8(dev, addr); | |
715 | + struct pci_dev *dev = to_pci_dev(hwif->dev); | |
716 | + unsigned long addr = siimage_selreg(hwif, 0); | |
717 | + u8 ata66 = sil_ioread8(dev, addr); | |
725 | 718 | |
726 | 719 | return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; |
727 | 720 | } |
728 | 721 | |
729 | 722 | |
... | ... | @@ -767,15 +760,16 @@ |
767 | 760 | }; |
768 | 761 | |
769 | 762 | /** |
770 | - * siimage_init_one - pci layer discovery entry | |
763 | + * siimage_init_one - PCI layer discovery entry | |
771 | 764 | * @dev: PCI device |
772 | 765 | * @id: ident table entry |
773 | 766 | * |
774 | - * Called by the PCI code when it finds an SI680 or SI3112 controller. | |
767 | + * Called by the PCI code when it finds an SiI680 or SiI3112 controller. | |
775 | 768 | * We then use the IDE PCI generic helper to do most of the work. |
776 | 769 | */ |
777 | - | |
778 | -static int __devinit siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
770 | + | |
771 | +static int __devinit siimage_init_one(struct pci_dev *dev, | |
772 | + const struct pci_device_id *id) | |
779 | 773 | { |
780 | 774 | struct ide_port_info d; |
781 | 775 | u8 idx = id->driver_data; |