mtd: nand: omap: Revert to using software ECC by default

For v3.12 and prior, 1-bit Hamming code ECC via software was the default choice. Commit c66d039197e4 in v3.13 changed the behaviour to use 1-bit Hamming code via Hardware using a different ECC layout i.e. (ROM code layout) than what is used by software ECC. This ECC layout change causes NAND filesystems created in v3.12 and prior to be unusable in v3.13 and later. So revert back to using software ECC by default if an ECC scheme is not explicitely specified. This defect can be observed on the following boards during legacy boot -omap3beagle -omap3touchbook -overo -am3517crane -devkit8000 -ldp -3430sdp Signed-off-by: Roger Quadros <rogerq@ti.com> Tested-by: Grazvydas Ignotas <notasas@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>

mtd: nand: omap: Revert to using software ECC by default
For v3.12 and prior, 1-bit Hamming code ECC via software was the default choice. Commit c66d039197e4 in v3.13 changed the behaviour to use 1-bit Hamming code via Hardware using a different ECC layout i.e. (ROM code layout) than what is used by software ECC. This ECC layout change causes NAND filesystems created in v3.12 and prior to be unusable in v3.13 and later. So revert back to using software ECC by default if an ECC scheme is not explicitely specified. This defect can be observed on the following boards during legacy boot -omap3beagle -omap3touchbook -overo -am3517crane -devkit8000 -ldp -3430sdp Signed-off-by: Roger Quadros <rogerq@ti.com> Tested-by: Grazvydas Ignotas <notasas@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Roger Quadros · Tony Lindgren · Eric Lee · Eric Lee · Eric Lee · Eric Lee
1 parent 52addcf9d6
Showing 4 changed files with 25 additions and 7 deletions Side-by-side Diff
arch/arm/mach-omap2/board-flash.c
arch/arm/mach-omap2/gpmc-nand.c
drivers/mtd/nand/omap2.c
include/linux/platform_data/mtd-nand-omap2.h
@@ -142,7 +142,7 @@
 	board_nand_data.nr_parts	= nr_parts;
 	board_nand_data.devsize		= nand_type;
  
-	board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_HW;
+	board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_SW;
 	gpmc_nand_init(&board_nand_data, gpmc_t);
 }
 #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
@@ -49,7 +49,8 @@
 		return 0;
  
 	/* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */
-	if (ecc_opt == OMAP_ECC_HAM1_CODE_HW)
+	if (ecc_opt == OMAP_ECC_HAM1_CODE_HW ||
+	    ecc_opt == OMAP_ECC_HAM1_CODE_SW)
 		return 1;
 	else
 		return 0;
@@ -1794,9 +1794,12 @@
 	}
  
 	/* populate MTD interface based on ECC scheme */
-	nand_chip->ecc.layout	= &omap_oobinfo;
 	ecclayout		= &omap_oobinfo;
 	switch (info->ecc_opt) {
+	case OMAP_ECC_HAM1_CODE_SW:
+		nand_chip->ecc.mode = NAND_ECC_SOFT;
+		break;
+
 	case OMAP_ECC_HAM1_CODE_HW:
 		pr_info("nand: using OMAP_ECC_HAM1_CODE_HW\n");
 		nand_chip->ecc.mode             = NAND_ECC_HW;
@@ -1848,7 +1851,7 @@
 		nand_chip->ecc.priv		= nand_bch_init(mtd,
 							nand_chip->ecc.size,
 							nand_chip->ecc.bytes,
-							&nand_chip->ecc.layout);
+							&ecclayout);
 		if (!nand_chip->ecc.priv) {
 			pr_err("nand: error: unable to use s/w BCH library\n");
 			err = -EINVAL;
@@ -1923,7 +1926,7 @@
 		nand_chip->ecc.priv		= nand_bch_init(mtd,
 							nand_chip->ecc.size,
 							nand_chip->ecc.bytes,
-							&nand_chip->ecc.layout);
+							&ecclayout);
 		if (!nand_chip->ecc.priv) {
 			pr_err("nand: error: unable to use s/w BCH library\n");
 			err = -EINVAL;
@@ -2012,6 +2015,9 @@
 		goto return_error;
 	}
  
+	if (info->ecc_opt == OMAP_ECC_HAM1_CODE_SW)
+		goto scan_tail;
+
 	/* all OOB bytes from oobfree->offset till end off OOB are free */
 	ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset;
 	/* check if NAND device's OOB is enough to store ECC signatures */
  
@@ -2021,7 +2027,9 @@
 		err = -EINVAL;
 		goto return_error;
 	}
+	nand_chip->ecc.layout = ecclayout;
  
+scan_tail:
 	/* second phase scan */
 	if (nand_scan_tail(mtd)) {
 		err = -ENXIO;
@@ -21,8 +21,17 @@
 };
  
 enum omap_ecc {
-	/* 1-bit  ECC calculation by GPMC, Error detection by Software */
-	OMAP_ECC_HAM1_CODE_HW = 0,
+	/*
+	 * 1-bit ECC: calculation and correction by SW
+	 * ECC stored at end of spare area
+	 */
+	OMAP_ECC_HAM1_CODE_SW = 0,
+
+	/*
+	 * 1-bit ECC: calculation by GPMC, Error detection by Software
+	 * ECC layout compatible with ROM code layout
+	 */
+	OMAP_ECC_HAM1_CODE_HW,
 	/* 4-bit  ECC calculation by GPMC, Error detection by Software */
 	OMAP_ECC_BCH4_CODE_HW_DETECTION_SW,
 	/* 4-bit  ECC calculation by GPMC, Error detection by ELM */
...	...	@@ -142,7 +142,7 @@
142	142	board_nand_data.nr_parts = nr_parts;
143	143	board_nand_data.devsize = nand_type;
144	144
145		- board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_HW;
	145	+ board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_SW;
146	146	gpmc_nand_init(&board_nand_data, gpmc_t);
147	147	}
148	148	#endif /* CONFIG_MTD_NAND_OMAP2 \|\| CONFIG_MTD_NAND_OMAP2_MODULE */
...	...	@@ -49,7 +49,8 @@
49	49	return 0;
50	50
51	51	/* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */
52		- if (ecc_opt == OMAP_ECC_HAM1_CODE_HW)
	52	+ if (ecc_opt == OMAP_ECC_HAM1_CODE_HW \|\|
	53	+ ecc_opt == OMAP_ECC_HAM1_CODE_SW)
53	54	return 1;
54	55	else
55	56	return 0;
...	...	@@ -1794,9 +1794,12 @@
1794	1794	}
1795	1795
1796	1796	/* populate MTD interface based on ECC scheme */
1797		- nand_chip->ecc.layout = &omap_oobinfo;
1798	1797	ecclayout = &omap_oobinfo;
1799	1798	switch (info->ecc_opt) {
	1799	+ case OMAP_ECC_HAM1_CODE_SW:
	1800	+ nand_chip->ecc.mode = NAND_ECC_SOFT;
	1801	+ break;
	1802	+
1800	1803	case OMAP_ECC_HAM1_CODE_HW:
1801	1804	pr_info("nand: using OMAP_ECC_HAM1_CODE_HW\n");
1802	1805	nand_chip->ecc.mode = NAND_ECC_HW;
...	...	@@ -1848,7 +1851,7 @@
1848	1851	nand_chip->ecc.priv = nand_bch_init(mtd,
1849	1852	nand_chip->ecc.size,
1850	1853	nand_chip->ecc.bytes,
1851		- &nand_chip->ecc.layout);
	1854	+ &ecclayout);
1852	1855	if (!nand_chip->ecc.priv) {
1853	1856	pr_err("nand: error: unable to use s/w BCH library\n");
1854	1857	err = -EINVAL;
...	...	@@ -1923,7 +1926,7 @@
1923	1926	nand_chip->ecc.priv = nand_bch_init(mtd,
1924	1927	nand_chip->ecc.size,
1925	1928	nand_chip->ecc.bytes,
1926		- &nand_chip->ecc.layout);
	1929	+ &ecclayout);
1927	1930	if (!nand_chip->ecc.priv) {
1928	1931	pr_err("nand: error: unable to use s/w BCH library\n");
1929	1932	err = -EINVAL;
...	...	@@ -2012,6 +2015,9 @@
2012	2015	goto return_error;
2013	2016	}
2014	2017
	2018	+ if (info->ecc_opt == OMAP_ECC_HAM1_CODE_SW)
	2019	+ goto scan_tail;
	2020	+
2015	2021	/* all OOB bytes from oobfree->offset till end off OOB are free */
2016	2022	ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset;
2017	2023	/* check if NAND device's OOB is enough to store ECC signatures */
2018	2024
...	...	@@ -2021,7 +2027,9 @@
2021	2027	err = -EINVAL;
2022	2028	goto return_error;
2023	2029	}
	2030	+ nand_chip->ecc.layout = ecclayout;
2024	2031
	2032	+scan_tail:
2025	2033	/* second phase scan */
2026	2034	if (nand_scan_tail(mtd)) {
2027	2035	err = -ENXIO;
...	...	@@ -21,8 +21,17 @@
21	21	};
22	22
23	23	enum omap_ecc {
24		- /* 1-bit ECC calculation by GPMC, Error detection by Software */
25		- OMAP_ECC_HAM1_CODE_HW = 0,
	24	+ /*
	25	+ * 1-bit ECC: calculation and correction by SW
	26	+ * ECC stored at end of spare area
	27	+ */
	28	+ OMAP_ECC_HAM1_CODE_SW = 0,
	29	+
	30	+ /*
	31	+ * 1-bit ECC: calculation by GPMC, Error detection by Software
	32	+ * ECC layout compatible with ROM code layout
	33	+ */
	34	+ OMAP_ECC_HAM1_CODE_HW,
26	35	/* 4-bit ECC calculation by GPMC, Error detection by Software */
27	36	OMAP_ECC_BCH4_CODE_HW_DETECTION_SW,
28	37	/* 4-bit ECC calculation by GPMC, Error detection by ELM */