Eric Lee / smarc-ti-linux-kernel

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Commit 7d8f159188410557630a7270efe3e14a1a305c2e

Authored by Kukjin Kim
1 parent 728599439f
Exists in master and in 16 other branches dlt-processor-sdk-linux-03.00.00.04, processor-sdk-linux-01.00.00, processor-sdk-linux-02.00.01, smarc-ti-linux-3.14.y, smarc-ti-linux-3.15.y, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04, ti-linux-3.14.y, ti-linux-3.15.y, ti-lsk-linux-4.1.y

PM / devfreq: move definitions for exynos4_bus into drivers/devfreq 

We don't need to keep the definitions for exynos4_bus into
mach-exynos/ so this moves them into drviers/devfreq with
adding header file.

Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

Showing 3 changed files with 112 additions and 96 deletions Side-by-side Diff

arch/arm/mach-exynos/include/mach/regs-clock.h
Diff comments   View file @ 7d8f159
... ... @@ -18,12 +18,6 @@
18 18  
19 19 #define EXYNOS_CLKREG(x) (S5P_VA_CMU + (x))
20 20  
21   -#define EXYNOS4_CLKDIV_LEFTBUS EXYNOS_CLKREG(0x04500)
22   -#define EXYNOS4_CLKDIV_STAT_LEFTBUS EXYNOS_CLKREG(0x04600)
23   -
24   -#define EXYNOS4_CLKDIV_RIGHTBUS EXYNOS_CLKREG(0x08500)
25   -#define EXYNOS4_CLKDIV_STAT_RIGHTBUS EXYNOS_CLKREG(0x08600)
26   -
27 21 #define EXYNOS4_EPLL_LOCK EXYNOS_CLKREG(0x0C010)
28 22 #define EXYNOS4_VPLL_LOCK EXYNOS_CLKREG(0x0C020)
29 23  
30 24  
31 25  
... ... @@ -41,25 +35,8 @@
41 35 #define EXYNOS4_CLKSRC_MASK_PERIL0 EXYNOS_CLKREG(0x0C350)
42 36 #define EXYNOS4_CLKSRC_MASK_PERIL1 EXYNOS_CLKREG(0x0C354)
43 37  
44   -#define EXYNOS4_CLKDIV_TOP EXYNOS_CLKREG(0x0C510)
45   -#define EXYNOS4_CLKDIV_CAM EXYNOS_CLKREG(0x0C520)
46   -#define EXYNOS4_CLKDIV_MFC EXYNOS_CLKREG(0x0C528)
47   -
48   -#define EXYNOS4_CLKDIV_STAT_TOP EXYNOS_CLKREG(0x0C610)
49   -#define EXYNOS4_CLKDIV_STAT_MFC EXYNOS_CLKREG(0x0C628)
50   -
51   -#define EXYNOS4210_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x0C930)
52   -#define EXYNOS4212_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x04930)
53   -
54 38 #define EXYNOS4_CLKSRC_MASK_DMC EXYNOS_CLKREG(0x10300)
55   -#define EXYNOS4_CLKDIV_DMC0 EXYNOS_CLKREG(0x10500)
56   -#define EXYNOS4_CLKDIV_DMC1 EXYNOS_CLKREG(0x10504)
57   -#define EXYNOS4_CLKDIV_STAT_DMC0 EXYNOS_CLKREG(0x10600)
58   -#define EXYNOS4_CLKDIV_STAT_DMC1 EXYNOS_CLKREG(0x10604)
59 39  
60   -#define EXYNOS4_DMC_PAUSE_CTRL EXYNOS_CLKREG(0x11094)
61   -#define EXYNOS4_DMC_PAUSE_ENABLE (1 << 0)
62   -
63 40 #define EXYNOS4_CLKSRC_CPU EXYNOS_CLKREG(0x14200)
64 41 #define EXYNOS4_CLKMUX_STATCPU EXYNOS_CLKREG(0x14400)
65 42  
66 43  
... ... @@ -74,80 +51,9 @@
74 51 #define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16)
75 52 #define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)
76 53  
77   -#define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0)
78   -#define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT)
79   -#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT (4)
80   -#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT)
81   -#define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT (8)
82   -#define EXYNOS4_CLKDIV_DMC0_DPHY_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT)
83   -#define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT (12)
84   -#define EXYNOS4_CLKDIV_DMC0_DMC_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT)
85   -#define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT (16)
86   -#define EXYNOS4_CLKDIV_DMC0_DMCD_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT)
87   -#define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT (20)
88   -#define EXYNOS4_CLKDIV_DMC0_DMCP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT)
89   -#define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT (24)
90   -#define EXYNOS4_CLKDIV_DMC0_COPY2_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT)
91   -#define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT (28)
92   -#define EXYNOS4_CLKDIV_DMC0_CORETI_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)
93   -
94   -#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT (0)
95   -#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK (0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT)
96   -#define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT (4)
97   -#define EXYNOS4_CLKDIV_DMC1_C2C_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT)
98   -#define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT (8)
99   -#define EXYNOS4_CLKDIV_DMC1_PWI_MASK (0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT)
100   -#define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT (12)
101   -#define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT)
102   -#define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT (16)
103   -#define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT)
104   -#define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT (24)
105   -#define EXYNOS4_CLKDIV_DMC1_DPM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT)
106   -
107   -#define EXYNOS4_CLKDIV_MFC_SHIFT (0)
108   -#define EXYNOS4_CLKDIV_MFC_MASK (0x7 << EXYNOS4_CLKDIV_MFC_SHIFT)
109   -
110   -#define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT (0)
111   -#define EXYNOS4_CLKDIV_TOP_ACLK200_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT)
112   -#define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT (4)
113   -#define EXYNOS4_CLKDIV_TOP_ACLK100_MASK (0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT)
114   -#define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT (8)
115   -#define EXYNOS4_CLKDIV_TOP_ACLK160_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT)
116   -#define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT (12)
117   -#define EXYNOS4_CLKDIV_TOP_ACLK133_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT)
118   -#define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT (16)
119   -#define EXYNOS4_CLKDIV_TOP_ONENAND_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)
120   -#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT (20)
121   -#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT)
122   -#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT (24)
123   -#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT)
124   -
125   -#define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT (0)
126   -#define EXYNOS4_CLKDIV_BUS_GDLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT)
127   -#define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT (4)
128   -#define EXYNOS4_CLKDIV_BUS_GPLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)
129   -
130   -#define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT (0)
131   -#define EXYNOS4_CLKDIV_CAM_FIMC0_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT)
132   -#define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT (4)
133   -#define EXYNOS4_CLKDIV_CAM_FIMC1_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT)
134   -#define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT (8)
135   -#define EXYNOS4_CLKDIV_CAM_FIMC2_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT)
136   -#define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT (12)
137   -#define EXYNOS4_CLKDIV_CAM_FIMC3_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT)
138   -
139 54 /* Only for EXYNOS4210 */
140 55  
141 56 #define EXYNOS4210_CLKSRC_MASK_LCD1 EXYNOS_CLKREG(0x0C338)
142   -
143   -/* Only for EXYNOS4212 */
144   -
145   -#define EXYNOS4_CLKDIV_CAM1 EXYNOS_CLKREG(0x0C568)
146   -
147   -#define EXYNOS4_CLKDIV_STAT_CAM1 EXYNOS_CLKREG(0x0C668)
148   -
149   -#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0)
150   -#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
151 57  
152 58 /* For EXYNOS5250 */
153 59  
drivers/devfreq/exynos/exynos4_bus.c
Diff comments   View file @ 7d8f159
... ... @@ -30,9 +30,9 @@
30 30 extern unsigned int exynos_result_of_asv;
31 31 #endif
32 32  
33   -#include <mach/regs-clock.h>
34   -
35 33 #include <plat/map-s5p.h>
  34 +
  35 +#include "exynos4_bus.h"
36 36  
37 37 #define MAX_SAFEVOLT 1200000 /* 1.2V */
38 38  
drivers/devfreq/exynos/exynos4_bus.h
Diff comments   View file @ 7d8f159
  1 +/*
  2 + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  3 + * http://www.samsung.com/
  4 + *
  5 + * EXYNOS4 BUS header
  6 + *
  7 + * This program is free software; you can redistribute it and/or modify
  8 + * it under the terms of the GNU General Public License version 2 as
  9 + * published by the Free Software Foundation.
  10 +*/
  11 +
  12 +#ifndef __DEVFREQ_EXYNOS4_BUS_H
  13 +#define __DEVFREQ_EXYNOS4_BUS_H __FILE__
  14 +
  15 +#include <mach/map.h>
  16 +
  17 +#define EXYNOS4_CLKDIV_LEFTBUS (S5P_VA_CMU + 0x04500)
  18 +#define EXYNOS4_CLKDIV_STAT_LEFTBUS (S5P_VA_CMU + 0x04600)
  19 +
  20 +#define EXYNOS4_CLKDIV_RIGHTBUS (S5P_VA_CMU + 0x08500)
  21 +#define EXYNOS4_CLKDIV_STAT_RIGHTBUS (S5P_VA_CMU + 0x08600)
  22 +
  23 +#define EXYNOS4_CLKDIV_TOP (S5P_VA_CMU + 0x0C510)
  24 +#define EXYNOS4_CLKDIV_CAM (S5P_VA_CMU + 0x0C520)
  25 +#define EXYNOS4_CLKDIV_MFC (S5P_VA_CMU + 0x0C528)
  26 +
  27 +#define EXYNOS4_CLKDIV_STAT_TOP (S5P_VA_CMU + 0x0C610)
  28 +#define EXYNOS4_CLKDIV_STAT_MFC (S5P_VA_CMU + 0x0C628)
  29 +
  30 +#define EXYNOS4210_CLKGATE_IP_IMAGE (S5P_VA_CMU + 0x0C930)
  31 +#define EXYNOS4212_CLKGATE_IP_IMAGE (S5P_VA_CMU + 0x04930)
  32 +
  33 +#define EXYNOS4_CLKDIV_DMC0 (S5P_VA_CMU + 0x10500)
  34 +#define EXYNOS4_CLKDIV_DMC1 (S5P_VA_CMU + 0x10504)
  35 +#define EXYNOS4_CLKDIV_STAT_DMC0 (S5P_VA_CMU + 0x10600)
  36 +#define EXYNOS4_CLKDIV_STAT_DMC1 (S5P_VA_CMU + 0x10604)
  37 +
  38 +#define EXYNOS4_DMC_PAUSE_CTRL (S5P_VA_CMU + 0x11094)
  39 +#define EXYNOS4_DMC_PAUSE_ENABLE (1 << 0)
  40 +
  41 +#define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0)
  42 +#define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT)
  43 +#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT (4)
  44 +#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT)
  45 +#define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT (8)
  46 +#define EXYNOS4_CLKDIV_DMC0_DPHY_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT)
  47 +#define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT (12)
  48 +#define EXYNOS4_CLKDIV_DMC0_DMC_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT)
  49 +#define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT (16)
  50 +#define EXYNOS4_CLKDIV_DMC0_DMCD_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT)
  51 +#define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT (20)
  52 +#define EXYNOS4_CLKDIV_DMC0_DMCP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT)
  53 +#define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT (24)
  54 +#define EXYNOS4_CLKDIV_DMC0_COPY2_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT)
  55 +#define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT (28)
  56 +#define EXYNOS4_CLKDIV_DMC0_CORETI_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)
  57 +
  58 +#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT (0)
  59 +#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK (0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT)
  60 +#define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT (4)
  61 +#define EXYNOS4_CLKDIV_DMC1_C2C_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT)
  62 +#define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT (8)
  63 +#define EXYNOS4_CLKDIV_DMC1_PWI_MASK (0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT)
  64 +#define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT (12)
  65 +#define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT)
  66 +#define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT (16)
  67 +#define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT)
  68 +#define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT (24)
  69 +#define EXYNOS4_CLKDIV_DMC1_DPM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT)
  70 +
  71 +#define EXYNOS4_CLKDIV_MFC_SHIFT (0)
  72 +#define EXYNOS4_CLKDIV_MFC_MASK (0x7 << EXYNOS4_CLKDIV_MFC_SHIFT)
  73 +
  74 +#define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT (0)
  75 +#define EXYNOS4_CLKDIV_TOP_ACLK200_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT)
  76 +#define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT (4)
  77 +#define EXYNOS4_CLKDIV_TOP_ACLK100_MASK (0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT)
  78 +#define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT (8)
  79 +#define EXYNOS4_CLKDIV_TOP_ACLK160_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT)
  80 +#define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT (12)
  81 +#define EXYNOS4_CLKDIV_TOP_ACLK133_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT)
  82 +#define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT (16)
  83 +#define EXYNOS4_CLKDIV_TOP_ONENAND_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)
  84 +#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT (20)
  85 +#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT)
  86 +#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT (24)
  87 +#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT)
  88 +
  89 +#define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT (0)
  90 +#define EXYNOS4_CLKDIV_BUS_GDLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT)
  91 +#define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT (4)
  92 +#define EXYNOS4_CLKDIV_BUS_GPLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)
  93 +
  94 +#define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT (0)
  95 +#define EXYNOS4_CLKDIV_CAM_FIMC0_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT)
  96 +#define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT (4)
  97 +#define EXYNOS4_CLKDIV_CAM_FIMC1_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT)
  98 +#define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT (8)
  99 +#define EXYNOS4_CLKDIV_CAM_FIMC2_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT)
  100 +#define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT (12)
  101 +#define EXYNOS4_CLKDIV_CAM_FIMC3_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT)
  102 +
  103 +#define EXYNOS4_CLKDIV_CAM1 (S5P_VA_CMU + 0x0C568)
  104 +
  105 +#define EXYNOS4_CLKDIV_STAT_CAM1 (S5P_VA_CMU + 0x0C668)
  106 +
  107 +#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0)
  108 +#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
  109 +
  110 +#endif /* __DEVFREQ_EXYNOS4_BUS_H */