Eric Lee / smarc-ti-linux-kernel

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Commit 7d9207c12182b07be4bffe6083e9ff4074a6ff91

Authored by Dave Gerlach
Committed by Tero Kristo
1 parent 0e09d43c21
Exists in ti-linux-3.12.y and in 3 other branches newt-ti-linux-3.12.y, smarc-ti-linux-3.12.10, smarc-ti-linux-3.12.y

ARM: dts: am43xx: Remove MPU DS0 voltage scaling 

Currently am43xx handles MPU voltage scaling to 0.95v during sleep using
CM3 firmware to write sequence to PMIC. This creates a problem during
resume because sequence written to scale the voltage back is fixed at
1.1v which may not agree with cpufreq governor. Because of the conflict
here MPU voltage should be scaled manually to lowest OPP with cpufreq
before suspend rather than doing it here.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>

Showing 2 changed files with 0 additions and 8 deletions Side-by-side Diff

arch/arm/boot/dts/am437x-gp-evm.dts
Diff comments   View file @ 7d9207c
... ... @@ -52,8 +52,6 @@
52 52 sleep-sequence = /bits/ 8 <
53 53 0x02 0x24 0x10 0x6b /* Password unlock 1 */
54 54 0x02 0x24 0x16 0x8A /* Set DCDC1 (Core) to 0.95V */
55   - 0x02 0x24 0x10 0x6A /* Password unlock 2 */
56   - 0x02 0x24 0x17 0x8A /* Set DCDC2 (MPU) to 0.95V */
57 55 0x02 0x24 0x10 0x67 /* Password unlock 3 */
58 56 0x02 0x24 0x1A 0x86 /* Apply DCDC changes */
59 57 >;
... ... @@ -62,8 +60,6 @@
62 60 wake-sequence = /bits/ 8 <
63 61 0x02 0x24 0x10 0x6B /* Password unlock 2 */
64 62 0x02 0x24 0x16 0x99 /* Set DCDC1 (Core) to 1.1V */
65   - 0x02 0x24 0x10 0x6A /* Password unlock 1 */
66   - 0x02 0x24 0x17 0x99 /* Set DCDC2 (MPU)to 1.1V */
67 63 0x02 0x24 0x10 0x67 /* Password unlock 3 */
68 64 0x02 0x24 0x1A 0x86 /* Apply DCDC changes */
69 65 >;
arch/arm/boot/dts/am43x-epos-evm.dts
Diff comments   View file @ 7d9207c
... ... @@ -43,8 +43,6 @@
43 43 sleep-sequence = /bits/ 8 <
44 44 0x02 0x24 0x10 0x6b /* Password unlock 1 */
45 45 0x02 0x24 0x16 0x8A /* Set DCDC1 (Core) to 0.95V */
46   - 0x02 0x24 0x10 0x6A /* Password unlock 2 */
47   - 0x02 0x24 0x17 0x8A /* Set DCDC2 (MPU) to 0.95V */
48 46 0x02 0x24 0x10 0x67 /* Password unlock 3 */
49 47 0x02 0x24 0x1A 0x86 /* Apply DCDC changes */
50 48 >;
... ... @@ -53,8 +51,6 @@
53 51 wake-sequence = /bits/ 8 <
54 52 0x02 0x24 0x10 0x6B /* Password unlock 2 */
55 53 0x02 0x24 0x16 0x99 /* Set DCDC1 (Core) to 1.1V */
56   - 0x02 0x24 0x10 0x6A /* Password unlock 1 */
57   - 0x02 0x24 0x17 0x99 /* Set DCDC2 (MPU)to 1.1V */
58 54 0x02 0x24 0x10 0x67 /* Password unlock 3 */
59 55 0x02 0x24 0x1A 0x86 /* Apply DCDC changes */
60 56 >;