Merge branch 'ti-linux-4.1.y' of git.ti.com:ti-linux-kernel/ti-linux-kernel into ti-lsk-linux-4.1.y

TI-Feature: ti_linux_base_lsk TI-Tree: git@git.ti.com:ti-linux-kernel/ti-linux-kernel.git TI-Branch: ti-linux-4.1.y * 'ti-linux-4.1.y' of git.ti.com:ti-linux-kernel/ti-linux-kernel: gpio: omap: convert to use generic irq handler gpio: omap: move pm runtime in irq_chip.irq_bus_lock/sync_unlock gpio: omap: fix static checker warning gpio: omap: Fix GPIO numbering for deferred probe gpio: omap: Fix gpiochip_add() handling for deferred probe ARM: OMAP2+: pm33xx-core: Disable off_mode for am335x Signed-off-by: Texas Instruments Auto Merger <lcpd_integration@list.ti.com>

Merge branch 'ti-linux-4.1.y' of git.ti.com:ti-linux-kernel/ti-linux-kernel into ti-lsk-linux-4.1.y
TI-Feature: ti_linux_base_lsk TI-Tree: git@git.ti.com:ti-linux-kernel/ti-linux-kernel.git TI-Branch: ti-linux-4.1.y * 'ti-linux-4.1.y' of git.ti.com:ti-linux-kernel/ti-linux-kernel: gpio: omap: convert to use generic irq handler gpio: omap: move pm runtime in irq_chip.irq_bus_lock/sync_unlock gpio: omap: fix static checker warning gpio: omap: Fix GPIO numbering for deferred probe gpio: omap: Fix gpiochip_add() handling for deferred probe ARM: OMAP2+: pm33xx-core: Disable off_mode for am335x Signed-off-by: Texas Instruments Auto Merger <lcpd_integration@list.ti.com>
Texas Instruments Auto Merger
2 parents 1a38c95b5c af44d54d3c
Showing 2 changed files Side-by-side Diff
arch/arm/mach-omap2/pm33xx-core.c
drivers/gpio/gpio-omap.c
@@ -52,6 +52,12 @@
 	return 0;
 }
  
+static int am33xx_check_off_mode_enable(void)
+{
+	/* off mode not supported on am335x so return 0 always */
+	return 0;
+}
+
 static int am43xx_check_off_mode_enable(void)
 {
 	return enable_off_mode;
@@ -260,7 +266,7 @@
 	.restore_context = am33xx_restore_context,
 	.prepare_rtc_suspend = am43xx_prepare_rtc_suspend,
 	.prepare_rtc_resume = am43xx_prepare_rtc_resume,
-	.check_off_mode_enable = am43xx_check_off_mode_enable,
+	.check_off_mode_enable = am33xx_check_off_mode_enable,
 	.get_rtc_base_addr = am43xx_get_rtc_base_addr,
 };
  
@@ -51,7 +51,7 @@
 struct gpio_bank {
 	struct list_head node;
 	void __iomem *base;
-	u16 irq;
+	int irq;
 	u32 non_wakeup_gpios;
 	u32 enabled_non_wakeup_gpios;
 	struct gpio_regs context;
@@ -59,6 +59,7 @@
 	u32 level_mask;
 	u32 toggle_mask;
 	raw_spinlock_t lock;
+	raw_spinlock_t wa_lock;
 	struct gpio_chip chip;
 	struct clk *dbck;
 	u32 mod_usage;
@@ -496,9 +497,6 @@
 		(type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
 		return -EINVAL;
  
-	if (!BANK_USED(bank))
-		pm_runtime_get_sync(bank->dev);
-
 	raw_spin_lock_irqsave(&bank->lock, flags);
 	retval = omap_set_gpio_triggering(bank, offset, type);
 	if (retval) {
@@ -521,8 +519,6 @@
 	return 0;
  
 error:
-	if (!BANK_USED(bank))
-		pm_runtime_put(bank->dev);
 	return retval;
 }
  
  
@@ -654,8 +650,13 @@
 {
 	struct gpio_bank *bank = omap_irq_data_get_bank(d);
 	unsigned offset = d->hwirq;
+	int ret;
  
-	return omap_set_gpio_wakeup(bank, offset, enable);
+	ret = omap_set_gpio_wakeup(bank, offset, enable);
+	if (!ret)
+		ret = irq_set_irq_wake(bank->irq, enable);
+
+	return ret;
 }
  
 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
  
  
  
  
@@ -709,26 +710,21 @@
  * line's interrupt handler has been run, we may miss some nested
  * interrupts.
  */
-static void omap_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
+static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
 {
 	void __iomem *isr_reg = NULL;
 	u32 isr;
 	unsigned int bit;
-	struct gpio_bank *bank;
-	int unmasked = 0;
-	struct irq_chip *irqchip = irq_desc_get_chip(desc);
-	struct gpio_chip *chip = irq_get_handler_data(irq);
+	struct gpio_bank *bank = gpiobank;
+	unsigned long wa_lock_flags;
 	unsigned long lock_flags;
  
-	chained_irq_enter(irqchip, desc);
-
-	bank = container_of(chip, struct gpio_bank, chip);
 	isr_reg = bank->base + bank->regs->irqstatus;
-	pm_runtime_get_sync(bank->dev);
-
 	if (WARN_ON(!isr_reg))
 		goto exit;
  
+	pm_runtime_get_sync(bank->dev);
+
 	while (1) {
 		u32 isr_saved, level_mask = 0;
 		u32 enabled;
@@ -750,13 +746,6 @@
  
 		raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
  
-		/* if there is only edge sensitive GPIO pin interrupts
-		configured, we could unmask GPIO bank interrupt immediately */
-		if (!level_mask && !unmasked) {
-			unmasked = 1;
-			chained_irq_exit(irqchip, desc);
-		}
-
 		if (!isr)
 			break;
  
  
  
  
  
@@ -777,18 +766,18 @@
  
 			raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
  
+			raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
+
 			generic_handle_irq(irq_find_mapping(bank->chip.irqdomain,
 							    bit));
+
+			raw_spin_unlock_irqrestore(&bank->wa_lock,
+						   wa_lock_flags);
 		}
 	}
-	/* if bank has any level sensitive GPIO pin interrupt
-	configured, we must unmask the bank interrupt only after
-	handler(s) are executed in order to avoid spurious bank
-	interrupt */
 exit:
-	if (!unmasked)
-		chained_irq_exit(irqchip, desc);
 	pm_runtime_put(bank->dev);
+	return IRQ_HANDLED;
 }
  
 static unsigned int omap_gpio_irq_startup(struct irq_data *d)
@@ -797,9 +786,6 @@
 	unsigned long flags;
 	unsigned offset = d->hwirq;
  
-	if (!BANK_USED(bank))
-		pm_runtime_get_sync(bank->dev);
-
 	raw_spin_lock_irqsave(&bank->lock, flags);
  
 	if (!LINE_USED(bank->mod_usage, offset))
@@ -815,8 +801,6 @@
 	return 0;
 err:
 	raw_spin_unlock_irqrestore(&bank->lock, flags);
-	if (!BANK_USED(bank))
-		pm_runtime_put(bank->dev);
 	return -EINVAL;
 }
  
  
@@ -835,7 +819,20 @@
 		omap_clear_gpio_debounce(bank, offset);
 	omap_disable_gpio_module(bank, offset);
 	raw_spin_unlock_irqrestore(&bank->lock, flags);
+}
  
+static void omap_gpio_irq_bus_lock(struct irq_data *data)
+{
+	struct gpio_bank *bank = omap_irq_data_get_bank(data);
+
+	if (!BANK_USED(bank))
+		pm_runtime_get_sync(bank->dev);
+}
+
+static void gpio_irq_bus_sync_unlock(struct irq_data *data)
+{
+	struct gpio_bank *bank = omap_irq_data_get_bank(data);
+
 	/*
 	 * If this is the last IRQ to be freed in the bank,
 	 * disable the bank module.
@@ -1098,7 +1095,6 @@
 	} else {
 		bank->chip.label = "gpio";
 		bank->chip.base = gpio;
-		gpio += bank->width;
 	}
 	bank->chip.ngpio = bank->width;
  
@@ -1108,6 +1104,9 @@
 		return ret;
 	}
  
+	if (!bank->is_mpuio)
+		gpio += bank->width;
+
 #ifdef CONFIG_ARCH_OMAP1
 	/*
 	 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
@@ -1130,7 +1129,7 @@
 	}
  
 	ret = gpiochip_irqchip_add(&bank->chip, irqc,
-				   irq_base, omap_gpio_irq_handler,
+				   irq_base, handle_bad_irq,
 				   IRQ_TYPE_NONE);
  
 	if (ret) {
  
@@ -1139,10 +1138,14 @@
 		return -ENODEV;
 	}
  
-	gpiochip_set_chained_irqchip(&bank->chip, irqc,
-				     bank->irq, omap_gpio_irq_handler);
+	gpiochip_set_chained_irqchip(&bank->chip, irqc, bank->irq, NULL);
  
-	return 0;
+	ret = devm_request_irq(bank->dev, bank->irq, omap_gpio_irq_handler,
+			       0, dev_name(bank->dev), bank);
+	if (ret)
+		gpiochip_remove(&bank->chip);
+
+	return ret;
 }
  
 static const struct of_device_id omap_gpio_match[];
@@ -1181,6 +1184,8 @@
 	irqc->irq_unmask = omap_gpio_unmask_irq,
 	irqc->irq_set_type = omap_gpio_irq_type,
 	irqc->irq_set_wake = omap_gpio_wake_enable,
+	irqc->irq_bus_lock = omap_gpio_irq_bus_lock,
+	irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
 	irqc->name = dev_name(&pdev->dev);
  
 	bank->irq = platform_get_irq(pdev, 0);
@@ -1216,6 +1221,7 @@
 		bank->set_dataout = omap_set_gpio_dataout_mask;
  
 	raw_spin_lock_init(&bank->lock);
+	raw_spin_lock_init(&bank->wa_lock);
  
 	/* Static mapping, never released */
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  
@@ -1247,8 +1253,11 @@
 	omap_gpio_mod_init(bank);
  
 	ret = omap_gpio_chip_init(bank, irqc);
-	if (ret)
+	if (ret) {
+		pm_runtime_put_sync(bank->dev);
+		pm_runtime_disable(bank->dev);
 		return ret;
+	}
  
 	omap_gpio_show_rev(bank);
...	...	@@ -52,6 +52,12 @@
52	52	return 0;
53	53	}
54	54
	55	+static int am33xx_check_off_mode_enable(void)
	56	+{
	57	+ /* off mode not supported on am335x so return 0 always */
	58	+ return 0;
	59	+}
	60	+
55	61	static int am43xx_check_off_mode_enable(void)
56	62	{
57	63	return enable_off_mode;
...	...	@@ -260,7 +266,7 @@
260	266	.restore_context = am33xx_restore_context,
261	267	.prepare_rtc_suspend = am43xx_prepare_rtc_suspend,
262	268	.prepare_rtc_resume = am43xx_prepare_rtc_resume,
263		- .check_off_mode_enable = am43xx_check_off_mode_enable,
	269	+ .check_off_mode_enable = am33xx_check_off_mode_enable,
264	270	.get_rtc_base_addr = am43xx_get_rtc_base_addr,
265	271	};
266	272
...	...	@@ -51,7 +51,7 @@
51	51	struct gpio_bank {
52	52	struct list_head node;
53	53	void __iomem *base;
54		- u16 irq;
	54	+ int irq;
55	55	u32 non_wakeup_gpios;
56	56	u32 enabled_non_wakeup_gpios;
57	57	struct gpio_regs context;
...	...	@@ -59,6 +59,7 @@
59	59	u32 level_mask;
60	60	u32 toggle_mask;
61	61	raw_spinlock_t lock;
	62	+ raw_spinlock_t wa_lock;
62	63	struct gpio_chip chip;
63	64	struct clk *dbck;
64	65	u32 mod_usage;
...	...	@@ -496,9 +497,6 @@
496	497	(type & (IRQ_TYPE_LEVEL_LOW\|IRQ_TYPE_LEVEL_HIGH)))
497	498	return -EINVAL;
498	499
499		- if (!BANK_USED(bank))
500		- pm_runtime_get_sync(bank->dev);
501		-
502	500	raw_spin_lock_irqsave(&bank->lock, flags);
503	501	retval = omap_set_gpio_triggering(bank, offset, type);
504	502	if (retval) {
...	...	@@ -521,8 +519,6 @@
521	519	return 0;
522	520
523	521	error:
524		- if (!BANK_USED(bank))
525		- pm_runtime_put(bank->dev);
526	522	return retval;
527	523	}
528	524
529	525
...	...	@@ -654,8 +650,13 @@
654	650	{
655	651	struct gpio_bank *bank = omap_irq_data_get_bank(d);
656	652	unsigned offset = d->hwirq;
	653	+ int ret;
657	654
658		- return omap_set_gpio_wakeup(bank, offset, enable);
	655	+ ret = omap_set_gpio_wakeup(bank, offset, enable);
	656	+ if (!ret)
	657	+ ret = irq_set_irq_wake(bank->irq, enable);
	658	+
	659	+ return ret;
659	660	}
660	661
661	662	static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
662	663
663	664
664	665
665	666
...	...	@@ -709,26 +710,21 @@
709	710	* line's interrupt handler has been run, we may miss some nested
710	711	* interrupts.
711	712	*/
712		-static void omap_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
	713	+static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
713	714	{
714	715	void __iomem *isr_reg = NULL;
715	716	u32 isr;
716	717	unsigned int bit;
717		- struct gpio_bank *bank;
718		- int unmasked = 0;
719		- struct irq_chip *irqchip = irq_desc_get_chip(desc);
720		- struct gpio_chip *chip = irq_get_handler_data(irq);
	718	+ struct gpio_bank *bank = gpiobank;
	719	+ unsigned long wa_lock_flags;
721	720	unsigned long lock_flags;
722	721
723		- chained_irq_enter(irqchip, desc);
724		-
725		- bank = container_of(chip, struct gpio_bank, chip);
726	722	isr_reg = bank->base + bank->regs->irqstatus;
727		- pm_runtime_get_sync(bank->dev);
728		-
729	723	if (WARN_ON(!isr_reg))
730	724	goto exit;
731	725
	726	+ pm_runtime_get_sync(bank->dev);
	727	+
732	728	while (1) {
733	729	u32 isr_saved, level_mask = 0;
734	730	u32 enabled;
...	...	@@ -750,13 +746,6 @@
750	746
751	747	raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
752	748
753		- /* if there is only edge sensitive GPIO pin interrupts
754		- configured, we could unmask GPIO bank interrupt immediately */
755		- if (!level_mask && !unmasked) {
756		- unmasked = 1;
757		- chained_irq_exit(irqchip, desc);
758		- }
759		-
760	749	if (!isr)
761	750	break;
762	751
763	752
764	753
765	754
766	755
...	...	@@ -777,18 +766,18 @@
777	766
778	767	raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
779	768
	769	+ raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
	770	+
780	771	generic_handle_irq(irq_find_mapping(bank->chip.irqdomain,
781	772	bit));
	773	+
	774	+ raw_spin_unlock_irqrestore(&bank->wa_lock,
	775	+ wa_lock_flags);
782	776	}
783	777	}
784		- /* if bank has any level sensitive GPIO pin interrupt
785		- configured, we must unmask the bank interrupt only after
786		- handler(s) are executed in order to avoid spurious bank
787		- interrupt */
788	778	exit:
789		- if (!unmasked)
790		- chained_irq_exit(irqchip, desc);
791	779	pm_runtime_put(bank->dev);
	780	+ return IRQ_HANDLED;
792	781	}
793	782
794	783	static unsigned int omap_gpio_irq_startup(struct irq_data *d)
...	...	@@ -797,9 +786,6 @@
797	786	unsigned long flags;
798	787	unsigned offset = d->hwirq;
799	788
800		- if (!BANK_USED(bank))
801		- pm_runtime_get_sync(bank->dev);
802		-
803	789	raw_spin_lock_irqsave(&bank->lock, flags);
804	790
805	791	if (!LINE_USED(bank->mod_usage, offset))
...	...	@@ -815,8 +801,6 @@
815	801	return 0;
816	802	err:
817	803	raw_spin_unlock_irqrestore(&bank->lock, flags);
818		- if (!BANK_USED(bank))
819		- pm_runtime_put(bank->dev);
820	804	return -EINVAL;
821	805	}
822	806
823	807
...	...	@@ -835,7 +819,20 @@
835	819	omap_clear_gpio_debounce(bank, offset);
836	820	omap_disable_gpio_module(bank, offset);
837	821	raw_spin_unlock_irqrestore(&bank->lock, flags);
	822	+}
838	823
	824	+static void omap_gpio_irq_bus_lock(struct irq_data *data)
	825	+{
	826	+ struct gpio_bank *bank = omap_irq_data_get_bank(data);
	827	+
	828	+ if (!BANK_USED(bank))
	829	+ pm_runtime_get_sync(bank->dev);
	830	+}
	831	+
	832	+static void gpio_irq_bus_sync_unlock(struct irq_data *data)
	833	+{
	834	+ struct gpio_bank *bank = omap_irq_data_get_bank(data);
	835	+
839	836	/*
840	837	* If this is the last IRQ to be freed in the bank,
841	838	* disable the bank module.
...	...	@@ -1098,7 +1095,6 @@
1098	1095	} else {
1099	1096	bank->chip.label = "gpio";
1100	1097	bank->chip.base = gpio;
1101		- gpio += bank->width;
1102	1098	}
1103	1099	bank->chip.ngpio = bank->width;
1104	1100
...	...	@@ -1108,6 +1104,9 @@
1108	1104	return ret;
1109	1105	}
1110	1106
	1107	+ if (!bank->is_mpuio)
	1108	+ gpio += bank->width;
	1109	+
1111	1110	#ifdef CONFIG_ARCH_OMAP1
1112	1111	/*
1113	1112	* REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
...	...	@@ -1130,7 +1129,7 @@
1130	1129	}
1131	1130
1132	1131	ret = gpiochip_irqchip_add(&bank->chip, irqc,
1133		- irq_base, omap_gpio_irq_handler,
	1132	+ irq_base, handle_bad_irq,
1134	1133	IRQ_TYPE_NONE);
1135	1134
1136	1135	if (ret) {
1137	1136
...	...	@@ -1139,10 +1138,14 @@
1139	1138	return -ENODEV;
1140	1139	}
1141	1140
1142		- gpiochip_set_chained_irqchip(&bank->chip, irqc,
1143		- bank->irq, omap_gpio_irq_handler);
	1141	+ gpiochip_set_chained_irqchip(&bank->chip, irqc, bank->irq, NULL);
1144	1142
1145		- return 0;
	1143	+ ret = devm_request_irq(bank->dev, bank->irq, omap_gpio_irq_handler,
	1144	+ 0, dev_name(bank->dev), bank);
	1145	+ if (ret)
	1146	+ gpiochip_remove(&bank->chip);
	1147	+
	1148	+ return ret;
1146	1149	}
1147	1150
1148	1151	static const struct of_device_id omap_gpio_match[];
...	...	@@ -1181,6 +1184,8 @@
1181	1184	irqc->irq_unmask = omap_gpio_unmask_irq,
1182	1185	irqc->irq_set_type = omap_gpio_irq_type,
1183	1186	irqc->irq_set_wake = omap_gpio_wake_enable,
	1187	+ irqc->irq_bus_lock = omap_gpio_irq_bus_lock,
	1188	+ irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
1184	1189	irqc->name = dev_name(&pdev->dev);
1185	1190
1186	1191	bank->irq = platform_get_irq(pdev, 0);
...	...	@@ -1216,6 +1221,7 @@
1216	1221	bank->set_dataout = omap_set_gpio_dataout_mask;
1217	1222
1218	1223	raw_spin_lock_init(&bank->lock);
	1224	+ raw_spin_lock_init(&bank->wa_lock);
1219	1225
1220	1226	/* Static mapping, never released */
1221	1227	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1222	1228
...	...	@@ -1247,8 +1253,11 @@
1247	1253	omap_gpio_mod_init(bank);
1248	1254
1249	1255	ret = omap_gpio_chip_init(bank, irqc);
1250		- if (ret)
	1256	+ if (ret) {
	1257	+ pm_runtime_put_sync(bank->dev);
	1258	+ pm_runtime_disable(bank->dev);
1251	1259	return ret;
	1260	+ }
1252	1261
1253	1262	omap_gpio_show_rev(bank);
1254	1263