drm/i915: add new Haswell DIP controls registers

Haswell has different DIP control registers and offsets which we need to use for infoframes, which this patch adds. Note that this does not adds full DIP frames support, but only the basic functionality necessary for HDMI to work in early enablement. v2: replace infoframe handling with a debug message, proper support will be added via a patch from Paulo Zanoni later. Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-by: Paulo Zanoni <przanoni@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

drm/i915: add new Haswell DIP controls registers
Haswell has different DIP control registers and offsets which we need to use for infoframes, which this patch adds. Note that this does not adds full DIP frames support, but only the basic functionality necessary for HDMI to work in early enablement. v2: replace infoframe handling with a debug message, proper support will be added via a patch from Paulo Zanoni later. Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-by: Paulo Zanoni <przanoni@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Eugeni Dodonov · Daniel Vetter
1 parent 1833b13445
Showing 2 changed files with 55 additions and 0 deletions Side-by-side Diff
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_hdmi.c
@@ -3524,6 +3524,42 @@
 #define VLV_TVIDEO_DIP_GCP(pipe) \
 	_PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
  
+/* Haswell DIP controls */
+#define HSW_VIDEO_DIP_CTL_A		0x60200
+#define HSW_VIDEO_DIP_AVI_DATA_A	0x60220
+#define HSW_VIDEO_DIP_VS_DATA_A		0x60260
+#define HSW_VIDEO_DIP_SPD_DATA_A	0x602A0
+#define HSW_VIDEO_DIP_GMP_DATA_A	0x602E0
+#define HSW_VIDEO_DIP_VSC_DATA_A	0x60320
+#define HSW_VIDEO_DIP_AVI_ECC_A		0x60240
+#define HSW_VIDEO_DIP_VS_ECC_A		0x60280
+#define HSW_VIDEO_DIP_SPD_ECC_A		0x602C0
+#define HSW_VIDEO_DIP_GMP_ECC_A		0x60300
+#define HSW_VIDEO_DIP_VSC_ECC_A		0x60344
+#define HSW_VIDEO_DIP_GCP_A		0x60210
+
+#define HSW_VIDEO_DIP_CTL_B		0x61200
+#define HSW_VIDEO_DIP_AVI_DATA_B	0x61220
+#define HSW_VIDEO_DIP_VS_DATA_B		0x61260
+#define HSW_VIDEO_DIP_SPD_DATA_B	0x612A0
+#define HSW_VIDEO_DIP_GMP_DATA_B	0x612E0
+#define HSW_VIDEO_DIP_VSC_DATA_B	0x61320
+#define HSW_VIDEO_DIP_BVI_ECC_B		0x61240
+#define HSW_VIDEO_DIP_VS_ECC_B		0x61280
+#define HSW_VIDEO_DIP_SPD_ECC_B		0x612C0
+#define HSW_VIDEO_DIP_GMP_ECC_B		0x61300
+#define HSW_VIDEO_DIP_VSC_ECC_B		0x61344
+#define HSW_VIDEO_DIP_GCP_B		0x61210
+
+#define HSW_TVIDEO_DIP_CTL(pipe) \
+	 _PIPE(pipe, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B)
+#define HSW_TVIDEO_DIP_AVI_DATA(pipe) \
+	 _PIPE(pipe, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B)
+#define HSW_TVIDEO_DIP_SPD_DATA(pipe) \
+	 _PIPE(pipe, HSW_VIDEO_DIP_SPD_DATA_A, HSW_VIDEO_DIP_SPD_DATA_B)
+#define HSW_TVIDEO_DIP_GCP(pipe) \
+	_PIPE(pipe, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B)
+
 #define _TRANS_HTOTAL_B          0xe1000
 #define _TRANS_HBLANK_B          0xe1004
 #define _TRANS_HSYNC_B           0xe1008
@@ -277,6 +277,18 @@
 	I915_WRITE(reg, val);
 }
  
+static void hsw_write_infoframe(struct drm_encoder *encoder,
+				     struct dip_infoframe *frame)
+{
+	/* Not implemented yet, so avoid doing anything at all.
+	 * This is the placeholder for Paulo Zanoni's infoframe writing patch
+	 */
+	DRM_DEBUG_DRIVER("Attempting to write infoframe on Haswell, this is not implemented yet.\n");
+
+	return;
+
+}
+
 static void intel_set_infoframe(struct drm_encoder *encoder,
 				struct dip_infoframe *frame)
 {
@@ -660,6 +672,13 @@
 		intel_hdmi->write_infoframe = vlv_write_infoframe;
 		for_each_pipe(i)
 			I915_WRITE(VLV_TVIDEO_DIP_CTL(i), 0);
+	} else if (IS_HASWELL(dev)) {
+		/* FIXME: Haswell has a new set of DIP frame registers, but we are
+		 * just doing the minimal required for HDMI to work at this stage.
+		 */
+		intel_hdmi->write_infoframe = hsw_write_infoframe;
+		for_each_pipe(i)
+			I915_WRITE(HSW_TVIDEO_DIP_CTL(i), 0);
 	} else if (HAS_PCH_IBX(dev)) {
 		intel_hdmi->write_infoframe = ibx_write_infoframe;
 		for_each_pipe(i)
...	...	@@ -3524,6 +3524,42 @@
3524	3524	#define VLV_TVIDEO_DIP_GCP(pipe) \
3525	3525	_PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
3526	3526
	3527	+/* Haswell DIP controls */
	3528	+#define HSW_VIDEO_DIP_CTL_A 0x60200
	3529	+#define HSW_VIDEO_DIP_AVI_DATA_A 0x60220
	3530	+#define HSW_VIDEO_DIP_VS_DATA_A 0x60260
	3531	+#define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
	3532	+#define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
	3533	+#define HSW_VIDEO_DIP_VSC_DATA_A 0x60320
	3534	+#define HSW_VIDEO_DIP_AVI_ECC_A 0x60240
	3535	+#define HSW_VIDEO_DIP_VS_ECC_A 0x60280
	3536	+#define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
	3537	+#define HSW_VIDEO_DIP_GMP_ECC_A 0x60300
	3538	+#define HSW_VIDEO_DIP_VSC_ECC_A 0x60344
	3539	+#define HSW_VIDEO_DIP_GCP_A 0x60210
	3540	+
	3541	+#define HSW_VIDEO_DIP_CTL_B 0x61200
	3542	+#define HSW_VIDEO_DIP_AVI_DATA_B 0x61220
	3543	+#define HSW_VIDEO_DIP_VS_DATA_B 0x61260
	3544	+#define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
	3545	+#define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
	3546	+#define HSW_VIDEO_DIP_VSC_DATA_B 0x61320
	3547	+#define HSW_VIDEO_DIP_BVI_ECC_B 0x61240
	3548	+#define HSW_VIDEO_DIP_VS_ECC_B 0x61280
	3549	+#define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
	3550	+#define HSW_VIDEO_DIP_GMP_ECC_B 0x61300
	3551	+#define HSW_VIDEO_DIP_VSC_ECC_B 0x61344
	3552	+#define HSW_VIDEO_DIP_GCP_B 0x61210
	3553	+
	3554	+#define HSW_TVIDEO_DIP_CTL(pipe) \
	3555	+ _PIPE(pipe, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B)
	3556	+#define HSW_TVIDEO_DIP_AVI_DATA(pipe) \
	3557	+ _PIPE(pipe, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B)
	3558	+#define HSW_TVIDEO_DIP_SPD_DATA(pipe) \
	3559	+ _PIPE(pipe, HSW_VIDEO_DIP_SPD_DATA_A, HSW_VIDEO_DIP_SPD_DATA_B)
	3560	+#define HSW_TVIDEO_DIP_GCP(pipe) \
	3561	+ _PIPE(pipe, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B)
	3562	+
3527	3563	#define _TRANS_HTOTAL_B 0xe1000
3528	3564	#define _TRANS_HBLANK_B 0xe1004
3529	3565	#define _TRANS_HSYNC_B 0xe1008
...	...	@@ -277,6 +277,18 @@
277	277	I915_WRITE(reg, val);
278	278	}
279	279
	280	+static void hsw_write_infoframe(struct drm_encoder *encoder,
	281	+ struct dip_infoframe *frame)
	282	+{
	283	+ /* Not implemented yet, so avoid doing anything at all.
	284	+ * This is the placeholder for Paulo Zanoni's infoframe writing patch
	285	+ */
	286	+ DRM_DEBUG_DRIVER("Attempting to write infoframe on Haswell, this is not implemented yet.\n");
	287	+
	288	+ return;
	289	+
	290	+}
	291	+
280	292	static void intel_set_infoframe(struct drm_encoder *encoder,
281	293	struct dip_infoframe *frame)
282	294	{
...	...	@@ -660,6 +672,13 @@
660	672	intel_hdmi->write_infoframe = vlv_write_infoframe;
661	673	for_each_pipe(i)
662	674	I915_WRITE(VLV_TVIDEO_DIP_CTL(i), 0);
	675	+ } else if (IS_HASWELL(dev)) {
	676	+ /* FIXME: Haswell has a new set of DIP frame registers, but we are
	677	+ * just doing the minimal required for HDMI to work at this stage.
	678	+ */
	679	+ intel_hdmi->write_infoframe = hsw_write_infoframe;
	680	+ for_each_pipe(i)
	681	+ I915_WRITE(HSW_TVIDEO_DIP_CTL(i), 0);
663	682	} else if (HAS_PCH_IBX(dev)) {
664	683	intel_hdmi->write_infoframe = ibx_write_infoframe;
665	684	for_each_pipe(i)