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Commit 92d3af9ac369faf3bd2c409cf5218510500af214

Authored by Brian Norris
1 parent a402191e9b
Exists in ti-lsk-linux-4.1.y and in 10 other branches dlt-processor-sdk-linux-03.00.00.04, processor-sdk-linux-02.00.01, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04

mtd: st_spi_fsm: replace FLACH_CMD_* with SPINOR_OP_* 

Begin to unify the differences between serial_flash_cmds.h and
spi-nor.h.

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Marek Vasut <marex@denx.de>

Showing 2 changed files with 87 additions and 87 deletions Side-by-side Diff

drivers/mtd/devices/serial_flash_cmds.h
Diff comments   View file @ 92d3af9
... ... @@ -13,43 +13,43 @@
13 13 #define _MTD_SERIAL_FLASH_CMDS_H
14 14  
15 15 /* Generic Flash Commands/OPCODEs */
16   -#define FLASH_CMD_WREN 0x06
17   -#define FLASH_CMD_WRDI 0x04
18   -#define FLASH_CMD_RDID 0x9f
19   -#define FLASH_CMD_RDSR 0x05
20   -#define FLASH_CMD_RDSR2 0x35
21   -#define FLASH_CMD_WRSR 0x01
22   -#define FLASH_CMD_SE_4K 0x20
23   -#define FLASH_CMD_SE_32K 0x52
24   -#define FLASH_CMD_SE 0xd8
25   -#define FLASH_CMD_CHIPERASE 0xc7
26   -#define FLASH_CMD_WRVCR 0x81
27   -#define FLASH_CMD_RDVCR 0x85
  16 +#define SPINOR_OP_WREN 0x06
  17 +#define SPINOR_OP_WRDI 0x04
  18 +#define SPINOR_OP_RDID 0x9f
  19 +#define SPINOR_OP_RDSR 0x05
  20 +#define SPINOR_OP_RDSR2 0x35
  21 +#define SPINOR_OP_WRSR 0x01
  22 +#define SPINOR_OP_SE_4K 0x20
  23 +#define SPINOR_OP_SE_32K 0x52
  24 +#define SPINOR_OP_SE 0xd8
  25 +#define SPINOR_OP_CHIPERASE 0xc7
  26 +#define SPINOR_OP_WRVCR 0x81
  27 +#define SPINOR_OP_RDVCR 0x85
28 28  
29 29 /* JEDEC Standard - Serial Flash Discoverable Parmeters (SFDP) Commands */
30   -#define FLASH_CMD_READ 0x03 /* READ */
31   -#define FLASH_CMD_READ_FAST 0x0b /* FAST READ */
32   -#define FLASH_CMD_READ_1_1_2 0x3b /* DUAL OUTPUT READ */
33   -#define FLASH_CMD_READ_1_2_2 0xbb /* DUAL I/O READ */
34   -#define FLASH_CMD_READ_1_1_4 0x6b /* QUAD OUTPUT READ */
35   -#define FLASH_CMD_READ_1_4_4 0xeb /* QUAD I/O READ */
  30 +#define SPINOR_OP_READ 0x03 /* READ */
  31 +#define SPINOR_OP_READ_FAST 0x0b /* FAST READ */
  32 +#define SPINOR_OP_READ_1_1_2 0x3b /* DUAL OUTPUT READ */
  33 +#define SPINOR_OP_READ_1_2_2 0xbb /* DUAL I/O READ */
  34 +#define SPINOR_OP_READ_1_1_4 0x6b /* QUAD OUTPUT READ */
  35 +#define SPINOR_OP_READ_1_4_4 0xeb /* QUAD I/O READ */
36 36  
37   -#define FLASH_CMD_WRITE 0x02 /* PAGE PROGRAM */
38   -#define FLASH_CMD_WRITE_1_1_2 0xa2 /* DUAL INPUT PROGRAM */
39   -#define FLASH_CMD_WRITE_1_2_2 0xd2 /* DUAL INPUT EXT PROGRAM */
40   -#define FLASH_CMD_WRITE_1_1_4 0x32 /* QUAD INPUT PROGRAM */
41   -#define FLASH_CMD_WRITE_1_4_4 0x12 /* QUAD INPUT EXT PROGRAM */
  37 +#define SPINOR_OP_WRITE 0x02 /* PAGE PROGRAM */
  38 +#define SPINOR_OP_WRITE_1_1_2 0xa2 /* DUAL INPUT PROGRAM */
  39 +#define SPINOR_OP_WRITE_1_2_2 0xd2 /* DUAL INPUT EXT PROGRAM */
  40 +#define SPINOR_OP_WRITE_1_1_4 0x32 /* QUAD INPUT PROGRAM */
  41 +#define SPINOR_OP_WRITE_1_4_4 0x12 /* QUAD INPUT EXT PROGRAM */
42 42  
43   -#define FLASH_CMD_EN4B_ADDR 0xb7 /* Enter 4-byte address mode */
44   -#define FLASH_CMD_EX4B_ADDR 0xe9 /* Exit 4-byte address mode */
  43 +#define SPINOR_OP_EN4B_ADDR 0xb7 /* Enter 4-byte address mode */
  44 +#define SPINOR_OP_EX4B_ADDR 0xe9 /* Exit 4-byte address mode */
45 45  
46 46 /* READ commands with 32-bit addressing */
47   -#define FLASH_CMD_READ4 0x13
48   -#define FLASH_CMD_READ4_FAST 0x0c
49   -#define FLASH_CMD_READ4_1_1_2 0x3c
50   -#define FLASH_CMD_READ4_1_2_2 0xbc
51   -#define FLASH_CMD_READ4_1_1_4 0x6c
52   -#define FLASH_CMD_READ4_1_4_4 0xec
  47 +#define SPINOR_OP_READ4 0x13
  48 +#define SPINOR_OP_READ4_FAST 0x0c
  49 +#define SPINOR_OP_READ4_1_1_2 0x3c
  50 +#define SPINOR_OP_READ4_1_2_2 0xbc
  51 +#define SPINOR_OP_READ4_1_1_4 0x6c
  52 +#define SPINOR_OP_READ4_1_4_4 0xec
53 53  
54 54 /* Configuration flags */
55 55 #define FLASH_FLAG_SINGLE 0x000000ff
drivers/mtd/devices/st_spi_fsm.c
Diff comments   View file @ 92d3af9
... ... @@ -208,7 +208,7 @@
208 208 #define S25FL_CMD_DYBWR 0xe1
209 209 #define S25FL_CMD_DYBRD 0xe0
210 210 #define S25FL_CMD_WRITE4 0x12 /* Note, opcode clashes with
211   - * 'FLASH_CMD_WRITE_1_4_4'
  211 + * 'SPINOR_OP_WRITE_1_4_4'
212 212 * as found on N25Qxxx devices! */
213 213  
214 214 /* Status register */
... ... @@ -296,7 +296,7 @@
296 296 u32 jedec_id;
297 297 u16 ext_id;
298 298 /*
299   - * The size listed here is what works with FLASH_CMD_SE, which isn't
  299 + * The size listed here is what works with SPINOR_OP_SE, which isn't
300 300 * necessarily called a "sector" by the vendor.
301 301 */
302 302 unsigned sector_size;
303 303  
... ... @@ -451,22 +451,22 @@
451 451  
452 452 /* Default READ configurations, in order of preference */
453 453 static struct seq_rw_config default_read_configs[] = {
454   - {FLASH_FLAG_READ_1_4_4, FLASH_CMD_READ_1_4_4, 0, 4, 4, 0x00, 2, 4},
455   - {FLASH_FLAG_READ_1_1_4, FLASH_CMD_READ_1_1_4, 0, 1, 4, 0x00, 4, 0},
456   - {FLASH_FLAG_READ_1_2_2, FLASH_CMD_READ_1_2_2, 0, 2, 2, 0x00, 4, 0},
457   - {FLASH_FLAG_READ_1_1_2, FLASH_CMD_READ_1_1_2, 0, 1, 2, 0x00, 0, 8},
458   - {FLASH_FLAG_READ_FAST, FLASH_CMD_READ_FAST, 0, 1, 1, 0x00, 0, 8},
459   - {FLASH_FLAG_READ_WRITE, FLASH_CMD_READ, 0, 1, 1, 0x00, 0, 0},
  454 + {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ_1_4_4, 0, 4, 4, 0x00, 2, 4},
  455 + {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ_1_1_4, 0, 1, 4, 0x00, 4, 0},
  456 + {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ_1_2_2, 0, 2, 2, 0x00, 4, 0},
  457 + {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ_1_1_2, 0, 1, 2, 0x00, 0, 8},
  458 + {FLASH_FLAG_READ_FAST, SPINOR_OP_READ_FAST, 0, 1, 1, 0x00, 0, 8},
  459 + {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ, 0, 1, 1, 0x00, 0, 0},
460 460 {0x00, 0, 0, 0, 0, 0x00, 0, 0},
461 461 };
462 462  
463 463 /* Default WRITE configurations */
464 464 static struct seq_rw_config default_write_configs[] = {
465   - {FLASH_FLAG_WRITE_1_4_4, FLASH_CMD_WRITE_1_4_4, 1, 4, 4, 0x00, 0, 0},
466   - {FLASH_FLAG_WRITE_1_1_4, FLASH_CMD_WRITE_1_1_4, 1, 1, 4, 0x00, 0, 0},
467   - {FLASH_FLAG_WRITE_1_2_2, FLASH_CMD_WRITE_1_2_2, 1, 2, 2, 0x00, 0, 0},
468   - {FLASH_FLAG_WRITE_1_1_2, FLASH_CMD_WRITE_1_1_2, 1, 1, 2, 0x00, 0, 0},
469   - {FLASH_FLAG_READ_WRITE, FLASH_CMD_WRITE, 1, 1, 1, 0x00, 0, 0},
  465 + {FLASH_FLAG_WRITE_1_4_4, SPINOR_OP_WRITE_1_4_4, 1, 4, 4, 0x00, 0, 0},
  466 + {FLASH_FLAG_WRITE_1_1_4, SPINOR_OP_WRITE_1_1_4, 1, 1, 4, 0x00, 0, 0},
  467 + {FLASH_FLAG_WRITE_1_2_2, SPINOR_OP_WRITE_1_2_2, 1, 2, 2, 0x00, 0, 0},
  468 + {FLASH_FLAG_WRITE_1_1_2, SPINOR_OP_WRITE_1_1_2, 1, 1, 2, 0x00, 0, 0},
  469 + {FLASH_FLAG_READ_WRITE, SPINOR_OP_WRITE, 1, 1, 1, 0x00, 0, 0},
470 470 {0x00, 0, 0, 0, 0, 0x00, 0, 0},
471 471 };
472 472  
... ... @@ -489,12 +489,12 @@
489 489 * cycles.
490 490 */
491 491 static struct seq_rw_config n25q_read3_configs[] = {
492   - {FLASH_FLAG_READ_1_4_4, FLASH_CMD_READ_1_4_4, 0, 4, 4, 0x00, 0, 8},
493   - {FLASH_FLAG_READ_1_1_4, FLASH_CMD_READ_1_1_4, 0, 1, 4, 0x00, 0, 8},
494   - {FLASH_FLAG_READ_1_2_2, FLASH_CMD_READ_1_2_2, 0, 2, 2, 0x00, 0, 8},
495   - {FLASH_FLAG_READ_1_1_2, FLASH_CMD_READ_1_1_2, 0, 1, 2, 0x00, 0, 8},
496   - {FLASH_FLAG_READ_FAST, FLASH_CMD_READ_FAST, 0, 1, 1, 0x00, 0, 8},
497   - {FLASH_FLAG_READ_WRITE, FLASH_CMD_READ, 0, 1, 1, 0x00, 0, 0},
  492 + {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ_1_4_4, 0, 4, 4, 0x00, 0, 8},
  493 + {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ_1_1_4, 0, 1, 4, 0x00, 0, 8},
  494 + {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ_1_2_2, 0, 2, 2, 0x00, 0, 8},
  495 + {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ_1_1_2, 0, 1, 2, 0x00, 0, 8},
  496 + {FLASH_FLAG_READ_FAST, SPINOR_OP_READ_FAST, 0, 1, 1, 0x00, 0, 8},
  497 + {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ, 0, 1, 1, 0x00, 0, 0},
498 498 {0x00, 0, 0, 0, 0, 0x00, 0, 0},
499 499 };
500 500  
... ... @@ -504,12 +504,12 @@
504 504 * - 'FAST' variants configured for 8 dummy cycles (see note above.)
505 505 */
506 506 static struct seq_rw_config n25q_read4_configs[] = {
507   - {FLASH_FLAG_READ_1_4_4, FLASH_CMD_READ4_1_4_4, 0, 4, 4, 0x00, 0, 8},
508   - {FLASH_FLAG_READ_1_1_4, FLASH_CMD_READ4_1_1_4, 0, 1, 4, 0x00, 0, 8},
509   - {FLASH_FLAG_READ_1_2_2, FLASH_CMD_READ4_1_2_2, 0, 2, 2, 0x00, 0, 8},
510   - {FLASH_FLAG_READ_1_1_2, FLASH_CMD_READ4_1_1_2, 0, 1, 2, 0x00, 0, 8},
511   - {FLASH_FLAG_READ_FAST, FLASH_CMD_READ4_FAST, 0, 1, 1, 0x00, 0, 8},
512   - {FLASH_FLAG_READ_WRITE, FLASH_CMD_READ4, 0, 1, 1, 0x00, 0, 0},
  507 + {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ4_1_4_4, 0, 4, 4, 0x00, 0, 8},
  508 + {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ4_1_1_4, 0, 1, 4, 0x00, 0, 8},
  509 + {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ4_1_2_2, 0, 2, 2, 0x00, 0, 8},
  510 + {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ4_1_1_2, 0, 1, 2, 0x00, 0, 8},
  511 + {FLASH_FLAG_READ_FAST, SPINOR_OP_READ4_FAST, 0, 1, 1, 0x00, 0, 8},
  512 + {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ4, 0, 1, 1, 0x00, 0, 0},
513 513 {0x00, 0, 0, 0, 0, 0x00, 0, 0},
514 514 };
515 515  
... ... @@ -522,7 +522,7 @@
522 522 {
523 523 seq->seq_opc[0] = (SEQ_OPC_PADS_1 |
524 524 SEQ_OPC_CYCLES(8) |
525   - SEQ_OPC_OPCODE(FLASH_CMD_EN4B_ADDR) |
  525 + SEQ_OPC_OPCODE(SPINOR_OP_EN4B_ADDR) |
526 526 SEQ_OPC_CSDEASSERT);
527 527  
528 528 seq->seq[0] = STFSM_INST_CMD1;
... ... @@ -550,12 +550,12 @@
550 550 * entering a state that is incompatible with the SPIBoot Controller.
551 551 */
552 552 static struct seq_rw_config stfsm_s25fl_read4_configs[] = {
553   - {FLASH_FLAG_READ_1_4_4, FLASH_CMD_READ4_1_4_4, 0, 4, 4, 0x00, 2, 4},
554   - {FLASH_FLAG_READ_1_1_4, FLASH_CMD_READ4_1_1_4, 0, 1, 4, 0x00, 0, 8},
555   - {FLASH_FLAG_READ_1_2_2, FLASH_CMD_READ4_1_2_2, 0, 2, 2, 0x00, 4, 0},
556   - {FLASH_FLAG_READ_1_1_2, FLASH_CMD_READ4_1_1_2, 0, 1, 2, 0x00, 0, 8},
557   - {FLASH_FLAG_READ_FAST, FLASH_CMD_READ4_FAST, 0, 1, 1, 0x00, 0, 8},
558   - {FLASH_FLAG_READ_WRITE, FLASH_CMD_READ4, 0, 1, 1, 0x00, 0, 0},
  553 + {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ4_1_4_4, 0, 4, 4, 0x00, 2, 4},
  554 + {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ4_1_1_4, 0, 1, 4, 0x00, 0, 8},
  555 + {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ4_1_2_2, 0, 2, 2, 0x00, 4, 0},
  556 + {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ4_1_1_2, 0, 1, 2, 0x00, 0, 8},
  557 + {FLASH_FLAG_READ_FAST, SPINOR_OP_READ4_FAST, 0, 1, 1, 0x00, 0, 8},
  558 + {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ4, 0, 1, 1, 0x00, 0, 0},
559 559 {0x00, 0, 0, 0, 0, 0x00, 0, 0},
560 560 };
561 561  
... ... @@ -574,7 +574,7 @@
574 574 .data_size = TRANSFER_SIZE(8),
575 575 .seq_opc[0] = (SEQ_OPC_PADS_1 |
576 576 SEQ_OPC_CYCLES(8) |
577   - SEQ_OPC_OPCODE(FLASH_CMD_RDID)),
  577 + SEQ_OPC_OPCODE(SPINOR_OP_RDID)),
578 578 .seq = {
579 579 STFSM_INST_CMD1,
580 580 STFSM_INST_DATA_READ,
... ... @@ -590,7 +590,7 @@
590 590 .data_size = TRANSFER_SIZE(4),
591 591 .seq_opc[0] = (SEQ_OPC_PADS_1 |
592 592 SEQ_OPC_CYCLES(8) |
593   - SEQ_OPC_OPCODE(FLASH_CMD_RDSR)),
  593 + SEQ_OPC_OPCODE(SPINOR_OP_RDSR)),
594 594 .seq = {
595 595 STFSM_INST_CMD1,
596 596 STFSM_INST_DATA_READ,
597 597  
... ... @@ -606,10 +606,10 @@
606 606 /* 'addr_cfg' configured during initialisation */
607 607 .seq_opc = {
608 608 (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
609   - SEQ_OPC_OPCODE(FLASH_CMD_WREN) | SEQ_OPC_CSDEASSERT),
  609 + SEQ_OPC_OPCODE(SPINOR_OP_WREN) | SEQ_OPC_CSDEASSERT),
610 610  
611 611 (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
612   - SEQ_OPC_OPCODE(FLASH_CMD_SE)),
  612 + SEQ_OPC_OPCODE(SPINOR_OP_SE)),
613 613 },
614 614 .seq = {
615 615 STFSM_INST_CMD1,
616 616  
... ... @@ -627,10 +627,10 @@
627 627 static struct stfsm_seq stfsm_seq_erase_chip = {
628 628 .seq_opc = {
629 629 (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
630   - SEQ_OPC_OPCODE(FLASH_CMD_WREN) | SEQ_OPC_CSDEASSERT),
  630 + SEQ_OPC_OPCODE(SPINOR_OP_WREN) | SEQ_OPC_CSDEASSERT),
631 631  
632 632 (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
633   - SEQ_OPC_OPCODE(FLASH_CMD_CHIPERASE) | SEQ_OPC_CSDEASSERT),
  633 + SEQ_OPC_OPCODE(SPINOR_OP_CHIPERASE) | SEQ_OPC_CSDEASSERT),
634 634 },
635 635 .seq = {
636 636 STFSM_INST_CMD1,
637 637  
... ... @@ -647,9 +647,9 @@
647 647  
648 648 static struct stfsm_seq stfsm_seq_write_status = {
649 649 .seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
650   - SEQ_OPC_OPCODE(FLASH_CMD_WREN) | SEQ_OPC_CSDEASSERT),
  650 + SEQ_OPC_OPCODE(SPINOR_OP_WREN) | SEQ_OPC_CSDEASSERT),
651 651 .seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
652   - SEQ_OPC_OPCODE(FLASH_CMD_WRSR)),
  652 + SEQ_OPC_OPCODE(SPINOR_OP_WRSR)),
653 653 .seq = {
654 654 STFSM_INST_CMD1,
655 655 STFSM_INST_CMD2,
656 656  
... ... @@ -665,9 +665,9 @@
665 665 static int stfsm_n25q_en_32bit_addr_seq(struct stfsm_seq *seq)
666 666 {
667 667 seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
668   - SEQ_OPC_OPCODE(FLASH_CMD_EN4B_ADDR));
  668 + SEQ_OPC_OPCODE(SPINOR_OP_EN4B_ADDR));
669 669 seq->seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
670   - SEQ_OPC_OPCODE(FLASH_CMD_WREN) |
  670 + SEQ_OPC_OPCODE(SPINOR_OP_WREN) |
671 671 SEQ_OPC_CSDEASSERT);
672 672  
673 673 seq->seq[0] = STFSM_INST_CMD2;
... ... @@ -788,7 +788,7 @@
788 788 static int stfsm_enter_32bit_addr(struct stfsm *fsm, int enter)
789 789 {
790 790 struct stfsm_seq *seq = &fsm->stfsm_seq_en_32bit_addr;
791   - uint32_t cmd = enter ? FLASH_CMD_EN4B_ADDR : FLASH_CMD_EX4B_ADDR;
  791 + uint32_t cmd = enter ? SPINOR_OP_EN4B_ADDR : SPINOR_OP_EX4B_ADDR;
792 792  
793 793 seq->seq_opc[0] = (SEQ_OPC_PADS_1 |
794 794 SEQ_OPC_CYCLES(8) |
... ... @@ -812,7 +812,7 @@
812 812 /* Use RDRS1 */
813 813 seq->seq_opc[0] = (SEQ_OPC_PADS_1 |
814 814 SEQ_OPC_CYCLES(8) |
815   - SEQ_OPC_OPCODE(FLASH_CMD_RDSR));
  815 + SEQ_OPC_OPCODE(SPINOR_OP_RDSR));
816 816  
817 817 /* Load read_status sequence */
818 818 stfsm_load_seq(fsm, seq);
... ... @@ -985,7 +985,7 @@
985 985 if (cfg->write)
986 986 seq->seq_opc[i++] = (SEQ_OPC_PADS_1 |
987 987 SEQ_OPC_CYCLES(8) |
988   - SEQ_OPC_OPCODE(FLASH_CMD_WREN) |
  988 + SEQ_OPC_OPCODE(SPINOR_OP_WREN) |
989 989 SEQ_OPC_CSDEASSERT);
990 990  
991 991 /* Address configuration (24 or 32-bit addresses) */
992 992  
993 993  
... ... @@ -1121,21 +1121,21 @@
1121 1121 }
1122 1122  
1123 1123 /* Check status of 'QE' bit, update if required. */
1124   - stfsm_read_status(fsm, FLASH_CMD_RDSR, &sta, 1);
  1124 + stfsm_read_status(fsm, SPINOR_OP_RDSR, &sta, 1);
1125 1125 data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1;
1126 1126 if (data_pads == 4) {
1127 1127 if (!(sta & MX25_STATUS_QE)) {
1128 1128 /* Set 'QE' */
1129 1129 sta |= MX25_STATUS_QE;
1130 1130  
1131   - stfsm_write_status(fsm, FLASH_CMD_WRSR, sta, 1, 1);
  1131 + stfsm_write_status(fsm, SPINOR_OP_WRSR, sta, 1, 1);
1132 1132 }
1133 1133 } else {
1134 1134 if (sta & MX25_STATUS_QE) {
1135 1135 /* Clear 'QE' */
1136 1136 sta &= ~MX25_STATUS_QE;
1137 1137  
1138   - stfsm_write_status(fsm, FLASH_CMD_WRSR, sta, 1, 1);
  1138 + stfsm_write_status(fsm, SPINOR_OP_WRSR, sta, 1, 1);
1139 1139 }
1140 1140 }
1141 1141  
... ... @@ -1260,7 +1260,7 @@
1260 1260 {
1261 1261 struct stfsm_seq seq = {
1262 1262 .seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
1263   - SEQ_OPC_OPCODE(FLASH_CMD_WREN) |
  1263 + SEQ_OPC_OPCODE(SPINOR_OP_WREN) |
1264 1264 SEQ_OPC_CSDEASSERT),
1265 1265 .seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
1266 1266 SEQ_OPC_OPCODE(S25FL_CMD_DYBWR)),
... ... @@ -1300,7 +1300,7 @@
1300 1300 SEQ_OPC_CSDEASSERT),
1301 1301 .seq_opc[1] = (SEQ_OPC_PADS_1 |
1302 1302 SEQ_OPC_CYCLES(8) |
1303   - SEQ_OPC_OPCODE(FLASH_CMD_WRDI) |
  1303 + SEQ_OPC_OPCODE(SPINOR_OP_WRDI) |
1304 1304 SEQ_OPC_CSDEASSERT),
1305 1305 .seq = {
1306 1306 STFSM_INST_CMD1,
... ... @@ -1379,7 +1379,7 @@
1379 1379 }
1380 1380  
1381 1381 /* Check status of 'QE' bit, update if required. */
1382   - stfsm_read_status(fsm, FLASH_CMD_RDSR2, &cr1, 1);
  1382 + stfsm_read_status(fsm, SPINOR_OP_RDSR2, &cr1, 1);
1383 1383 data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1;
1384 1384 if (data_pads == 4) {
1385 1385 if (!(cr1 & STFSM_S25FL_CONFIG_QE)) {
1386 1386  
... ... @@ -1397,9 +1397,9 @@
1397 1397 }
1398 1398 }
1399 1399 if (update_sr) {
1400   - stfsm_read_status(fsm, FLASH_CMD_RDSR, &sr1, 1);
  1400 + stfsm_read_status(fsm, SPINOR_OP_RDSR, &sr1, 1);
1401 1401 sta_wr = ((uint16_t)cr1 << 8) | sr1;
1402   - stfsm_write_status(fsm, FLASH_CMD_WRSR, sta_wr, 2, 1);
  1402 + stfsm_write_status(fsm, SPINOR_OP_WRSR, sta_wr, 2, 1);
1403 1403 }
1404 1404  
1405 1405 /*
... ... @@ -1424,7 +1424,7 @@
1424 1424 return ret;
1425 1425  
1426 1426 /* Check status of 'QE' bit, update if required. */
1427   - stfsm_read_status(fsm, FLASH_CMD_RDSR2, &sr2, 1);
  1427 + stfsm_read_status(fsm, SPINOR_OP_RDSR2, &sr2, 1);
1428 1428 data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1;
1429 1429 if (data_pads == 4) {
1430 1430 if (!(sr2 & W25Q_STATUS_QE)) {
1431 1431  
... ... @@ -1441,9 +1441,9 @@
1441 1441 }
1442 1442 if (update_sr) {
1443 1443 /* Write status register */
1444   - stfsm_read_status(fsm, FLASH_CMD_RDSR, &sr1, 1);
  1444 + stfsm_read_status(fsm, SPINOR_OP_RDSR, &sr1, 1);
1445 1445 sr_wr = ((uint16_t)sr2 << 8) | sr1;
1446   - stfsm_write_status(fsm, FLASH_CMD_WRSR, sr_wr, 2, 1);
  1446 + stfsm_write_status(fsm, SPINOR_OP_WRSR, sr_wr, 2, 1);
1447 1447 }
1448 1448  
1449 1449 return 0;