Merge tag 'staging-3.19-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging

Pull staging driver fixes from Greg KH: "Here are 6 staging driver fixes for 3.19-rc5. They fix some reported issues with some IIO drivers, as well as some issues with the vt6655 wireless driver. All have been in linux-next for a while" * tag 'staging-3.19-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging: staging: vt6655: fix sparse warning: argument type staging: vt6655: Fix loss of distant/weak access points on channel change. staging: vt6655: vnt_tx_packet Fix corrupted tx packets. staging: vt6655: fix sparse warnings: incorrect argument type iio: iio: Fix iio_channel_read return if channel havn't info iio: ad799x: Fix ad7991/ad7995/ad7999 config setup

Merge tag 'staging-3.19-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging
Pull staging driver fixes from Greg KH: "Here are 6 staging driver fixes for 3.19-rc5. They fix some reported issues with some IIO drivers, as well as some issues with the vt6655 wireless driver. All have been in linux-next for a while" * tag 'staging-3.19-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging: staging: vt6655: fix sparse warning: argument type staging: vt6655: Fix loss of distant/weak access points on channel change. staging: vt6655: vnt_tx_packet Fix corrupted tx packets. staging: vt6655: fix sparse warnings: incorrect argument type iio: iio: Fix iio_channel_read return if channel havn't info iio: ad799x: Fix ad7991/ad7995/ad7999 config setup
Linus Torvalds
2 parents 79600d4bba a307d1d6d4
Showing 6 changed files Side-by-side Diff
drivers/iio/adc/ad799x.c
drivers/iio/inkern.c
drivers/staging/vt6655/baseband.c
drivers/staging/vt6655/channel.c
drivers/staging/vt6655/device_main.c
drivers/staging/vt6655/rxtx.c
@@ -143,9 +143,15 @@
 	case ad7998:
 		return i2c_smbus_write_word_swapped(st->client, AD7998_CONF_REG,
 			val);
-	default:
+	case ad7992:
+	case ad7993:
+	case ad7994:
 		return i2c_smbus_write_byte_data(st->client, AD7998_CONF_REG,
 			val);
+	default:
+		/* Will be written when doing a conversion */
+		st->config = val;
+		return 0;
 	}
 }
  
  
@@ -155,8 +161,13 @@
 	case ad7997:
 	case ad7998:
 		return i2c_smbus_read_word_swapped(st->client, AD7998_CONF_REG);
-	default:
+	case ad7992:
+	case ad7993:
+	case ad7994:
 		return i2c_smbus_read_byte_data(st->client, AD7998_CONF_REG);
+	default:
+		/* No readback support */
+		return st->config;
 	}
 }
  
@@ -449,6 +449,9 @@
 	if (val2 == NULL)
 		val2 = &unused;
  
+	if(!iio_channel_has_info(chan->channel, info))
+		return -EINVAL;
+
 	if (chan->indio_dev->info->read_raw_multi) {
 		ret = chan->indio_dev->info->read_raw_multi(chan->indio_dev,
 					chan->channel, INDIO_MAX_RAW_ELEMENTS,
@@ -2177,7 +2177,7 @@
 		/* Init ANT B select,RX Config CR10 = 0x28->0x2A, 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted) */
 		/*bResult &= BBbWriteEmbedded(dwIoBase,0x0a,0x28);*/
 		/* Select VC1/VC2, CR215 = 0x02->0x06 */
-		bResult &= BBbWriteEmbedded(dwIoBase, 0xd7, 0x06);
+		bResult &= BBbWriteEmbedded(priv, 0xd7, 0x06);
 		/* }} */
  
 		for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
@@ -182,6 +182,14 @@
 	if (pDevice->byCurrentCh == uConnectionChannel)
 		return bResult;
  
+	/* Set VGA to max sensitivity */
+	if (pDevice->bUpdateBBVGA &&
+	    pDevice->byBBVGACurrent != pDevice->abyBBVGA[0]) {
+		pDevice->byBBVGACurrent = pDevice->abyBBVGA[0];
+
+		BBvSetVGAGainOffset(pDevice, pDevice->byBBVGACurrent);
+	}
+
 	/* clear NAV */
 	MACvRegBitsOn(pDevice->PortOffset, MAC_REG_MACCR, MACCR_CLRNAV);
  
@@ -1232,7 +1232,7 @@
  
 	head_td = priv->apCurrTD[dma_idx];
  
-	head_td->m_td1TD1.byTCR = (TCR_EDP|TCR_STP);
+	head_td->m_td1TD1.byTCR = 0;
  
 	head_td->pTDInfo->skb = skb;
  
@@ -1257,6 +1257,11 @@
  
 	priv->bPWBitOn = false;
  
+	/* Set TSR1 & ReqCount in TxDescHead */
+	head_td->m_td1TD1.byTCR |= (TCR_STP | TCR_EDP | EDMSDU);
+	head_td->m_td1TD1.wReqCount =
+			cpu_to_le16((u16)head_td->pTDInfo->dwReqCount);
+
 	head_td->pTDInfo->byFlags = TD_FLAGS_NETIF_SKB;
  
 	if (dma_idx == TYPE_AC0DMA)
  
@@ -1500,9 +1505,11 @@
 		if (conf->enable_beacon) {
 			vnt_beacon_enable(priv, vif, conf);
  
-			MACvRegBitsOn(priv, MAC_REG_TCR, TCR_AUTOBCNTX);
+			MACvRegBitsOn(priv->PortOffset, MAC_REG_TCR,
+				      TCR_AUTOBCNTX);
 		} else {
-			MACvRegBitsOff(priv, MAC_REG_TCR, TCR_AUTOBCNTX);
+			MACvRegBitsOff(priv->PortOffset, MAC_REG_TCR,
+				       TCR_AUTOBCNTX);
 		}
 	}
  
@@ -1204,13 +1204,10 @@
  
 	ptdCurr = (PSTxDesc)pHeadTD;
  
-	ptdCurr->pTDInfo->dwReqCount = cbReqCount - uPadding;
+	ptdCurr->pTDInfo->dwReqCount = cbReqCount;
 	ptdCurr->pTDInfo->dwHeaderLength = cbHeaderLength;
 	ptdCurr->pTDInfo->skb_dma = ptdCurr->pTDInfo->buf_dma;
 	ptdCurr->buff_addr = cpu_to_le32(ptdCurr->pTDInfo->skb_dma);
-	/* Set TSR1 & ReqCount in TxDescHead */
-	ptdCurr->m_td1TD1.byTCR |= (TCR_STP | TCR_EDP | EDMSDU);
-	ptdCurr->m_td1TD1.wReqCount = cpu_to_le16((unsigned short)(cbReqCount));
  
 	return cbHeaderLength;
 }
...	...	@@ -143,9 +143,15 @@
143	143	case ad7998:
144	144	return i2c_smbus_write_word_swapped(st->client, AD7998_CONF_REG,
145	145	val);
146		- default:
	146	+ case ad7992:
	147	+ case ad7993:
	148	+ case ad7994:
147	149	return i2c_smbus_write_byte_data(st->client, AD7998_CONF_REG,
148	150	val);
	151	+ default:
	152	+ /* Will be written when doing a conversion */
	153	+ st->config = val;
	154	+ return 0;
149	155	}
150	156	}
151	157
152	158
...	...	@@ -155,8 +161,13 @@
155	161	case ad7997:
156	162	case ad7998:
157	163	return i2c_smbus_read_word_swapped(st->client, AD7998_CONF_REG);
158		- default:
	164	+ case ad7992:
	165	+ case ad7993:
	166	+ case ad7994:
159	167	return i2c_smbus_read_byte_data(st->client, AD7998_CONF_REG);
	168	+ default:
	169	+ /* No readback support */
	170	+ return st->config;
160	171	}
161	172	}
162	173
...	...	@@ -449,6 +449,9 @@
449	449	if (val2 == NULL)
450	450	val2 = &unused;
451	451
	452	+ if(!iio_channel_has_info(chan->channel, info))
	453	+ return -EINVAL;
	454	+
452	455	if (chan->indio_dev->info->read_raw_multi) {
453	456	ret = chan->indio_dev->info->read_raw_multi(chan->indio_dev,
454	457	chan->channel, INDIO_MAX_RAW_ELEMENTS,
...	...	@@ -2177,7 +2177,7 @@
2177	2177	/* Init ANT B select,RX Config CR10 = 0x28->0x2A, 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted) */
2178	2178	/bResult &= BBbWriteEmbedded(dwIoBase,0x0a,0x28);/
2179	2179	/* Select VC1/VC2, CR215 = 0x02->0x06 */
2180		- bResult &= BBbWriteEmbedded(dwIoBase, 0xd7, 0x06);
	2180	+ bResult &= BBbWriteEmbedded(priv, 0xd7, 0x06);
2181	2181	/* }} */
2182	2182
2183	2183	for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
...	...	@@ -182,6 +182,14 @@
182	182	if (pDevice->byCurrentCh == uConnectionChannel)
183	183	return bResult;
184	184
	185	+ /* Set VGA to max sensitivity */
	186	+ if (pDevice->bUpdateBBVGA &&
	187	+ pDevice->byBBVGACurrent != pDevice->abyBBVGA[0]) {
	188	+ pDevice->byBBVGACurrent = pDevice->abyBBVGA[0];
	189	+
	190	+ BBvSetVGAGainOffset(pDevice, pDevice->byBBVGACurrent);
	191	+ }
	192	+
185	193	/* clear NAV */
186	194	MACvRegBitsOn(pDevice->PortOffset, MAC_REG_MACCR, MACCR_CLRNAV);
187	195
...	...	@@ -1232,7 +1232,7 @@
1232	1232
1233	1233	head_td = priv->apCurrTD[dma_idx];
1234	1234
1235		- head_td->m_td1TD1.byTCR = (TCR_EDP\|TCR_STP);
	1235	+ head_td->m_td1TD1.byTCR = 0;
1236	1236
1237	1237	head_td->pTDInfo->skb = skb;
1238	1238
...	...	@@ -1257,6 +1257,11 @@
1257	1257
1258	1258	priv->bPWBitOn = false;
1259	1259
	1260	+ /* Set TSR1 & ReqCount in TxDescHead */
	1261	+ head_td->m_td1TD1.byTCR \|= (TCR_STP \| TCR_EDP \| EDMSDU);
	1262	+ head_td->m_td1TD1.wReqCount =
	1263	+ cpu_to_le16((u16)head_td->pTDInfo->dwReqCount);
	1264	+
1260	1265	head_td->pTDInfo->byFlags = TD_FLAGS_NETIF_SKB;
1261	1266
1262	1267	if (dma_idx == TYPE_AC0DMA)
1263	1268
...	...	@@ -1500,9 +1505,11 @@
1500	1505	if (conf->enable_beacon) {
1501	1506	vnt_beacon_enable(priv, vif, conf);
1502	1507
1503		- MACvRegBitsOn(priv, MAC_REG_TCR, TCR_AUTOBCNTX);
	1508	+ MACvRegBitsOn(priv->PortOffset, MAC_REG_TCR,
	1509	+ TCR_AUTOBCNTX);
1504	1510	} else {
1505		- MACvRegBitsOff(priv, MAC_REG_TCR, TCR_AUTOBCNTX);
	1511	+ MACvRegBitsOff(priv->PortOffset, MAC_REG_TCR,
	1512	+ TCR_AUTOBCNTX);
1506	1513	}
1507	1514	}
1508	1515
...	...	@@ -1204,13 +1204,10 @@
1204	1204
1205	1205	ptdCurr = (PSTxDesc)pHeadTD;
1206	1206
1207		- ptdCurr->pTDInfo->dwReqCount = cbReqCount - uPadding;
	1207	+ ptdCurr->pTDInfo->dwReqCount = cbReqCount;
1208	1208	ptdCurr->pTDInfo->dwHeaderLength = cbHeaderLength;
1209	1209	ptdCurr->pTDInfo->skb_dma = ptdCurr->pTDInfo->buf_dma;
1210	1210	ptdCurr->buff_addr = cpu_to_le32(ptdCurr->pTDInfo->skb_dma);
1211		- /* Set TSR1 & ReqCount in TxDescHead */
1212		- ptdCurr->m_td1TD1.byTCR \|= (TCR_STP \| TCR_EDP \| EDMSDU);
1213		- ptdCurr->m_td1TD1.wReqCount = cpu_to_le16((unsigned short)(cbReqCount));
1214	1211
1215	1212	return cbHeaderLength;
1216	1213	}