Eric Lee / smarc-ti-linux-kernel | Embedian Git Server

Commit 95acd4c7b69c9b250d901d154390ec4c8b7b51c1

Authored by Ley Foon Tan 2014-11-06 15:20:03 +0800

nios2: Device tree support

Add device tree support to arch/nios2.

Signed-off-by: Ley Foon Tan <lftan@altera.com>

Showing 6 changed files with 375 additions and 0 deletions Side-by-side Diff

Documentation/devicetree/bindings/nios2/nios2.txt
Documentation/devicetree/bindings/nios2/timer.txt
arch/nios2/boot/dts/3c120_devboard.dts
arch/nios2/boot/linked_dtb.S
arch/nios2/kernel/prom.c
arch/nios2/platform/platform.c

Documentation/devicetree/bindings/nios2/nios2.txt

Diff comments View file @ 95acd4c

	1	+* Nios II Processor Binding
	2	+
	3	+This binding specifies what properties available in the device tree
	4	+representation of a Nios II Processor Core.
	5	+
	6	+Users can use sopc2dts tool for generating device tree sources (dts) from a
	7	+Qsys system. See more detail in: http://www.alterawiki.com/wiki/Sopc2dts
	8	+
	9	+Required properties:
	10	+
	11	+- compatible: Compatible property value should be "altr,nios2-1.0".
	12	+- reg: Contains CPU index.
	13	+- interrupt-controller: Specifies that the node is an interrupt controller
	14	+- #interrupt-cells: Specifies the number of cells needed to encode an
	15	+ interrupt source, should be 1.
	16	+- clock-frequency: Contains the clock frequency for CPU, in Hz.
	17	+- dcache-line-size: Contains data cache line size.
	18	+- icache-line-size: Contains instruction line size.
	19	+- dcache-size: Contains data cache size.
	20	+- icache-size: Contains instruction cache size.
	21	+- altr,pid-num-bits: Specifies the number of bits to use to represent the process
	22	+ identifier (PID).
	23	+- altr,tlb-num-ways: Specifies the number of set-associativity ways in the TLB.
	24	+- altr,tlb-num-entries: Specifies the number of entries in the TLB.
	25	+- altr,tlb-ptr-sz: Specifies size of TLB pointer.
	26	+- altr,has-mul: Specifies CPU hardware multipy support, should be 1.
	27	+- altr,has-mmu: Specifies CPU support MMU support, should be 1.
	28	+- altr,has-initda: Specifies CPU support initda instruction, should be 1.
	29	+- altr,reset-addr: Specifies CPU reset address
	30	+- altr,fast-tlb-miss-addr: Specifies CPU fast TLB miss exception address
	31	+- altr,exception-addr: Specifies CPU exception address
	32	+
	33	+Optional properties:
	34	+- altr,has-div: Specifies CPU hardware divide support
	35	+- altr,implementation: Nios II core implementation, this should be "fast";
	36	+
	37	+Example:
	38	+
	39	+cpu@0x0 {
	40	+ device_type = "cpu";
	41	+ compatible = "altr,nios2-1.0";
	42	+ reg = <0>;
	43	+ interrupt-controller;
	44	+ #interrupt-cells = <1>;
	45	+ clock-frequency = <125000000>;
	46	+ dcache-line-size = <32>;
	47	+ icache-line-size = <32>;
	48	+ dcache-size = <32768>;
	49	+ icache-size = <32768>;
	50	+ altr,implementation = "fast";
	51	+ altr,pid-num-bits = <8>;
	52	+ altr,tlb-num-ways = <16>;
	53	+ altr,tlb-num-entries = <128>;
	54	+ altr,tlb-ptr-sz = <7>;
	55	+ altr,has-div = <1>;
	56	+ altr,has-mul = <1>;
	57	+ altr,reset-addr = <0xc2800000>;
	58	+ altr,fast-tlb-miss-addr = <0xc7fff400>;
	59	+ altr,exception-addr = <0xd0000020>;
	60	+ altr,has-initda = <1>;
	61	+ altr,has-mmu = <1>;
	62	+};

Documentation/devicetree/bindings/nios2/timer.txt

Diff comments View file @ 95acd4c

	1	+Altera Timer
	2	+
	3	+Required properties:
	4	+
	5	+- compatible : should be "altr,timer-1.0"
	6	+- reg : Specifies base physical address and size of the registers.
	7	+- interrupt-parent: phandle of the interrupt controller
	8	+- interrupts : Should contain the timer interrupt number
	9	+- clock-frequency : The frequency of the clock that drives the counter, in Hz.
	10	+
	11	+Example:
	12	+
	13	+timer {
	14	+ compatible = "altr,timer-1.0";
	15	+ reg = <0x00400000 0x00000020>;
	16	+ interrupt-parent = <&cpu>;
	17	+ interrupts = <11>;
	18	+ clock-frequency = <125000000>;
	19	+};

arch/nios2/boot/dts/3c120_devboard.dts

Diff comments View file @ 95acd4c

	1	+/*
	2	+ * Copyright (C) 2013 Altera Corporation
	3	+ *
	4	+ * This program is free software; you can redistribute it and/or modify
	5	+ * it under the terms of the GNU General Public License as published by
	6	+ * the Free Software Foundation; either version 2 of the License, or
	7	+ * (at your option) any later version.
	8	+ *
	9	+ * This program is distributed in the hope that it will be useful,
	10	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	+ * GNU General Public License for more details.
	13	+ *
	14	+ * You should have received a copy of the GNU General Public License
	15	+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
	16	+ *
	17	+ * This file is generated by sopc2dts.
	18	+ */
	19	+
	20	+/dts-v1/;
	21	+
	22	+/ {
	23	+ model = "altr,qsys_ghrd_3c120";
	24	+ compatible = "altr,qsys_ghrd_3c120";
	25	+ #address-cells = <1>;
	26	+ #size-cells = <1>;
	27	+
	28	+ cpus {
	29	+ #address-cells = <1>;
	30	+ #size-cells = <0>;
	31	+
	32	+ cpu: cpu@0x0 {
	33	+ device_type = "cpu";
	34	+ compatible = "altr,nios2-1.0";
	35	+ reg = <0x00000000>;
	36	+ interrupt-controller;
	37	+ #interrupt-cells = <1>;
	38	+ clock-frequency = <125000000>;
	39	+ dcache-line-size = <32>;
	40	+ icache-line-size = <32>;
	41	+ dcache-size = <32768>;
	42	+ icache-size = <32768>;
	43	+ altr,implementation = "fast";
	44	+ altr,pid-num-bits = <8>;
	45	+ altr,tlb-num-ways = <16>;
	46	+ altr,tlb-num-entries = <128>;
	47	+ altr,tlb-ptr-sz = <7>;
	48	+ altr,has-div = <1>;
	49	+ altr,has-mul = <1>;
	50	+ altr,reset-addr = <0xc2800000>;
	51	+ altr,fast-tlb-miss-addr = <0xc7fff400>;
	52	+ altr,exception-addr = <0xd0000020>;
	53	+ altr,has-initda = <1>;
	54	+ altr,has-mmu = <1>;
	55	+ };
	56	+ };
	57	+
	58	+ memory@0 {
	59	+ device_type = "memory";
	60	+ reg = <0x10000000 0x08000000>,
	61	+ <0x07fff400 0x00000400>;
	62	+ };
	63	+
	64	+ sopc@0 {
	65	+ device_type = "soc";
	66	+ ranges;
	67	+ #address-cells = <1>;
	68	+ #size-cells = <1>;
	69	+ compatible = "altr,avalon", "simple-bus";
	70	+ bus-frequency = <125000000>;
	71	+
	72	+ pb_cpu_to_io: bridge@0x8000000 {
	73	+ compatible = "simple-bus";
	74	+ reg = <0x08000000 0x00800000>;
	75	+ #address-cells = <1>;
	76	+ #size-cells = <1>;
	77	+ ranges = <0x00002000 0x08002000 0x00002000>,
	78	+ <0x00004000 0x08004000 0x00000400>,
	79	+ <0x00004400 0x08004400 0x00000040>,
	80	+ <0x00004800 0x08004800 0x00000040>,
	81	+ <0x00004c80 0x08004c80 0x00000020>,
	82	+ <0x00004d50 0x08004d50 0x00000008>,
	83	+ <0x00008000 0x08008000 0x00000020>,
	84	+ <0x00400000 0x08400000 0x00000020>;
	85	+
	86	+ timer_1ms: timer@0x400000 {
	87	+ compatible = "altr,timer-1.0";
	88	+ reg = <0x00400000 0x00000020>;
	89	+ interrupt-parent = <&cpu>;
	90	+ interrupts = <11>;
	91	+ clock-frequency = <125000000>;
	92	+ };
	93	+
	94	+ timer_0: timer@0x8000 {
	95	+ compatible = "altr,timer-1.0";
	96	+ reg = < 0x00008000 0x00000020 >;
	97	+ interrupt-parent = < &cpu >;
	98	+ interrupts = < 5 >;
	99	+ clock-frequency = < 125000000 >;
	100	+ };
	101	+
	102	+ jtag_uart: serial@0x4d50 {
	103	+ compatible = "altr,juart-1.0";
	104	+ reg = <0x00004d50 0x00000008>;
	105	+ interrupt-parent = <&cpu>;
	106	+ interrupts = <1>;
	107	+ };
	108	+
	109	+ tse_mac: ethernet@0x4000 {
	110	+ compatible = "altr,tse-1.0";
	111	+ reg = <0x00004000 0x00000400>,
	112	+ <0x00004400 0x00000040>,
	113	+ <0x00004800 0x00000040>,
	114	+ <0x00002000 0x00002000>;
	115	+ reg-names = "control_port", "rx_csr", "tx_csr", "s1";
	116	+ interrupt-parent = <&cpu>;
	117	+ interrupts = <2 3>;
	118	+ interrupt-names = "rx_irq", "tx_irq";
	119	+ rx-fifo-depth = <8192>;
	120	+ tx-fifo-depth = <8192>;
	121	+ max-frame-size = <1518>;
	122	+ local-mac-address = [ 00 00 00 00 00 00 ];
	123	+ phy-mode = "rgmii-id";
	124	+ phy-handle = <&phy0>;
	125	+ tse_mac_mdio: mdio {
	126	+ compatible = "altr,tse-mdio";
	127	+ #address-cells = <1>;
	128	+ #size-cells = <0>;
	129	+ phy0: ethernet-phy@18 {
	130	+ reg = <18>;
	131	+ device_type = "ethernet-phy";
	132	+ };
	133	+ };
	134	+ };
	135	+
	136	+ uart: serial@0x4c80 {
	137	+ compatible = "altr,uart-1.0";
	138	+ reg = <0x00004c80 0x00000020>;
	139	+ interrupt-parent = <&cpu>;
	140	+ interrupts = <10>;
	141	+ current-speed = <115200>;
	142	+ clock-frequency = <62500000>;
	143	+ };
	144	+ };
	145	+
	146	+ cfi_flash_64m: flash@0x0 {
	147	+ compatible = "cfi-flash";
	148	+ reg = <0x00000000 0x04000000>;
	149	+ bank-width = <2>;
	150	+ device-width = <1>;
	151	+ #address-cells = <1>;
	152	+ #size-cells = <1>;
	153	+
	154	+ partition@800000 {
	155	+ reg = <0x00800000 0x01e00000>;
	156	+ label = "JFFS2 Filesystem";
	157	+ };
	158	+ };
	159	+ };
	160	+
	161	+ chosen {
	162	+ bootargs = "debug console=ttyJ0,115200";
	163	+ };
	164	+};

arch/nios2/boot/linked_dtb.S

Diff comments View file @ 95acd4c

	1	+/*
	2	+ * Copyright (C) 2011 Thomas Chou <thomas@wytron.com.tw>
	3	+ *
	4	+ * This program is free software; you can redistribute it and/or modify
	5	+ * it under the terms of the GNU General Public License as published by
	6	+ * the Free Software Foundation; either version 2 of the License, or
	7	+ * (at your option) any later version.
	8	+ *
	9	+ * This program is distributed in the hope that it will be useful,
	10	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	+ * GNU General Public License for more details.
	13	+ *
	14	+ * You should have received a copy of the GNU General Public License
	15	+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
	16	+ *
	17	+ */
	18	+.section .dtb.init.rodata,"a"
	19	+.incbin "arch/nios2/boot/system.dtb"

arch/nios2/kernel/prom.c

Diff comments View file @ 95acd4c

	1	+/*
	2	+ * Device tree support
	3	+ *
	4	+ * Copyright (C) 2013 Altera Corporation
	5	+ * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
	6	+ *
	7	+ * Based on MIPS support for CONFIG_OF device tree support
	8	+ *
	9	+ * Copyright (C) 2010 Cisco Systems Inc. <dediao@cisco.com>
	10	+ *
	11	+ * This program is free software; you can redistribute it and/or modify
	12	+ * it under the terms of the GNU General Public License as published by
	13	+ * the Free Software Foundation; either version 2 of the License, or
	14	+ * (at your option) any later version.
	15	+ *
	16	+ * This program is distributed in the hope that it will be useful,
	17	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	+ * GNU General Public License for more details.
	20	+ *
	21	+ * You should have received a copy of the GNU General Public License
	22	+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
	23	+ *
	24	+ */
	25	+
	26	+#include <linux/init.h>
	27	+#include <linux/types.h>
	28	+#include <linux/bootmem.h>
	29	+#include <linux/of.h>
	30	+#include <linux/of_fdt.h>
	31	+#include <linux/io.h>
	32	+
	33	+#include <asm/sections.h>
	34	+
	35	+void __init early_init_dt_add_memory_arch(u64 base, u64 size)
	36	+{
	37	+ u64 kernel_start = (u64)virt_to_phys(_text);
	38	+
	39	+ if (!memory_size &&
	40	+ (kernel_start >= base) && (kernel_start < (base + size)))
	41	+ memory_size = size;
	42	+
	43	+}
	44	+
	45	+void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
	46	+{
	47	+ return alloc_bootmem_align(size, align);
	48	+}
	49	+
	50	+void __init early_init_devtree(void *params)
	51	+{
	52	+ __be32 dtb = (u32 )__dtb_start;
	53	+#if defined(CONFIG_NIOS2_DTB_AT_PHYS_ADDR)
	54	+ if (be32_to_cpup((__be32 *)CONFIG_NIOS2_DTB_PHYS_ADDR) ==
	55	+ OF_DT_HEADER) {
	56	+ params = (void *)CONFIG_NIOS2_DTB_PHYS_ADDR;
	57	+ early_init_dt_scan(params);
	58	+ return;
	59	+ }
	60	+#endif
	61	+ if (be32_to_cpu((__be32) *dtb) == OF_DT_HEADER)
	62	+ params = (void *)__dtb_start;
	63	+
	64	+ early_init_dt_scan(params);
	65	+}

arch/nios2/platform/platform.c

Diff comments View file @ 95acd4c

	1	+/*
	2	+ * Copyright (C) 2013 Altera Corporation
	3	+ * Copyright (C) 2011 Thomas Chou
	4	+ * Copyright (C) 2011 Walter Goossens
	5	+ *
	6	+ * This file is subject to the terms and conditions of the GNU General
	7	+ * Public License. See the file COPYING in the main directory of this
	8	+ * archive for more details.
	9	+ */
	10	+
	11	+#include <linux/init.h>
	12	+#include <linux/of_platform.h>
	13	+#include <linux/of_address.h>
	14	+#include <linux/of_fdt.h>
	15	+#include <linux/err.h>
	16	+#include <linux/slab.h>
	17	+#include <linux/sys_soc.h>
	18	+#include <linux/io.h>
	19	+
	20	+static int __init nios2_soc_device_init(void)
	21	+{
	22	+ struct soc_device *soc_dev;
	23	+ struct soc_device_attribute *soc_dev_attr;
	24	+ const char *machine;
	25	+
	26	+ soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
	27	+ if (soc_dev_attr) {
	28	+ machine = of_flat_dt_get_machine_name();
	29	+ if (machine)
	30	+ soc_dev_attr->machine = kasprintf(GFP_KERNEL, "%s",
	31	+ machine);
	32	+
	33	+ soc_dev_attr->family = "Nios II";
	34	+
	35	+ soc_dev = soc_device_register(soc_dev_attr);
	36	+ if (IS_ERR(soc_dev)) {
	37	+ kfree(soc_dev_attr->machine);
	38	+ kfree(soc_dev_attr);
	39	+ }
	40	+ }
	41	+
	42	+ return of_platform_populate(NULL, of_default_bus_match_table,
	43	+ NULL, NULL);
	44	+}
	45	+
	46	+device_initcall(nios2_soc_device_init);