Eric Lee / smarc-ti-linux-kernel

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Commit 96a30175f927facfb421655ef08b7a0fe546fbed

Authored by Arnd Bergmann
Committed by David S. Miller
1 parent e9b106b8fb

net: am2150: fix nmclan_cs.c shared interrupt handling 

A recent patch tried to work around a valid warning for the use of a
deprecated interface by blindly changing from the old
pcmcia_request_exclusive_irq() interface to pcmcia_request_irq().

This driver has an interrupt handler that is not currently aware
of shared interrupts, but can be easily converted to be.
At the moment, the driver reads the interrupt status register
repeatedly until it contains only zeroes in the interesting bits,
and handles each bit individually.

This patch adds the missing part of returning IRQ_NONE in case none
of the bits are set to start with, so we can move on to the next
interrupt source.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Fixes: 5f5316fcd08ef7 ("am2150: Update nmclan_cs.c to use update PCMCIA API")
Signed-off-by: David S. Miller <davem@davemloft.net>

Showing 1 changed file with 2 additions and 0 deletions Inline Diff

drivers/net/ethernet/amd/nmclan_cs.c
Diff comments   View file @ 96a3017
1 /* ---------------------------------------------------------------------------- 1 /* ----------------------------------------------------------------------------
2 Linux PCMCIA ethernet adapter driver for the New Media Ethernet LAN. 2 Linux PCMCIA ethernet adapter driver for the New Media Ethernet LAN.
3 nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao 3 nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao
4 4
5 The Ethernet LAN uses the Advanced Micro Devices (AMD) Am79C940 Media 5 The Ethernet LAN uses the Advanced Micro Devices (AMD) Am79C940 Media
6 Access Controller for Ethernet (MACE). It is essentially the Am2150 6 Access Controller for Ethernet (MACE). It is essentially the Am2150
7 PCMCIA Ethernet card contained in the Am2150 Demo Kit. 7 PCMCIA Ethernet card contained in the Am2150 Demo Kit.
8 8
9 Written by Roger C. Pao <rpao@paonet.org> 9 Written by Roger C. Pao <rpao@paonet.org>
10 Copyright 1995 Roger C. Pao 10 Copyright 1995 Roger C. Pao
11 Linux 2.5 cleanups Copyright Red Hat 2003 11 Linux 2.5 cleanups Copyright Red Hat 2003
12 12
13 This software may be used and distributed according to the terms of 13 This software may be used and distributed according to the terms of
14 the GNU General Public License. 14 the GNU General Public License.
15 15
16 Ported to Linux 1.3.* network driver environment by 16 Ported to Linux 1.3.* network driver environment by
17 Matti Aarnio <mea@utu.fi> 17 Matti Aarnio <mea@utu.fi>
18 18
19 References 19 References
20 20
21 Am2150 Technical Reference Manual, Revision 1.0, August 17, 1993 21 Am2150 Technical Reference Manual, Revision 1.0, August 17, 1993
22 Am79C940 (MACE) Data Sheet, 1994 22 Am79C940 (MACE) Data Sheet, 1994
23 Am79C90 (C-LANCE) Data Sheet, 1994 23 Am79C90 (C-LANCE) Data Sheet, 1994
24 Linux PCMCIA Programmer's Guide v1.17 24 Linux PCMCIA Programmer's Guide v1.17
25 /usr/src/linux/net/inet/dev.c, Linux kernel 1.2.8 25 /usr/src/linux/net/inet/dev.c, Linux kernel 1.2.8
26 26
27 Eric Mears, New Media Corporation 27 Eric Mears, New Media Corporation
28 Tom Pollard, New Media Corporation 28 Tom Pollard, New Media Corporation
29 Dean Siasoyco, New Media Corporation 29 Dean Siasoyco, New Media Corporation
30 Ken Lesniak, Silicon Graphics, Inc. <lesniak@boston.sgi.com> 30 Ken Lesniak, Silicon Graphics, Inc. <lesniak@boston.sgi.com>
31 Donald Becker <becker@scyld.com> 31 Donald Becker <becker@scyld.com>
32 David Hinds <dahinds@users.sourceforge.net> 32 David Hinds <dahinds@users.sourceforge.net>
33 33
34 The Linux client driver is based on the 3c589_cs.c client driver by 34 The Linux client driver is based on the 3c589_cs.c client driver by
35 David Hinds. 35 David Hinds.
36 36
37 The Linux network driver outline is based on the 3c589_cs.c driver, 37 The Linux network driver outline is based on the 3c589_cs.c driver,
38 the 8390.c driver, and the example skeleton.c kernel code, which are 38 the 8390.c driver, and the example skeleton.c kernel code, which are
39 by Donald Becker. 39 by Donald Becker.
40 40
41 The Am2150 network driver hardware interface code is based on the 41 The Am2150 network driver hardware interface code is based on the
42 OS/9000 driver for the New Media Ethernet LAN by Eric Mears. 42 OS/9000 driver for the New Media Ethernet LAN by Eric Mears.
43 43
44 Special thanks for testing and help in debugging this driver goes 44 Special thanks for testing and help in debugging this driver goes
45 to Ken Lesniak. 45 to Ken Lesniak.
46 46
47 ------------------------------------------------------------------------------- 47 -------------------------------------------------------------------------------
48 Driver Notes and Issues 48 Driver Notes and Issues
49 ------------------------------------------------------------------------------- 49 -------------------------------------------------------------------------------
50 50
51 1. Developed on a Dell 320SLi 51 1. Developed on a Dell 320SLi
52 PCMCIA Card Services 2.6.2 52 PCMCIA Card Services 2.6.2
53 Linux dell 1.2.10 #1 Thu Jun 29 20:23:41 PDT 1995 i386 53 Linux dell 1.2.10 #1 Thu Jun 29 20:23:41 PDT 1995 i386
54 54
55 2. rc.pcmcia may require loading pcmcia_core with io_speed=300: 55 2. rc.pcmcia may require loading pcmcia_core with io_speed=300:
56 'insmod pcmcia_core.o io_speed=300'. 56 'insmod pcmcia_core.o io_speed=300'.
57 This will avoid problems with fast systems which causes rx_framecnt 57 This will avoid problems with fast systems which causes rx_framecnt
58 to return random values. 58 to return random values.
59 59
60 3. If hot extraction does not work for you, use 'ifconfig eth0 down' 60 3. If hot extraction does not work for you, use 'ifconfig eth0 down'
61 before extraction. 61 before extraction.
62 62
63 4. There is a bad slow-down problem in this driver. 63 4. There is a bad slow-down problem in this driver.
64 64
65 5. Future: Multicast processing. In the meantime, do _not_ compile your 65 5. Future: Multicast processing. In the meantime, do _not_ compile your
66 kernel with multicast ip enabled. 66 kernel with multicast ip enabled.
67 67
68 ------------------------------------------------------------------------------- 68 -------------------------------------------------------------------------------
69 History 69 History
70 ------------------------------------------------------------------------------- 70 -------------------------------------------------------------------------------
71 Log: nmclan_cs.c,v 71 Log: nmclan_cs.c,v
72 * 2.5.75-ac1 2003/07/11 Alan Cox <alan@lxorguk.ukuu.org.uk> 72 * 2.5.75-ac1 2003/07/11 Alan Cox <alan@lxorguk.ukuu.org.uk>
73 * Fixed hang on card eject as we probe it 73 * Fixed hang on card eject as we probe it
74 * Cleaned up to use new style locking. 74 * Cleaned up to use new style locking.
75 * 75 *
76 * Revision 0.16 1995/07/01 06:42:17 rpao 76 * Revision 0.16 1995/07/01 06:42:17 rpao
77 * Bug fix: nmclan_reset() called CardServices incorrectly. 77 * Bug fix: nmclan_reset() called CardServices incorrectly.
78 * 78 *
79 * Revision 0.15 1995/05/24 08:09:47 rpao 79 * Revision 0.15 1995/05/24 08:09:47 rpao
80 * Re-implement MULTI_TX dev->tbusy handling. 80 * Re-implement MULTI_TX dev->tbusy handling.
81 * 81 *
82 * Revision 0.14 1995/05/23 03:19:30 rpao 82 * Revision 0.14 1995/05/23 03:19:30 rpao
83 * Added, in nmclan_config(), "tuple.Attributes = 0;". 83 * Added, in nmclan_config(), "tuple.Attributes = 0;".
84 * Modified MACE ID check to ignore chip revision level. 84 * Modified MACE ID check to ignore chip revision level.
85 * Avoid tx_free_frames race condition between _start_xmit and _interrupt. 85 * Avoid tx_free_frames race condition between _start_xmit and _interrupt.
86 * 86 *
87 * Revision 0.13 1995/05/18 05:56:34 rpao 87 * Revision 0.13 1995/05/18 05:56:34 rpao
88 * Statistics changes. 88 * Statistics changes.
89 * Bug fix: nmclan_reset did not enable TX and RX: call restore_multicast_list. 89 * Bug fix: nmclan_reset did not enable TX and RX: call restore_multicast_list.
90 * Bug fix: mace_interrupt checks ~MACE_IMR_DEFAULT. Fixes driver lockup. 90 * Bug fix: mace_interrupt checks ~MACE_IMR_DEFAULT. Fixes driver lockup.
91 * 91 *
92 * Revision 0.12 1995/05/14 00:12:23 rpao 92 * Revision 0.12 1995/05/14 00:12:23 rpao
93 * Statistics overhaul. 93 * Statistics overhaul.
94 * 94 *
95 95
96 95/05/13 rpao V0.10a 96 95/05/13 rpao V0.10a
97 Bug fix: MACE statistics counters used wrong I/O ports. 97 Bug fix: MACE statistics counters used wrong I/O ports.
98 Bug fix: mace_interrupt() needed to allow statistics to be 98 Bug fix: mace_interrupt() needed to allow statistics to be
99 processed without RX or TX interrupts pending. 99 processed without RX or TX interrupts pending.
100 95/05/11 rpao V0.10 100 95/05/11 rpao V0.10
101 Multiple transmit request processing. 101 Multiple transmit request processing.
102 Modified statistics to use MACE counters where possible. 102 Modified statistics to use MACE counters where possible.
103 95/05/10 rpao V0.09 Bug fix: Must use IO_DATA_PATH_WIDTH_AUTO. 103 95/05/10 rpao V0.09 Bug fix: Must use IO_DATA_PATH_WIDTH_AUTO.
104 *Released 104 *Released
105 95/05/10 rpao V0.08 105 95/05/10 rpao V0.08
106 Bug fix: Make all non-exported functions private by using 106 Bug fix: Make all non-exported functions private by using
107 static keyword. 107 static keyword.
108 Bug fix: Test IntrCnt _before_ reading MACE_IR. 108 Bug fix: Test IntrCnt _before_ reading MACE_IR.
109 95/05/10 rpao V0.07 Statistics. 109 95/05/10 rpao V0.07 Statistics.
110 95/05/09 rpao V0.06 Fix rx_framecnt problem by addition of PCIC wait states. 110 95/05/09 rpao V0.06 Fix rx_framecnt problem by addition of PCIC wait states.
111 111
112 ---------------------------------------------------------------------------- */ 112 ---------------------------------------------------------------------------- */
113 113
114 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 114 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
115 115
116 #define DRV_NAME "nmclan_cs" 116 #define DRV_NAME "nmclan_cs"
117 #define DRV_VERSION "0.16" 117 #define DRV_VERSION "0.16"
118 118
119 119
120 /* ---------------------------------------------------------------------------- 120 /* ----------------------------------------------------------------------------
121 Conditional Compilation Options 121 Conditional Compilation Options
122 ---------------------------------------------------------------------------- */ 122 ---------------------------------------------------------------------------- */
123 123
124 #define MULTI_TX 0 124 #define MULTI_TX 0
125 #define RESET_ON_TIMEOUT 1 125 #define RESET_ON_TIMEOUT 1
126 #define TX_INTERRUPTABLE 1 126 #define TX_INTERRUPTABLE 1
127 #define RESET_XILINX 0 127 #define RESET_XILINX 0
128 128
129 /* ---------------------------------------------------------------------------- 129 /* ----------------------------------------------------------------------------
130 Include Files 130 Include Files
131 ---------------------------------------------------------------------------- */ 131 ---------------------------------------------------------------------------- */
132 132
133 #include <linux/module.h> 133 #include <linux/module.h>
134 #include <linux/kernel.h> 134 #include <linux/kernel.h>
135 #include <linux/ptrace.h> 135 #include <linux/ptrace.h>
136 #include <linux/slab.h> 136 #include <linux/slab.h>
137 #include <linux/string.h> 137 #include <linux/string.h>
138 #include <linux/timer.h> 138 #include <linux/timer.h>
139 #include <linux/interrupt.h> 139 #include <linux/interrupt.h>
140 #include <linux/in.h> 140 #include <linux/in.h>
141 #include <linux/delay.h> 141 #include <linux/delay.h>
142 #include <linux/ethtool.h> 142 #include <linux/ethtool.h>
143 #include <linux/netdevice.h> 143 #include <linux/netdevice.h>
144 #include <linux/etherdevice.h> 144 #include <linux/etherdevice.h>
145 #include <linux/skbuff.h> 145 #include <linux/skbuff.h>
146 #include <linux/if_arp.h> 146 #include <linux/if_arp.h>
147 #include <linux/ioport.h> 147 #include <linux/ioport.h>
148 #include <linux/bitops.h> 148 #include <linux/bitops.h>
149 149
150 #include <pcmcia/cisreg.h> 150 #include <pcmcia/cisreg.h>
151 #include <pcmcia/cistpl.h> 151 #include <pcmcia/cistpl.h>
152 #include <pcmcia/ds.h> 152 #include <pcmcia/ds.h>
153 153
154 #include <asm/uaccess.h> 154 #include <asm/uaccess.h>
155 #include <asm/io.h> 155 #include <asm/io.h>
156 156
157 /* ---------------------------------------------------------------------------- 157 /* ----------------------------------------------------------------------------
158 Defines 158 Defines
159 ---------------------------------------------------------------------------- */ 159 ---------------------------------------------------------------------------- */
160 160
161 #define MACE_LADRF_LEN 8 161 #define MACE_LADRF_LEN 8
162 /* 8 bytes in Logical Address Filter */ 162 /* 8 bytes in Logical Address Filter */
163 163
164 /* Loop Control Defines */ 164 /* Loop Control Defines */
165 #define MACE_MAX_IR_ITERATIONS 10 165 #define MACE_MAX_IR_ITERATIONS 10
166 #define MACE_MAX_RX_ITERATIONS 12 166 #define MACE_MAX_RX_ITERATIONS 12
167 /* 167 /*
168 TBD: Dean brought this up, and I assumed the hardware would 168 TBD: Dean brought this up, and I assumed the hardware would
169 handle it: 169 handle it:
170 170
171 If MACE_MAX_RX_ITERATIONS is > 1, rx_framecnt may still be 171 If MACE_MAX_RX_ITERATIONS is > 1, rx_framecnt may still be
172 non-zero when the isr exits. We may not get another interrupt 172 non-zero when the isr exits. We may not get another interrupt
173 to process the remaining packets for some time. 173 to process the remaining packets for some time.
174 */ 174 */
175 175
176 /* 176 /*
177 The Am2150 has a Xilinx XC3042 field programmable gate array (FPGA) 177 The Am2150 has a Xilinx XC3042 field programmable gate array (FPGA)
178 which manages the interface between the MACE and the PCMCIA bus. It 178 which manages the interface between the MACE and the PCMCIA bus. It
179 also includes buffer management for the 32K x 8 SRAM to control up to 179 also includes buffer management for the 32K x 8 SRAM to control up to
180 four transmit and 12 receive frames at a time. 180 four transmit and 12 receive frames at a time.
181 */ 181 */
182 #define AM2150_MAX_TX_FRAMES 4 182 #define AM2150_MAX_TX_FRAMES 4
183 #define AM2150_MAX_RX_FRAMES 12 183 #define AM2150_MAX_RX_FRAMES 12
184 184
185 /* Am2150 Ethernet Card I/O Mapping */ 185 /* Am2150 Ethernet Card I/O Mapping */
186 #define AM2150_RCV 0x00 186 #define AM2150_RCV 0x00
187 #define AM2150_XMT 0x04 187 #define AM2150_XMT 0x04
188 #define AM2150_XMT_SKIP 0x09 188 #define AM2150_XMT_SKIP 0x09
189 #define AM2150_RCV_NEXT 0x0A 189 #define AM2150_RCV_NEXT 0x0A
190 #define AM2150_RCV_FRAME_COUNT 0x0B 190 #define AM2150_RCV_FRAME_COUNT 0x0B
191 #define AM2150_MACE_BANK 0x0C 191 #define AM2150_MACE_BANK 0x0C
192 #define AM2150_MACE_BASE 0x10 192 #define AM2150_MACE_BASE 0x10
193 193
194 /* MACE Registers */ 194 /* MACE Registers */
195 #define MACE_RCVFIFO 0 195 #define MACE_RCVFIFO 0
196 #define MACE_XMTFIFO 1 196 #define MACE_XMTFIFO 1
197 #define MACE_XMTFC 2 197 #define MACE_XMTFC 2
198 #define MACE_XMTFS 3 198 #define MACE_XMTFS 3
199 #define MACE_XMTRC 4 199 #define MACE_XMTRC 4
200 #define MACE_RCVFC 5 200 #define MACE_RCVFC 5
201 #define MACE_RCVFS 6 201 #define MACE_RCVFS 6
202 #define MACE_FIFOFC 7 202 #define MACE_FIFOFC 7
203 #define MACE_IR 8 203 #define MACE_IR 8
204 #define MACE_IMR 9 204 #define MACE_IMR 9
205 #define MACE_PR 10 205 #define MACE_PR 10
206 #define MACE_BIUCC 11 206 #define MACE_BIUCC 11
207 #define MACE_FIFOCC 12 207 #define MACE_FIFOCC 12
208 #define MACE_MACCC 13 208 #define MACE_MACCC 13
209 #define MACE_PLSCC 14 209 #define MACE_PLSCC 14
210 #define MACE_PHYCC 15 210 #define MACE_PHYCC 15
211 #define MACE_CHIPIDL 16 211 #define MACE_CHIPIDL 16
212 #define MACE_CHIPIDH 17 212 #define MACE_CHIPIDH 17
213 #define MACE_IAC 18 213 #define MACE_IAC 18
214 /* Reserved */ 214 /* Reserved */
215 #define MACE_LADRF 20 215 #define MACE_LADRF 20
216 #define MACE_PADR 21 216 #define MACE_PADR 21
217 /* Reserved */ 217 /* Reserved */
218 /* Reserved */ 218 /* Reserved */
219 #define MACE_MPC 24 219 #define MACE_MPC 24
220 /* Reserved */ 220 /* Reserved */
221 #define MACE_RNTPC 26 221 #define MACE_RNTPC 26
222 #define MACE_RCVCC 27 222 #define MACE_RCVCC 27
223 /* Reserved */ 223 /* Reserved */
224 #define MACE_UTR 29 224 #define MACE_UTR 29
225 #define MACE_RTR1 30 225 #define MACE_RTR1 30
226 #define MACE_RTR2 31 226 #define MACE_RTR2 31
227 227
228 /* MACE Bit Masks */ 228 /* MACE Bit Masks */
229 #define MACE_XMTRC_EXDEF 0x80 229 #define MACE_XMTRC_EXDEF 0x80
230 #define MACE_XMTRC_XMTRC 0x0F 230 #define MACE_XMTRC_XMTRC 0x0F
231 231
232 #define MACE_XMTFS_XMTSV 0x80 232 #define MACE_XMTFS_XMTSV 0x80
233 #define MACE_XMTFS_UFLO 0x40 233 #define MACE_XMTFS_UFLO 0x40
234 #define MACE_XMTFS_LCOL 0x20 234 #define MACE_XMTFS_LCOL 0x20
235 #define MACE_XMTFS_MORE 0x10 235 #define MACE_XMTFS_MORE 0x10
236 #define MACE_XMTFS_ONE 0x08 236 #define MACE_XMTFS_ONE 0x08
237 #define MACE_XMTFS_DEFER 0x04 237 #define MACE_XMTFS_DEFER 0x04
238 #define MACE_XMTFS_LCAR 0x02 238 #define MACE_XMTFS_LCAR 0x02
239 #define MACE_XMTFS_RTRY 0x01 239 #define MACE_XMTFS_RTRY 0x01
240 240
241 #define MACE_RCVFS_RCVSTS 0xF000 241 #define MACE_RCVFS_RCVSTS 0xF000
242 #define MACE_RCVFS_OFLO 0x8000 242 #define MACE_RCVFS_OFLO 0x8000
243 #define MACE_RCVFS_CLSN 0x4000 243 #define MACE_RCVFS_CLSN 0x4000
244 #define MACE_RCVFS_FRAM 0x2000 244 #define MACE_RCVFS_FRAM 0x2000
245 #define MACE_RCVFS_FCS 0x1000 245 #define MACE_RCVFS_FCS 0x1000
246 246
247 #define MACE_FIFOFC_RCVFC 0xF0 247 #define MACE_FIFOFC_RCVFC 0xF0
248 #define MACE_FIFOFC_XMTFC 0x0F 248 #define MACE_FIFOFC_XMTFC 0x0F
249 249
250 #define MACE_IR_JAB 0x80 250 #define MACE_IR_JAB 0x80
251 #define MACE_IR_BABL 0x40 251 #define MACE_IR_BABL 0x40
252 #define MACE_IR_CERR 0x20 252 #define MACE_IR_CERR 0x20
253 #define MACE_IR_RCVCCO 0x10 253 #define MACE_IR_RCVCCO 0x10
254 #define MACE_IR_RNTPCO 0x08 254 #define MACE_IR_RNTPCO 0x08
255 #define MACE_IR_MPCO 0x04 255 #define MACE_IR_MPCO 0x04
256 #define MACE_IR_RCVINT 0x02 256 #define MACE_IR_RCVINT 0x02
257 #define MACE_IR_XMTINT 0x01 257 #define MACE_IR_XMTINT 0x01
258 258
259 #define MACE_MACCC_PROM 0x80 259 #define MACE_MACCC_PROM 0x80
260 #define MACE_MACCC_DXMT2PD 0x40 260 #define MACE_MACCC_DXMT2PD 0x40
261 #define MACE_MACCC_EMBA 0x20 261 #define MACE_MACCC_EMBA 0x20
262 #define MACE_MACCC_RESERVED 0x10 262 #define MACE_MACCC_RESERVED 0x10
263 #define MACE_MACCC_DRCVPA 0x08 263 #define MACE_MACCC_DRCVPA 0x08
264 #define MACE_MACCC_DRCVBC 0x04 264 #define MACE_MACCC_DRCVBC 0x04
265 #define MACE_MACCC_ENXMT 0x02 265 #define MACE_MACCC_ENXMT 0x02
266 #define MACE_MACCC_ENRCV 0x01 266 #define MACE_MACCC_ENRCV 0x01
267 267
268 #define MACE_PHYCC_LNKFL 0x80 268 #define MACE_PHYCC_LNKFL 0x80
269 #define MACE_PHYCC_DLNKTST 0x40 269 #define MACE_PHYCC_DLNKTST 0x40
270 #define MACE_PHYCC_REVPOL 0x20 270 #define MACE_PHYCC_REVPOL 0x20
271 #define MACE_PHYCC_DAPC 0x10 271 #define MACE_PHYCC_DAPC 0x10
272 #define MACE_PHYCC_LRT 0x08 272 #define MACE_PHYCC_LRT 0x08
273 #define MACE_PHYCC_ASEL 0x04 273 #define MACE_PHYCC_ASEL 0x04
274 #define MACE_PHYCC_RWAKE 0x02 274 #define MACE_PHYCC_RWAKE 0x02
275 #define MACE_PHYCC_AWAKE 0x01 275 #define MACE_PHYCC_AWAKE 0x01
276 276
277 #define MACE_IAC_ADDRCHG 0x80 277 #define MACE_IAC_ADDRCHG 0x80
278 #define MACE_IAC_PHYADDR 0x04 278 #define MACE_IAC_PHYADDR 0x04
279 #define MACE_IAC_LOGADDR 0x02 279 #define MACE_IAC_LOGADDR 0x02
280 280
281 #define MACE_UTR_RTRE 0x80 281 #define MACE_UTR_RTRE 0x80
282 #define MACE_UTR_RTRD 0x40 282 #define MACE_UTR_RTRD 0x40
283 #define MACE_UTR_RPA 0x20 283 #define MACE_UTR_RPA 0x20
284 #define MACE_UTR_FCOLL 0x10 284 #define MACE_UTR_FCOLL 0x10
285 #define MACE_UTR_RCVFCSE 0x08 285 #define MACE_UTR_RCVFCSE 0x08
286 #define MACE_UTR_LOOP_INCL_MENDEC 0x06 286 #define MACE_UTR_LOOP_INCL_MENDEC 0x06
287 #define MACE_UTR_LOOP_NO_MENDEC 0x04 287 #define MACE_UTR_LOOP_NO_MENDEC 0x04
288 #define MACE_UTR_LOOP_EXTERNAL 0x02 288 #define MACE_UTR_LOOP_EXTERNAL 0x02
289 #define MACE_UTR_LOOP_NONE 0x00 289 #define MACE_UTR_LOOP_NONE 0x00
290 #define MACE_UTR_RESERVED 0x01 290 #define MACE_UTR_RESERVED 0x01
291 291
292 /* Switch MACE register bank (only 0 and 1 are valid) */ 292 /* Switch MACE register bank (only 0 and 1 are valid) */
293 #define MACEBANK(win_num) outb((win_num), ioaddr + AM2150_MACE_BANK) 293 #define MACEBANK(win_num) outb((win_num), ioaddr + AM2150_MACE_BANK)
294 294
295 #define MACE_IMR_DEFAULT \ 295 #define MACE_IMR_DEFAULT \
296 (0xFF - \ 296 (0xFF - \
297 ( \ 297 ( \
298 MACE_IR_CERR | \ 298 MACE_IR_CERR | \
299 MACE_IR_RCVCCO | \ 299 MACE_IR_RCVCCO | \
300 MACE_IR_RNTPCO | \ 300 MACE_IR_RNTPCO | \
301 MACE_IR_MPCO | \ 301 MACE_IR_MPCO | \
302 MACE_IR_RCVINT | \ 302 MACE_IR_RCVINT | \
303 MACE_IR_XMTINT \ 303 MACE_IR_XMTINT \
304 ) \ 304 ) \
305 ) 305 )
306 #undef MACE_IMR_DEFAULT 306 #undef MACE_IMR_DEFAULT
307 #define MACE_IMR_DEFAULT 0x00 /* New statistics handling: grab everything */ 307 #define MACE_IMR_DEFAULT 0x00 /* New statistics handling: grab everything */
308 308
309 #define TX_TIMEOUT ((400*HZ)/1000) 309 #define TX_TIMEOUT ((400*HZ)/1000)
310 310
311 /* ---------------------------------------------------------------------------- 311 /* ----------------------------------------------------------------------------
312 Type Definitions 312 Type Definitions
313 ---------------------------------------------------------------------------- */ 313 ---------------------------------------------------------------------------- */
314 314
315 typedef struct _mace_statistics { 315 typedef struct _mace_statistics {
316 /* MACE_XMTFS */ 316 /* MACE_XMTFS */
317 int xmtsv; 317 int xmtsv;
318 int uflo; 318 int uflo;
319 int lcol; 319 int lcol;
320 int more; 320 int more;
321 int one; 321 int one;
322 int defer; 322 int defer;
323 int lcar; 323 int lcar;
324 int rtry; 324 int rtry;
325 325
326 /* MACE_XMTRC */ 326 /* MACE_XMTRC */
327 int exdef; 327 int exdef;
328 int xmtrc; 328 int xmtrc;
329 329
330 /* RFS1--Receive Status (RCVSTS) */ 330 /* RFS1--Receive Status (RCVSTS) */
331 int oflo; 331 int oflo;
332 int clsn; 332 int clsn;
333 int fram; 333 int fram;
334 int fcs; 334 int fcs;
335 335
336 /* RFS2--Runt Packet Count (RNTPC) */ 336 /* RFS2--Runt Packet Count (RNTPC) */
337 int rfs_rntpc; 337 int rfs_rntpc;
338 338
339 /* RFS3--Receive Collision Count (RCVCC) */ 339 /* RFS3--Receive Collision Count (RCVCC) */
340 int rfs_rcvcc; 340 int rfs_rcvcc;
341 341
342 /* MACE_IR */ 342 /* MACE_IR */
343 int jab; 343 int jab;
344 int babl; 344 int babl;
345 int cerr; 345 int cerr;
346 int rcvcco; 346 int rcvcco;
347 int rntpco; 347 int rntpco;
348 int mpco; 348 int mpco;
349 349
350 /* MACE_MPC */ 350 /* MACE_MPC */
351 int mpc; 351 int mpc;
352 352
353 /* MACE_RNTPC */ 353 /* MACE_RNTPC */
354 int rntpc; 354 int rntpc;
355 355
356 /* MACE_RCVCC */ 356 /* MACE_RCVCC */
357 int rcvcc; 357 int rcvcc;
358 } mace_statistics; 358 } mace_statistics;
359 359
360 typedef struct _mace_private { 360 typedef struct _mace_private {
361 struct pcmcia_device *p_dev; 361 struct pcmcia_device *p_dev;
362 struct net_device_stats linux_stats; /* Linux statistics counters */ 362 struct net_device_stats linux_stats; /* Linux statistics counters */
363 mace_statistics mace_stats; /* MACE chip statistics counters */ 363 mace_statistics mace_stats; /* MACE chip statistics counters */
364 364
365 /* restore_multicast_list() state variables */ 365 /* restore_multicast_list() state variables */
366 int multicast_ladrf[MACE_LADRF_LEN]; /* Logical address filter */ 366 int multicast_ladrf[MACE_LADRF_LEN]; /* Logical address filter */
367 int multicast_num_addrs; 367 int multicast_num_addrs;
368 368
369 char tx_free_frames; /* Number of free transmit frame buffers */ 369 char tx_free_frames; /* Number of free transmit frame buffers */
370 char tx_irq_disabled; /* MACE TX interrupt disabled */ 370 char tx_irq_disabled; /* MACE TX interrupt disabled */
371 371
372 spinlock_t bank_lock; /* Must be held if you step off bank 0 */ 372 spinlock_t bank_lock; /* Must be held if you step off bank 0 */
373 } mace_private; 373 } mace_private;
374 374
375 /* ---------------------------------------------------------------------------- 375 /* ----------------------------------------------------------------------------
376 Private Global Variables 376 Private Global Variables
377 ---------------------------------------------------------------------------- */ 377 ---------------------------------------------------------------------------- */
378 378
379 static const char *if_names[]={ 379 static const char *if_names[]={
380 "Auto", "10baseT", "BNC", 380 "Auto", "10baseT", "BNC",
381 }; 381 };
382 382
383 /* ---------------------------------------------------------------------------- 383 /* ----------------------------------------------------------------------------
384 Parameters 384 Parameters
385 These are the parameters that can be set during loading with 385 These are the parameters that can be set during loading with
386 'insmod'. 386 'insmod'.
387 ---------------------------------------------------------------------------- */ 387 ---------------------------------------------------------------------------- */
388 388
389 MODULE_DESCRIPTION("New Media PCMCIA ethernet driver"); 389 MODULE_DESCRIPTION("New Media PCMCIA ethernet driver");
390 MODULE_LICENSE("GPL"); 390 MODULE_LICENSE("GPL");
391 391
392 #define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0) 392 #define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
393 393
394 /* 0=auto, 1=10baseT, 2 = 10base2, default=auto */ 394 /* 0=auto, 1=10baseT, 2 = 10base2, default=auto */
395 INT_MODULE_PARM(if_port, 0); 395 INT_MODULE_PARM(if_port, 0);
396 396
397 397
398 /* ---------------------------------------------------------------------------- 398 /* ----------------------------------------------------------------------------
399 Function Prototypes 399 Function Prototypes
400 ---------------------------------------------------------------------------- */ 400 ---------------------------------------------------------------------------- */
401 401
402 static int nmclan_config(struct pcmcia_device *link); 402 static int nmclan_config(struct pcmcia_device *link);
403 static void nmclan_release(struct pcmcia_device *link); 403 static void nmclan_release(struct pcmcia_device *link);
404 404
405 static void nmclan_reset(struct net_device *dev); 405 static void nmclan_reset(struct net_device *dev);
406 static int mace_config(struct net_device *dev, struct ifmap *map); 406 static int mace_config(struct net_device *dev, struct ifmap *map);
407 static int mace_open(struct net_device *dev); 407 static int mace_open(struct net_device *dev);
408 static int mace_close(struct net_device *dev); 408 static int mace_close(struct net_device *dev);
409 static netdev_tx_t mace_start_xmit(struct sk_buff *skb, 409 static netdev_tx_t mace_start_xmit(struct sk_buff *skb,
410 struct net_device *dev); 410 struct net_device *dev);
411 static void mace_tx_timeout(struct net_device *dev); 411 static void mace_tx_timeout(struct net_device *dev);
412 static irqreturn_t mace_interrupt(int irq, void *dev_id); 412 static irqreturn_t mace_interrupt(int irq, void *dev_id);
413 static struct net_device_stats *mace_get_stats(struct net_device *dev); 413 static struct net_device_stats *mace_get_stats(struct net_device *dev);
414 static int mace_rx(struct net_device *dev, unsigned char RxCnt); 414 static int mace_rx(struct net_device *dev, unsigned char RxCnt);
415 static void restore_multicast_list(struct net_device *dev); 415 static void restore_multicast_list(struct net_device *dev);
416 static void set_multicast_list(struct net_device *dev); 416 static void set_multicast_list(struct net_device *dev);
417 static const struct ethtool_ops netdev_ethtool_ops; 417 static const struct ethtool_ops netdev_ethtool_ops;
418 418
419 419
420 static void nmclan_detach(struct pcmcia_device *p_dev); 420 static void nmclan_detach(struct pcmcia_device *p_dev);
421 421
422 static const struct net_device_ops mace_netdev_ops = { 422 static const struct net_device_ops mace_netdev_ops = {
423 .ndo_open = mace_open, 423 .ndo_open = mace_open,
424 .ndo_stop = mace_close, 424 .ndo_stop = mace_close,
425 .ndo_start_xmit = mace_start_xmit, 425 .ndo_start_xmit = mace_start_xmit,
426 .ndo_tx_timeout = mace_tx_timeout, 426 .ndo_tx_timeout = mace_tx_timeout,
427 .ndo_set_config = mace_config, 427 .ndo_set_config = mace_config,
428 .ndo_get_stats = mace_get_stats, 428 .ndo_get_stats = mace_get_stats,
429 .ndo_set_rx_mode = set_multicast_list, 429 .ndo_set_rx_mode = set_multicast_list,
430 .ndo_change_mtu = eth_change_mtu, 430 .ndo_change_mtu = eth_change_mtu,
431 .ndo_set_mac_address = eth_mac_addr, 431 .ndo_set_mac_address = eth_mac_addr,
432 .ndo_validate_addr = eth_validate_addr, 432 .ndo_validate_addr = eth_validate_addr,
433 }; 433 };
434 434
435 static int nmclan_probe(struct pcmcia_device *link) 435 static int nmclan_probe(struct pcmcia_device *link)
436 { 436 {
437 mace_private *lp; 437 mace_private *lp;
438 struct net_device *dev; 438 struct net_device *dev;
439 439
440 dev_dbg(&link->dev, "nmclan_attach()\n"); 440 dev_dbg(&link->dev, "nmclan_attach()\n");
441 441
442 /* Create new ethernet device */ 442 /* Create new ethernet device */
443 dev = alloc_etherdev(sizeof(mace_private)); 443 dev = alloc_etherdev(sizeof(mace_private));
444 if (!dev) 444 if (!dev)
445 return -ENOMEM; 445 return -ENOMEM;
446 lp = netdev_priv(dev); 446 lp = netdev_priv(dev);
447 lp->p_dev = link; 447 lp->p_dev = link;
448 link->priv = dev; 448 link->priv = dev;
449 449
450 spin_lock_init(&lp->bank_lock); 450 spin_lock_init(&lp->bank_lock);
451 link->resource[0]->end = 32; 451 link->resource[0]->end = 32;
452 link->resource[0]->flags |= IO_DATA_PATH_WIDTH_AUTO; 452 link->resource[0]->flags |= IO_DATA_PATH_WIDTH_AUTO;
453 link->config_flags |= CONF_ENABLE_IRQ; 453 link->config_flags |= CONF_ENABLE_IRQ;
454 link->config_index = 1; 454 link->config_index = 1;
455 link->config_regs = PRESENT_OPTION; 455 link->config_regs = PRESENT_OPTION;
456 456
457 lp->tx_free_frames=AM2150_MAX_TX_FRAMES; 457 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
458 458
459 dev->netdev_ops = &mace_netdev_ops; 459 dev->netdev_ops = &mace_netdev_ops;
460 dev->ethtool_ops = &netdev_ethtool_ops; 460 dev->ethtool_ops = &netdev_ethtool_ops;
461 dev->watchdog_timeo = TX_TIMEOUT; 461 dev->watchdog_timeo = TX_TIMEOUT;
462 462
463 return nmclan_config(link); 463 return nmclan_config(link);
464 } /* nmclan_attach */ 464 } /* nmclan_attach */
465 465
466 static void nmclan_detach(struct pcmcia_device *link) 466 static void nmclan_detach(struct pcmcia_device *link)
467 { 467 {
468 struct net_device *dev = link->priv; 468 struct net_device *dev = link->priv;
469 469
470 dev_dbg(&link->dev, "nmclan_detach\n"); 470 dev_dbg(&link->dev, "nmclan_detach\n");
471 471
472 unregister_netdev(dev); 472 unregister_netdev(dev);
473 473
474 nmclan_release(link); 474 nmclan_release(link);
475 475
476 free_netdev(dev); 476 free_netdev(dev);
477 } /* nmclan_detach */ 477 } /* nmclan_detach */
478 478
479 /* ---------------------------------------------------------------------------- 479 /* ----------------------------------------------------------------------------
480 mace_read 480 mace_read
481 Reads a MACE register. This is bank independent; however, the 481 Reads a MACE register. This is bank independent; however, the
482 caller must ensure that this call is not interruptable. We are 482 caller must ensure that this call is not interruptable. We are
483 assuming that during normal operation, the MACE is always in 483 assuming that during normal operation, the MACE is always in
484 bank 0. 484 bank 0.
485 ---------------------------------------------------------------------------- */ 485 ---------------------------------------------------------------------------- */
486 static int mace_read(mace_private *lp, unsigned int ioaddr, int reg) 486 static int mace_read(mace_private *lp, unsigned int ioaddr, int reg)
487 { 487 {
488 int data = 0xFF; 488 int data = 0xFF;
489 unsigned long flags; 489 unsigned long flags;
490 490
491 switch (reg >> 4) { 491 switch (reg >> 4) {
492 case 0: /* register 0-15 */ 492 case 0: /* register 0-15 */
493 data = inb(ioaddr + AM2150_MACE_BASE + reg); 493 data = inb(ioaddr + AM2150_MACE_BASE + reg);
494 break; 494 break;
495 case 1: /* register 16-31 */ 495 case 1: /* register 16-31 */
496 spin_lock_irqsave(&lp->bank_lock, flags); 496 spin_lock_irqsave(&lp->bank_lock, flags);
497 MACEBANK(1); 497 MACEBANK(1);
498 data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F)); 498 data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
499 MACEBANK(0); 499 MACEBANK(0);
500 spin_unlock_irqrestore(&lp->bank_lock, flags); 500 spin_unlock_irqrestore(&lp->bank_lock, flags);
501 break; 501 break;
502 } 502 }
503 return data & 0xFF; 503 return data & 0xFF;
504 } /* mace_read */ 504 } /* mace_read */
505 505
506 /* ---------------------------------------------------------------------------- 506 /* ----------------------------------------------------------------------------
507 mace_write 507 mace_write
508 Writes to a MACE register. This is bank independent; however, 508 Writes to a MACE register. This is bank independent; however,
509 the caller must ensure that this call is not interruptable. We 509 the caller must ensure that this call is not interruptable. We
510 are assuming that during normal operation, the MACE is always in 510 are assuming that during normal operation, the MACE is always in
511 bank 0. 511 bank 0.
512 ---------------------------------------------------------------------------- */ 512 ---------------------------------------------------------------------------- */
513 static void mace_write(mace_private *lp, unsigned int ioaddr, int reg, 513 static void mace_write(mace_private *lp, unsigned int ioaddr, int reg,
514 int data) 514 int data)
515 { 515 {
516 unsigned long flags; 516 unsigned long flags;
517 517
518 switch (reg >> 4) { 518 switch (reg >> 4) {
519 case 0: /* register 0-15 */ 519 case 0: /* register 0-15 */
520 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg); 520 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg);
521 break; 521 break;
522 case 1: /* register 16-31 */ 522 case 1: /* register 16-31 */
523 spin_lock_irqsave(&lp->bank_lock, flags); 523 spin_lock_irqsave(&lp->bank_lock, flags);
524 MACEBANK(1); 524 MACEBANK(1);
525 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F)); 525 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
526 MACEBANK(0); 526 MACEBANK(0);
527 spin_unlock_irqrestore(&lp->bank_lock, flags); 527 spin_unlock_irqrestore(&lp->bank_lock, flags);
528 break; 528 break;
529 } 529 }
530 } /* mace_write */ 530 } /* mace_write */
531 531
532 /* ---------------------------------------------------------------------------- 532 /* ----------------------------------------------------------------------------
533 mace_init 533 mace_init
534 Resets the MACE chip. 534 Resets the MACE chip.
535 ---------------------------------------------------------------------------- */ 535 ---------------------------------------------------------------------------- */
536 static int mace_init(mace_private *lp, unsigned int ioaddr, char *enet_addr) 536 static int mace_init(mace_private *lp, unsigned int ioaddr, char *enet_addr)
537 { 537 {
538 int i; 538 int i;
539 int ct = 0; 539 int ct = 0;
540 540
541 /* MACE Software reset */ 541 /* MACE Software reset */
542 mace_write(lp, ioaddr, MACE_BIUCC, 1); 542 mace_write(lp, ioaddr, MACE_BIUCC, 1);
543 while (mace_read(lp, ioaddr, MACE_BIUCC) & 0x01) { 543 while (mace_read(lp, ioaddr, MACE_BIUCC) & 0x01) {
544 /* Wait for reset bit to be cleared automatically after <= 200ns */; 544 /* Wait for reset bit to be cleared automatically after <= 200ns */;
545 if(++ct > 500) 545 if(++ct > 500)
546 { 546 {
547 pr_err("reset failed, card removed?\n"); 547 pr_err("reset failed, card removed?\n");
548 return -1; 548 return -1;
549 } 549 }
550 udelay(1); 550 udelay(1);
551 } 551 }
552 mace_write(lp, ioaddr, MACE_BIUCC, 0); 552 mace_write(lp, ioaddr, MACE_BIUCC, 0);
553 553
554 /* The Am2150 requires that the MACE FIFOs operate in burst mode. */ 554 /* The Am2150 requires that the MACE FIFOs operate in burst mode. */
555 mace_write(lp, ioaddr, MACE_FIFOCC, 0x0F); 555 mace_write(lp, ioaddr, MACE_FIFOCC, 0x0F);
556 556
557 mace_write(lp,ioaddr, MACE_RCVFC, 0); /* Disable Auto Strip Receive */ 557 mace_write(lp,ioaddr, MACE_RCVFC, 0); /* Disable Auto Strip Receive */
558 mace_write(lp, ioaddr, MACE_IMR, 0xFF); /* Disable all interrupts until _open */ 558 mace_write(lp, ioaddr, MACE_IMR, 0xFF); /* Disable all interrupts until _open */
559 559
560 /* 560 /*
561 * Bit 2-1 PORTSEL[1-0] Port Select. 561 * Bit 2-1 PORTSEL[1-0] Port Select.
562 * 00 AUI/10Base-2 562 * 00 AUI/10Base-2
563 * 01 10Base-T 563 * 01 10Base-T
564 * 10 DAI Port (reserved in Am2150) 564 * 10 DAI Port (reserved in Am2150)
565 * 11 GPSI 565 * 11 GPSI
566 * For this card, only the first two are valid. 566 * For this card, only the first two are valid.
567 * So, PLSCC should be set to 567 * So, PLSCC should be set to
568 * 0x00 for 10Base-2 568 * 0x00 for 10Base-2
569 * 0x02 for 10Base-T 569 * 0x02 for 10Base-T
570 * Or just set ASEL in PHYCC below! 570 * Or just set ASEL in PHYCC below!
571 */ 571 */
572 switch (if_port) { 572 switch (if_port) {
573 case 1: 573 case 1:
574 mace_write(lp, ioaddr, MACE_PLSCC, 0x02); 574 mace_write(lp, ioaddr, MACE_PLSCC, 0x02);
575 break; 575 break;
576 case 2: 576 case 2:
577 mace_write(lp, ioaddr, MACE_PLSCC, 0x00); 577 mace_write(lp, ioaddr, MACE_PLSCC, 0x00);
578 break; 578 break;
579 default: 579 default:
580 mace_write(lp, ioaddr, MACE_PHYCC, /* ASEL */ 4); 580 mace_write(lp, ioaddr, MACE_PHYCC, /* ASEL */ 4);
581 /* ASEL Auto Select. When set, the PORTSEL[1-0] bits are overridden, 581 /* ASEL Auto Select. When set, the PORTSEL[1-0] bits are overridden,
582 and the MACE device will automatically select the operating media 582 and the MACE device will automatically select the operating media
583 interface port. */ 583 interface port. */
584 break; 584 break;
585 } 585 }
586 586
587 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR); 587 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR);
588 /* Poll ADDRCHG bit */ 588 /* Poll ADDRCHG bit */
589 ct = 0; 589 ct = 0;
590 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG) 590 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
591 { 591 {
592 if(++ ct > 500) 592 if(++ ct > 500)
593 { 593 {
594 pr_err("ADDRCHG timeout, card removed?\n"); 594 pr_err("ADDRCHG timeout, card removed?\n");
595 return -1; 595 return -1;
596 } 596 }
597 } 597 }
598 /* Set PADR register */ 598 /* Set PADR register */
599 for (i = 0; i < ETH_ALEN; i++) 599 for (i = 0; i < ETH_ALEN; i++)
600 mace_write(lp, ioaddr, MACE_PADR, enet_addr[i]); 600 mace_write(lp, ioaddr, MACE_PADR, enet_addr[i]);
601 601
602 /* MAC Configuration Control Register should be written last */ 602 /* MAC Configuration Control Register should be written last */
603 /* Let set_multicast_list set this. */ 603 /* Let set_multicast_list set this. */
604 /* mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); */ 604 /* mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); */
605 mace_write(lp, ioaddr, MACE_MACCC, 0x00); 605 mace_write(lp, ioaddr, MACE_MACCC, 0x00);
606 return 0; 606 return 0;
607 } /* mace_init */ 607 } /* mace_init */
608 608
609 static int nmclan_config(struct pcmcia_device *link) 609 static int nmclan_config(struct pcmcia_device *link)
610 { 610 {
611 struct net_device *dev = link->priv; 611 struct net_device *dev = link->priv;
612 mace_private *lp = netdev_priv(dev); 612 mace_private *lp = netdev_priv(dev);
613 u8 *buf; 613 u8 *buf;
614 size_t len; 614 size_t len;
615 int i, ret; 615 int i, ret;
616 unsigned int ioaddr; 616 unsigned int ioaddr;
617 617
618 dev_dbg(&link->dev, "nmclan_config\n"); 618 dev_dbg(&link->dev, "nmclan_config\n");
619 619
620 link->io_lines = 5; 620 link->io_lines = 5;
621 ret = pcmcia_request_io(link); 621 ret = pcmcia_request_io(link);
622 if (ret) 622 if (ret)
623 goto failed; 623 goto failed;
624 ret = pcmcia_request_irq(link, mace_interrupt); 624 ret = pcmcia_request_irq(link, mace_interrupt);
625 if (ret) 625 if (ret)
626 goto failed; 626 goto failed;
627 ret = pcmcia_enable_device(link); 627 ret = pcmcia_enable_device(link);
628 if (ret) 628 if (ret)
629 goto failed; 629 goto failed;
630 630
631 dev->irq = link->irq; 631 dev->irq = link->irq;
632 dev->base_addr = link->resource[0]->start; 632 dev->base_addr = link->resource[0]->start;
633 633
634 ioaddr = dev->base_addr; 634 ioaddr = dev->base_addr;
635 635
636 /* Read the ethernet address from the CIS. */ 636 /* Read the ethernet address from the CIS. */
637 len = pcmcia_get_tuple(link, 0x80, &buf); 637 len = pcmcia_get_tuple(link, 0x80, &buf);
638 if (!buf || len < ETH_ALEN) { 638 if (!buf || len < ETH_ALEN) {
639 kfree(buf); 639 kfree(buf);
640 goto failed; 640 goto failed;
641 } 641 }
642 memcpy(dev->dev_addr, buf, ETH_ALEN); 642 memcpy(dev->dev_addr, buf, ETH_ALEN);
643 kfree(buf); 643 kfree(buf);
644 644
645 /* Verify configuration by reading the MACE ID. */ 645 /* Verify configuration by reading the MACE ID. */
646 { 646 {
647 char sig[2]; 647 char sig[2];
648 648
649 sig[0] = mace_read(lp, ioaddr, MACE_CHIPIDL); 649 sig[0] = mace_read(lp, ioaddr, MACE_CHIPIDL);
650 sig[1] = mace_read(lp, ioaddr, MACE_CHIPIDH); 650 sig[1] = mace_read(lp, ioaddr, MACE_CHIPIDH);
651 if ((sig[0] == 0x40) && ((sig[1] & 0x0F) == 0x09)) { 651 if ((sig[0] == 0x40) && ((sig[1] & 0x0F) == 0x09)) {
652 dev_dbg(&link->dev, "nmclan_cs configured: mace id=%x %x\n", 652 dev_dbg(&link->dev, "nmclan_cs configured: mace id=%x %x\n",
653 sig[0], sig[1]); 653 sig[0], sig[1]);
654 } else { 654 } else {
655 pr_notice("mace id not found: %x %x should be 0x40 0x?9\n", 655 pr_notice("mace id not found: %x %x should be 0x40 0x?9\n",
656 sig[0], sig[1]); 656 sig[0], sig[1]);
657 return -ENODEV; 657 return -ENODEV;
658 } 658 }
659 } 659 }
660 660
661 if(mace_init(lp, ioaddr, dev->dev_addr) == -1) 661 if(mace_init(lp, ioaddr, dev->dev_addr) == -1)
662 goto failed; 662 goto failed;
663 663
664 /* The if_port symbol can be set when the module is loaded */ 664 /* The if_port symbol can be set when the module is loaded */
665 if (if_port <= 2) 665 if (if_port <= 2)
666 dev->if_port = if_port; 666 dev->if_port = if_port;
667 else 667 else
668 pr_notice("invalid if_port requested\n"); 668 pr_notice("invalid if_port requested\n");
669 669
670 SET_NETDEV_DEV(dev, &link->dev); 670 SET_NETDEV_DEV(dev, &link->dev);
671 671
672 i = register_netdev(dev); 672 i = register_netdev(dev);
673 if (i != 0) { 673 if (i != 0) {
674 pr_notice("register_netdev() failed\n"); 674 pr_notice("register_netdev() failed\n");
675 goto failed; 675 goto failed;
676 } 676 }
677 677
678 netdev_info(dev, "nmclan: port %#3lx, irq %d, %s port, hw_addr %pM\n", 678 netdev_info(dev, "nmclan: port %#3lx, irq %d, %s port, hw_addr %pM\n",
679 dev->base_addr, dev->irq, if_names[dev->if_port], dev->dev_addr); 679 dev->base_addr, dev->irq, if_names[dev->if_port], dev->dev_addr);
680 return 0; 680 return 0;
681 681
682 failed: 682 failed:
683 nmclan_release(link); 683 nmclan_release(link);
684 return -ENODEV; 684 return -ENODEV;
685 } /* nmclan_config */ 685 } /* nmclan_config */
686 686
687 static void nmclan_release(struct pcmcia_device *link) 687 static void nmclan_release(struct pcmcia_device *link)
688 { 688 {
689 dev_dbg(&link->dev, "nmclan_release\n"); 689 dev_dbg(&link->dev, "nmclan_release\n");
690 pcmcia_disable_device(link); 690 pcmcia_disable_device(link);
691 } 691 }
692 692
693 static int nmclan_suspend(struct pcmcia_device *link) 693 static int nmclan_suspend(struct pcmcia_device *link)
694 { 694 {
695 struct net_device *dev = link->priv; 695 struct net_device *dev = link->priv;
696 696
697 if (link->open) 697 if (link->open)
698 netif_device_detach(dev); 698 netif_device_detach(dev);
699 699
700 return 0; 700 return 0;
701 } 701 }
702 702
703 static int nmclan_resume(struct pcmcia_device *link) 703 static int nmclan_resume(struct pcmcia_device *link)
704 { 704 {
705 struct net_device *dev = link->priv; 705 struct net_device *dev = link->priv;
706 706
707 if (link->open) { 707 if (link->open) {
708 nmclan_reset(dev); 708 nmclan_reset(dev);
709 netif_device_attach(dev); 709 netif_device_attach(dev);
710 } 710 }
711 711
712 return 0; 712 return 0;
713 } 713 }
714 714
715 715
716 /* ---------------------------------------------------------------------------- 716 /* ----------------------------------------------------------------------------
717 nmclan_reset 717 nmclan_reset
718 Reset and restore all of the Xilinx and MACE registers. 718 Reset and restore all of the Xilinx and MACE registers.
719 ---------------------------------------------------------------------------- */ 719 ---------------------------------------------------------------------------- */
720 static void nmclan_reset(struct net_device *dev) 720 static void nmclan_reset(struct net_device *dev)
721 { 721 {
722 mace_private *lp = netdev_priv(dev); 722 mace_private *lp = netdev_priv(dev);
723 723
724 #if RESET_XILINX 724 #if RESET_XILINX
725 struct pcmcia_device *link = &lp->link; 725 struct pcmcia_device *link = &lp->link;
726 u8 OrigCorValue; 726 u8 OrigCorValue;
727 727
728 /* Save original COR value */ 728 /* Save original COR value */
729 pcmcia_read_config_byte(link, CISREG_COR, &OrigCorValue); 729 pcmcia_read_config_byte(link, CISREG_COR, &OrigCorValue);
730 730
731 /* Reset Xilinx */ 731 /* Reset Xilinx */
732 dev_dbg(&link->dev, "nmclan_reset: OrigCorValue=0x%x, resetting...\n", 732 dev_dbg(&link->dev, "nmclan_reset: OrigCorValue=0x%x, resetting...\n",
733 OrigCorValue); 733 OrigCorValue);
734 pcmcia_write_config_byte(link, CISREG_COR, COR_SOFT_RESET); 734 pcmcia_write_config_byte(link, CISREG_COR, COR_SOFT_RESET);
735 /* Need to wait for 20 ms for PCMCIA to finish reset. */ 735 /* Need to wait for 20 ms for PCMCIA to finish reset. */
736 736
737 /* Restore original COR configuration index */ 737 /* Restore original COR configuration index */
738 pcmcia_write_config_byte(link, CISREG_COR, 738 pcmcia_write_config_byte(link, CISREG_COR,
739 (COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK))); 739 (COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK)));
740 /* Xilinx is now completely reset along with the MACE chip. */ 740 /* Xilinx is now completely reset along with the MACE chip. */
741 lp->tx_free_frames=AM2150_MAX_TX_FRAMES; 741 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
742 742
743 #endif /* #if RESET_XILINX */ 743 #endif /* #if RESET_XILINX */
744 744
745 /* Xilinx is now completely reset along with the MACE chip. */ 745 /* Xilinx is now completely reset along with the MACE chip. */
746 lp->tx_free_frames=AM2150_MAX_TX_FRAMES; 746 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
747 747
748 /* Reinitialize the MACE chip for operation. */ 748 /* Reinitialize the MACE chip for operation. */
749 mace_init(lp, dev->base_addr, dev->dev_addr); 749 mace_init(lp, dev->base_addr, dev->dev_addr);
750 mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT); 750 mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT);
751 751
752 /* Restore the multicast list and enable TX and RX. */ 752 /* Restore the multicast list and enable TX and RX. */
753 restore_multicast_list(dev); 753 restore_multicast_list(dev);
754 } /* nmclan_reset */ 754 } /* nmclan_reset */
755 755
756 /* ---------------------------------------------------------------------------- 756 /* ----------------------------------------------------------------------------
757 mace_config 757 mace_config
758 [Someone tell me what this is supposed to do? Is if_port a defined 758 [Someone tell me what this is supposed to do? Is if_port a defined
759 standard? If so, there should be defines to indicate 1=10Base-T, 759 standard? If so, there should be defines to indicate 1=10Base-T,
760 2=10Base-2, etc. including limited automatic detection.] 760 2=10Base-2, etc. including limited automatic detection.]
761 ---------------------------------------------------------------------------- */ 761 ---------------------------------------------------------------------------- */
762 static int mace_config(struct net_device *dev, struct ifmap *map) 762 static int mace_config(struct net_device *dev, struct ifmap *map)
763 { 763 {
764 if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) { 764 if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) {
765 if (map->port <= 2) { 765 if (map->port <= 2) {
766 dev->if_port = map->port; 766 dev->if_port = map->port;
767 netdev_info(dev, "switched to %s port\n", if_names[dev->if_port]); 767 netdev_info(dev, "switched to %s port\n", if_names[dev->if_port]);
768 } else 768 } else
769 return -EINVAL; 769 return -EINVAL;
770 } 770 }
771 return 0; 771 return 0;
772 } /* mace_config */ 772 } /* mace_config */
773 773
774 /* ---------------------------------------------------------------------------- 774 /* ----------------------------------------------------------------------------
775 mace_open 775 mace_open
776 Open device driver. 776 Open device driver.
777 ---------------------------------------------------------------------------- */ 777 ---------------------------------------------------------------------------- */
778 static int mace_open(struct net_device *dev) 778 static int mace_open(struct net_device *dev)
779 { 779 {
780 unsigned int ioaddr = dev->base_addr; 780 unsigned int ioaddr = dev->base_addr;
781 mace_private *lp = netdev_priv(dev); 781 mace_private *lp = netdev_priv(dev);
782 struct pcmcia_device *link = lp->p_dev; 782 struct pcmcia_device *link = lp->p_dev;
783 783
784 if (!pcmcia_dev_present(link)) 784 if (!pcmcia_dev_present(link))
785 return -ENODEV; 785 return -ENODEV;
786 786
787 link->open++; 787 link->open++;
788 788
789 MACEBANK(0); 789 MACEBANK(0);
790 790
791 netif_start_queue(dev); 791 netif_start_queue(dev);
792 nmclan_reset(dev); 792 nmclan_reset(dev);
793 793
794 return 0; /* Always succeed */ 794 return 0; /* Always succeed */
795 } /* mace_open */ 795 } /* mace_open */
796 796
797 /* ---------------------------------------------------------------------------- 797 /* ----------------------------------------------------------------------------
798 mace_close 798 mace_close
799 Closes device driver. 799 Closes device driver.
800 ---------------------------------------------------------------------------- */ 800 ---------------------------------------------------------------------------- */
801 static int mace_close(struct net_device *dev) 801 static int mace_close(struct net_device *dev)
802 { 802 {
803 unsigned int ioaddr = dev->base_addr; 803 unsigned int ioaddr = dev->base_addr;
804 mace_private *lp = netdev_priv(dev); 804 mace_private *lp = netdev_priv(dev);
805 struct pcmcia_device *link = lp->p_dev; 805 struct pcmcia_device *link = lp->p_dev;
806 806
807 dev_dbg(&link->dev, "%s: shutting down ethercard.\n", dev->name); 807 dev_dbg(&link->dev, "%s: shutting down ethercard.\n", dev->name);
808 808
809 /* Mask off all interrupts from the MACE chip. */ 809 /* Mask off all interrupts from the MACE chip. */
810 outb(0xFF, ioaddr + AM2150_MACE_BASE + MACE_IMR); 810 outb(0xFF, ioaddr + AM2150_MACE_BASE + MACE_IMR);
811 811
812 link->open--; 812 link->open--;
813 netif_stop_queue(dev); 813 netif_stop_queue(dev);
814 814
815 return 0; 815 return 0;
816 } /* mace_close */ 816 } /* mace_close */
817 817
818 static void netdev_get_drvinfo(struct net_device *dev, 818 static void netdev_get_drvinfo(struct net_device *dev,
819 struct ethtool_drvinfo *info) 819 struct ethtool_drvinfo *info)
820 { 820 {
821 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 821 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
822 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 822 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
823 snprintf(info->bus_info, sizeof(info->bus_info), 823 snprintf(info->bus_info, sizeof(info->bus_info),
824 "PCMCIA 0x%lx", dev->base_addr); 824 "PCMCIA 0x%lx", dev->base_addr);
825 } 825 }
826 826
827 static const struct ethtool_ops netdev_ethtool_ops = { 827 static const struct ethtool_ops netdev_ethtool_ops = {
828 .get_drvinfo = netdev_get_drvinfo, 828 .get_drvinfo = netdev_get_drvinfo,
829 }; 829 };
830 830
831 /* ---------------------------------------------------------------------------- 831 /* ----------------------------------------------------------------------------
832 mace_start_xmit 832 mace_start_xmit
833 This routine begins the packet transmit function. When completed, 833 This routine begins the packet transmit function. When completed,
834 it will generate a transmit interrupt. 834 it will generate a transmit interrupt.
835 835
836 According to /usr/src/linux/net/inet/dev.c, if _start_xmit 836 According to /usr/src/linux/net/inet/dev.c, if _start_xmit
837 returns 0, the "packet is now solely the responsibility of the 837 returns 0, the "packet is now solely the responsibility of the
838 driver." If _start_xmit returns non-zero, the "transmission 838 driver." If _start_xmit returns non-zero, the "transmission
839 failed, put skb back into a list." 839 failed, put skb back into a list."
840 ---------------------------------------------------------------------------- */ 840 ---------------------------------------------------------------------------- */
841 841
842 static void mace_tx_timeout(struct net_device *dev) 842 static void mace_tx_timeout(struct net_device *dev)
843 { 843 {
844 mace_private *lp = netdev_priv(dev); 844 mace_private *lp = netdev_priv(dev);
845 struct pcmcia_device *link = lp->p_dev; 845 struct pcmcia_device *link = lp->p_dev;
846 846
847 netdev_notice(dev, "transmit timed out -- "); 847 netdev_notice(dev, "transmit timed out -- ");
848 #if RESET_ON_TIMEOUT 848 #if RESET_ON_TIMEOUT
849 pr_cont("resetting card\n"); 849 pr_cont("resetting card\n");
850 pcmcia_reset_card(link->socket); 850 pcmcia_reset_card(link->socket);
851 #else /* #if RESET_ON_TIMEOUT */ 851 #else /* #if RESET_ON_TIMEOUT */
852 pr_cont("NOT resetting card\n"); 852 pr_cont("NOT resetting card\n");
853 #endif /* #if RESET_ON_TIMEOUT */ 853 #endif /* #if RESET_ON_TIMEOUT */
854 dev->trans_start = jiffies; /* prevent tx timeout */ 854 dev->trans_start = jiffies; /* prevent tx timeout */
855 netif_wake_queue(dev); 855 netif_wake_queue(dev);
856 } 856 }
857 857
858 static netdev_tx_t mace_start_xmit(struct sk_buff *skb, 858 static netdev_tx_t mace_start_xmit(struct sk_buff *skb,
859 struct net_device *dev) 859 struct net_device *dev)
860 { 860 {
861 mace_private *lp = netdev_priv(dev); 861 mace_private *lp = netdev_priv(dev);
862 unsigned int ioaddr = dev->base_addr; 862 unsigned int ioaddr = dev->base_addr;
863 863
864 netif_stop_queue(dev); 864 netif_stop_queue(dev);
865 865
866 pr_debug("%s: mace_start_xmit(length = %ld) called.\n", 866 pr_debug("%s: mace_start_xmit(length = %ld) called.\n",
867 dev->name, (long)skb->len); 867 dev->name, (long)skb->len);
868 868
869 #if (!TX_INTERRUPTABLE) 869 #if (!TX_INTERRUPTABLE)
870 /* Disable MACE TX interrupts. */ 870 /* Disable MACE TX interrupts. */
871 outb(MACE_IMR_DEFAULT | MACE_IR_XMTINT, 871 outb(MACE_IMR_DEFAULT | MACE_IR_XMTINT,
872 ioaddr + AM2150_MACE_BASE + MACE_IMR); 872 ioaddr + AM2150_MACE_BASE + MACE_IMR);
873 lp->tx_irq_disabled=1; 873 lp->tx_irq_disabled=1;
874 #endif /* #if (!TX_INTERRUPTABLE) */ 874 #endif /* #if (!TX_INTERRUPTABLE) */
875 875
876 { 876 {
877 /* This block must not be interrupted by another transmit request! 877 /* This block must not be interrupted by another transmit request!
878 mace_tx_timeout will take care of timer-based retransmissions from 878 mace_tx_timeout will take care of timer-based retransmissions from
879 the upper layers. The interrupt handler is guaranteed never to 879 the upper layers. The interrupt handler is guaranteed never to
880 service a transmit interrupt while we are in here. 880 service a transmit interrupt while we are in here.
881 */ 881 */
882 882
883 lp->linux_stats.tx_bytes += skb->len; 883 lp->linux_stats.tx_bytes += skb->len;
884 lp->tx_free_frames--; 884 lp->tx_free_frames--;
885 885
886 /* WARNING: Write the _exact_ number of bytes written in the header! */ 886 /* WARNING: Write the _exact_ number of bytes written in the header! */
887 /* Put out the word header [must be an outw()] . . . */ 887 /* Put out the word header [must be an outw()] . . . */
888 outw(skb->len, ioaddr + AM2150_XMT); 888 outw(skb->len, ioaddr + AM2150_XMT);
889 /* . . . and the packet [may be any combination of outw() and outb()] */ 889 /* . . . and the packet [may be any combination of outw() and outb()] */
890 outsw(ioaddr + AM2150_XMT, skb->data, skb->len >> 1); 890 outsw(ioaddr + AM2150_XMT, skb->data, skb->len >> 1);
891 if (skb->len & 1) { 891 if (skb->len & 1) {
892 /* Odd byte transfer */ 892 /* Odd byte transfer */
893 outb(skb->data[skb->len-1], ioaddr + AM2150_XMT); 893 outb(skb->data[skb->len-1], ioaddr + AM2150_XMT);
894 } 894 }
895 895
896 #if MULTI_TX 896 #if MULTI_TX
897 if (lp->tx_free_frames > 0) 897 if (lp->tx_free_frames > 0)
898 netif_start_queue(dev); 898 netif_start_queue(dev);
899 #endif /* #if MULTI_TX */ 899 #endif /* #if MULTI_TX */
900 } 900 }
901 901
902 #if (!TX_INTERRUPTABLE) 902 #if (!TX_INTERRUPTABLE)
903 /* Re-enable MACE TX interrupts. */ 903 /* Re-enable MACE TX interrupts. */
904 lp->tx_irq_disabled=0; 904 lp->tx_irq_disabled=0;
905 outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR); 905 outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR);
906 #endif /* #if (!TX_INTERRUPTABLE) */ 906 #endif /* #if (!TX_INTERRUPTABLE) */
907 907
908 dev_kfree_skb(skb); 908 dev_kfree_skb(skb);
909 909
910 return NETDEV_TX_OK; 910 return NETDEV_TX_OK;
911 } /* mace_start_xmit */ 911 } /* mace_start_xmit */
912 912
913 /* ---------------------------------------------------------------------------- 913 /* ----------------------------------------------------------------------------
914 mace_interrupt 914 mace_interrupt
915 The interrupt handler. 915 The interrupt handler.
916 ---------------------------------------------------------------------------- */ 916 ---------------------------------------------------------------------------- */
917 static irqreturn_t mace_interrupt(int irq, void *dev_id) 917 static irqreturn_t mace_interrupt(int irq, void *dev_id)
918 { 918 {
919 struct net_device *dev = (struct net_device *) dev_id; 919 struct net_device *dev = (struct net_device *) dev_id;
920 mace_private *lp = netdev_priv(dev); 920 mace_private *lp = netdev_priv(dev);
921 unsigned int ioaddr; 921 unsigned int ioaddr;
922 int status; 922 int status;
923 int IntrCnt = MACE_MAX_IR_ITERATIONS; 923 int IntrCnt = MACE_MAX_IR_ITERATIONS;
924 924
925 if (dev == NULL) { 925 if (dev == NULL) {
926 pr_debug("mace_interrupt(): irq 0x%X for unknown device.\n", 926 pr_debug("mace_interrupt(): irq 0x%X for unknown device.\n",
927 irq); 927 irq);
928 return IRQ_NONE; 928 return IRQ_NONE;
929 } 929 }
930 930
931 ioaddr = dev->base_addr; 931 ioaddr = dev->base_addr;
932 932
933 if (lp->tx_irq_disabled) { 933 if (lp->tx_irq_disabled) {
934 const char *msg; 934 const char *msg;
935 if (lp->tx_irq_disabled) 935 if (lp->tx_irq_disabled)
936 msg = "Interrupt with tx_irq_disabled"; 936 msg = "Interrupt with tx_irq_disabled";
937 else 937 else
938 msg = "Re-entering the interrupt handler"; 938 msg = "Re-entering the interrupt handler";
939 netdev_notice(dev, "%s [isr=%02X, imr=%02X]\n", 939 netdev_notice(dev, "%s [isr=%02X, imr=%02X]\n",
940 msg, 940 msg,
941 inb(ioaddr + AM2150_MACE_BASE + MACE_IR), 941 inb(ioaddr + AM2150_MACE_BASE + MACE_IR),
942 inb(ioaddr + AM2150_MACE_BASE + MACE_IMR)); 942 inb(ioaddr + AM2150_MACE_BASE + MACE_IMR));
943 /* WARNING: MACE_IR has been read! */ 943 /* WARNING: MACE_IR has been read! */
944 return IRQ_NONE; 944 return IRQ_NONE;
945 } 945 }
946 946
947 if (!netif_device_present(dev)) { 947 if (!netif_device_present(dev)) {
948 netdev_dbg(dev, "interrupt from dead card\n"); 948 netdev_dbg(dev, "interrupt from dead card\n");
949 return IRQ_NONE; 949 return IRQ_NONE;
950 } 950 }
951 951
952 do { 952 do {
953 /* WARNING: MACE_IR is a READ/CLEAR port! */ 953 /* WARNING: MACE_IR is a READ/CLEAR port! */
954 status = inb(ioaddr + AM2150_MACE_BASE + MACE_IR); 954 status = inb(ioaddr + AM2150_MACE_BASE + MACE_IR);
955 if (!(status & ~MACE_IMR_DEFAULT) && IntrCnt == MACE_MAX_IR_ITERATIONS)
956 return IRQ_NONE;
955 957
956 pr_debug("mace_interrupt: irq 0x%X status 0x%X.\n", irq, status); 958 pr_debug("mace_interrupt: irq 0x%X status 0x%X.\n", irq, status);
957 959
958 if (status & MACE_IR_RCVINT) { 960 if (status & MACE_IR_RCVINT) {
959 mace_rx(dev, MACE_MAX_RX_ITERATIONS); 961 mace_rx(dev, MACE_MAX_RX_ITERATIONS);
960 } 962 }
961 963
962 if (status & MACE_IR_XMTINT) { 964 if (status & MACE_IR_XMTINT) {
963 unsigned char fifofc; 965 unsigned char fifofc;
964 unsigned char xmtrc; 966 unsigned char xmtrc;
965 unsigned char xmtfs; 967 unsigned char xmtfs;
966 968
967 fifofc = inb(ioaddr + AM2150_MACE_BASE + MACE_FIFOFC); 969 fifofc = inb(ioaddr + AM2150_MACE_BASE + MACE_FIFOFC);
968 if ((fifofc & MACE_FIFOFC_XMTFC)==0) { 970 if ((fifofc & MACE_FIFOFC_XMTFC)==0) {
969 lp->linux_stats.tx_errors++; 971 lp->linux_stats.tx_errors++;
970 outb(0xFF, ioaddr + AM2150_XMT_SKIP); 972 outb(0xFF, ioaddr + AM2150_XMT_SKIP);
971 } 973 }
972 974
973 /* Transmit Retry Count (XMTRC, reg 4) */ 975 /* Transmit Retry Count (XMTRC, reg 4) */
974 xmtrc = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTRC); 976 xmtrc = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTRC);
975 if (xmtrc & MACE_XMTRC_EXDEF) lp->mace_stats.exdef++; 977 if (xmtrc & MACE_XMTRC_EXDEF) lp->mace_stats.exdef++;
976 lp->mace_stats.xmtrc += (xmtrc & MACE_XMTRC_XMTRC); 978 lp->mace_stats.xmtrc += (xmtrc & MACE_XMTRC_XMTRC);
977 979
978 if ( 980 if (
979 (xmtfs = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) & 981 (xmtfs = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) &
980 MACE_XMTFS_XMTSV /* Transmit Status Valid */ 982 MACE_XMTFS_XMTSV /* Transmit Status Valid */
981 ) { 983 ) {
982 lp->mace_stats.xmtsv++; 984 lp->mace_stats.xmtsv++;
983 985
984 if (xmtfs & ~MACE_XMTFS_XMTSV) { 986 if (xmtfs & ~MACE_XMTFS_XMTSV) {
985 if (xmtfs & MACE_XMTFS_UFLO) { 987 if (xmtfs & MACE_XMTFS_UFLO) {
986 /* Underflow. Indicates that the Transmit FIFO emptied before 988 /* Underflow. Indicates that the Transmit FIFO emptied before
987 the end of frame was reached. */ 989 the end of frame was reached. */
988 lp->mace_stats.uflo++; 990 lp->mace_stats.uflo++;
989 } 991 }
990 if (xmtfs & MACE_XMTFS_LCOL) { 992 if (xmtfs & MACE_XMTFS_LCOL) {
991 /* Late Collision */ 993 /* Late Collision */
992 lp->mace_stats.lcol++; 994 lp->mace_stats.lcol++;
993 } 995 }
994 if (xmtfs & MACE_XMTFS_MORE) { 996 if (xmtfs & MACE_XMTFS_MORE) {
995 /* MORE than one retry was needed */ 997 /* MORE than one retry was needed */
996 lp->mace_stats.more++; 998 lp->mace_stats.more++;
997 } 999 }
998 if (xmtfs & MACE_XMTFS_ONE) { 1000 if (xmtfs & MACE_XMTFS_ONE) {
999 /* Exactly ONE retry occurred */ 1001 /* Exactly ONE retry occurred */
1000 lp->mace_stats.one++; 1002 lp->mace_stats.one++;
1001 } 1003 }
1002 if (xmtfs & MACE_XMTFS_DEFER) { 1004 if (xmtfs & MACE_XMTFS_DEFER) {
1003 /* Transmission was defered */ 1005 /* Transmission was defered */
1004 lp->mace_stats.defer++; 1006 lp->mace_stats.defer++;
1005 } 1007 }
1006 if (xmtfs & MACE_XMTFS_LCAR) { 1008 if (xmtfs & MACE_XMTFS_LCAR) {
1007 /* Loss of carrier */ 1009 /* Loss of carrier */
1008 lp->mace_stats.lcar++; 1010 lp->mace_stats.lcar++;
1009 } 1011 }
1010 if (xmtfs & MACE_XMTFS_RTRY) { 1012 if (xmtfs & MACE_XMTFS_RTRY) {
1011 /* Retry error: transmit aborted after 16 attempts */ 1013 /* Retry error: transmit aborted after 16 attempts */
1012 lp->mace_stats.rtry++; 1014 lp->mace_stats.rtry++;
1013 } 1015 }
1014 } /* if (xmtfs & ~MACE_XMTFS_XMTSV) */ 1016 } /* if (xmtfs & ~MACE_XMTFS_XMTSV) */
1015 1017
1016 } /* if (xmtfs & MACE_XMTFS_XMTSV) */ 1018 } /* if (xmtfs & MACE_XMTFS_XMTSV) */
1017 1019
1018 lp->linux_stats.tx_packets++; 1020 lp->linux_stats.tx_packets++;
1019 lp->tx_free_frames++; 1021 lp->tx_free_frames++;
1020 netif_wake_queue(dev); 1022 netif_wake_queue(dev);
1021 } /* if (status & MACE_IR_XMTINT) */ 1023 } /* if (status & MACE_IR_XMTINT) */
1022 1024
1023 if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) { 1025 if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) {
1024 if (status & MACE_IR_JAB) { 1026 if (status & MACE_IR_JAB) {
1025 /* Jabber Error. Excessive transmit duration (20-150ms). */ 1027 /* Jabber Error. Excessive transmit duration (20-150ms). */
1026 lp->mace_stats.jab++; 1028 lp->mace_stats.jab++;
1027 } 1029 }
1028 if (status & MACE_IR_BABL) { 1030 if (status & MACE_IR_BABL) {
1029 /* Babble Error. >1518 bytes transmitted. */ 1031 /* Babble Error. >1518 bytes transmitted. */
1030 lp->mace_stats.babl++; 1032 lp->mace_stats.babl++;
1031 } 1033 }
1032 if (status & MACE_IR_CERR) { 1034 if (status & MACE_IR_CERR) {
1033 /* Collision Error. CERR indicates the absence of the 1035 /* Collision Error. CERR indicates the absence of the
1034 Signal Quality Error Test message after a packet 1036 Signal Quality Error Test message after a packet
1035 transmission. */ 1037 transmission. */
1036 lp->mace_stats.cerr++; 1038 lp->mace_stats.cerr++;
1037 } 1039 }
1038 if (status & MACE_IR_RCVCCO) { 1040 if (status & MACE_IR_RCVCCO) {
1039 /* Receive Collision Count Overflow; */ 1041 /* Receive Collision Count Overflow; */
1040 lp->mace_stats.rcvcco++; 1042 lp->mace_stats.rcvcco++;
1041 } 1043 }
1042 if (status & MACE_IR_RNTPCO) { 1044 if (status & MACE_IR_RNTPCO) {
1043 /* Runt Packet Count Overflow */ 1045 /* Runt Packet Count Overflow */
1044 lp->mace_stats.rntpco++; 1046 lp->mace_stats.rntpco++;
1045 } 1047 }
1046 if (status & MACE_IR_MPCO) { 1048 if (status & MACE_IR_MPCO) {
1047 /* Missed Packet Count Overflow */ 1049 /* Missed Packet Count Overflow */
1048 lp->mace_stats.mpco++; 1050 lp->mace_stats.mpco++;
1049 } 1051 }
1050 } /* if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) */ 1052 } /* if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) */
1051 1053
1052 } while ((status & ~MACE_IMR_DEFAULT) && (--IntrCnt)); 1054 } while ((status & ~MACE_IMR_DEFAULT) && (--IntrCnt));
1053 1055
1054 return IRQ_HANDLED; 1056 return IRQ_HANDLED;
1055 } /* mace_interrupt */ 1057 } /* mace_interrupt */
1056 1058
1057 /* ---------------------------------------------------------------------------- 1059 /* ----------------------------------------------------------------------------
1058 mace_rx 1060 mace_rx
1059 Receives packets. 1061 Receives packets.
1060 ---------------------------------------------------------------------------- */ 1062 ---------------------------------------------------------------------------- */
1061 static int mace_rx(struct net_device *dev, unsigned char RxCnt) 1063 static int mace_rx(struct net_device *dev, unsigned char RxCnt)
1062 { 1064 {
1063 mace_private *lp = netdev_priv(dev); 1065 mace_private *lp = netdev_priv(dev);
1064 unsigned int ioaddr = dev->base_addr; 1066 unsigned int ioaddr = dev->base_addr;
1065 unsigned char rx_framecnt; 1067 unsigned char rx_framecnt;
1066 unsigned short rx_status; 1068 unsigned short rx_status;
1067 1069
1068 while ( 1070 while (
1069 ((rx_framecnt = inb(ioaddr + AM2150_RCV_FRAME_COUNT)) > 0) && 1071 ((rx_framecnt = inb(ioaddr + AM2150_RCV_FRAME_COUNT)) > 0) &&
1070 (rx_framecnt <= 12) && /* rx_framecnt==0xFF if card is extracted. */ 1072 (rx_framecnt <= 12) && /* rx_framecnt==0xFF if card is extracted. */
1071 (RxCnt--) 1073 (RxCnt--)
1072 ) { 1074 ) {
1073 rx_status = inw(ioaddr + AM2150_RCV); 1075 rx_status = inw(ioaddr + AM2150_RCV);
1074 1076
1075 pr_debug("%s: in mace_rx(), framecnt 0x%X, rx_status" 1077 pr_debug("%s: in mace_rx(), framecnt 0x%X, rx_status"
1076 " 0x%X.\n", dev->name, rx_framecnt, rx_status); 1078 " 0x%X.\n", dev->name, rx_framecnt, rx_status);
1077 1079
1078 if (rx_status & MACE_RCVFS_RCVSTS) { /* Error, update stats. */ 1080 if (rx_status & MACE_RCVFS_RCVSTS) { /* Error, update stats. */
1079 lp->linux_stats.rx_errors++; 1081 lp->linux_stats.rx_errors++;
1080 if (rx_status & MACE_RCVFS_OFLO) { 1082 if (rx_status & MACE_RCVFS_OFLO) {
1081 lp->mace_stats.oflo++; 1083 lp->mace_stats.oflo++;
1082 } 1084 }
1083 if (rx_status & MACE_RCVFS_CLSN) { 1085 if (rx_status & MACE_RCVFS_CLSN) {
1084 lp->mace_stats.clsn++; 1086 lp->mace_stats.clsn++;
1085 } 1087 }
1086 if (rx_status & MACE_RCVFS_FRAM) { 1088 if (rx_status & MACE_RCVFS_FRAM) {
1087 lp->mace_stats.fram++; 1089 lp->mace_stats.fram++;
1088 } 1090 }
1089 if (rx_status & MACE_RCVFS_FCS) { 1091 if (rx_status & MACE_RCVFS_FCS) {
1090 lp->mace_stats.fcs++; 1092 lp->mace_stats.fcs++;
1091 } 1093 }
1092 } else { 1094 } else {
1093 short pkt_len = (rx_status & ~MACE_RCVFS_RCVSTS) - 4; 1095 short pkt_len = (rx_status & ~MACE_RCVFS_RCVSTS) - 4;
1094 /* Auto Strip is off, always subtract 4 */ 1096 /* Auto Strip is off, always subtract 4 */
1095 struct sk_buff *skb; 1097 struct sk_buff *skb;
1096 1098
1097 lp->mace_stats.rfs_rntpc += inb(ioaddr + AM2150_RCV); 1099 lp->mace_stats.rfs_rntpc += inb(ioaddr + AM2150_RCV);
1098 /* runt packet count */ 1100 /* runt packet count */
1099 lp->mace_stats.rfs_rcvcc += inb(ioaddr + AM2150_RCV); 1101 lp->mace_stats.rfs_rcvcc += inb(ioaddr + AM2150_RCV);
1100 /* rcv collision count */ 1102 /* rcv collision count */
1101 1103
1102 pr_debug(" receiving packet size 0x%X rx_status" 1104 pr_debug(" receiving packet size 0x%X rx_status"
1103 " 0x%X.\n", pkt_len, rx_status); 1105 " 0x%X.\n", pkt_len, rx_status);
1104 1106
1105 skb = netdev_alloc_skb(dev, pkt_len + 2); 1107 skb = netdev_alloc_skb(dev, pkt_len + 2);
1106 1108
1107 if (skb != NULL) { 1109 if (skb != NULL) {
1108 skb_reserve(skb, 2); 1110 skb_reserve(skb, 2);
1109 insw(ioaddr + AM2150_RCV, skb_put(skb, pkt_len), pkt_len>>1); 1111 insw(ioaddr + AM2150_RCV, skb_put(skb, pkt_len), pkt_len>>1);
1110 if (pkt_len & 1) 1112 if (pkt_len & 1)
1111 *(skb_tail_pointer(skb) - 1) = inb(ioaddr + AM2150_RCV); 1113 *(skb_tail_pointer(skb) - 1) = inb(ioaddr + AM2150_RCV);
1112 skb->protocol = eth_type_trans(skb, dev); 1114 skb->protocol = eth_type_trans(skb, dev);
1113 1115
1114 netif_rx(skb); /* Send the packet to the upper (protocol) layers. */ 1116 netif_rx(skb); /* Send the packet to the upper (protocol) layers. */
1115 1117
1116 lp->linux_stats.rx_packets++; 1118 lp->linux_stats.rx_packets++;
1117 lp->linux_stats.rx_bytes += pkt_len; 1119 lp->linux_stats.rx_bytes += pkt_len;
1118 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */ 1120 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1119 continue; 1121 continue;
1120 } else { 1122 } else {
1121 pr_debug("%s: couldn't allocate a sk_buff of size" 1123 pr_debug("%s: couldn't allocate a sk_buff of size"
1122 " %d.\n", dev->name, pkt_len); 1124 " %d.\n", dev->name, pkt_len);
1123 lp->linux_stats.rx_dropped++; 1125 lp->linux_stats.rx_dropped++;
1124 } 1126 }
1125 } 1127 }
1126 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */ 1128 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1127 } /* while */ 1129 } /* while */
1128 1130
1129 return 0; 1131 return 0;
1130 } /* mace_rx */ 1132 } /* mace_rx */
1131 1133
1132 /* ---------------------------------------------------------------------------- 1134 /* ----------------------------------------------------------------------------
1133 pr_linux_stats 1135 pr_linux_stats
1134 ---------------------------------------------------------------------------- */ 1136 ---------------------------------------------------------------------------- */
1135 static void pr_linux_stats(struct net_device_stats *pstats) 1137 static void pr_linux_stats(struct net_device_stats *pstats)
1136 { 1138 {
1137 pr_debug("pr_linux_stats\n"); 1139 pr_debug("pr_linux_stats\n");
1138 pr_debug(" rx_packets=%-7ld tx_packets=%ld\n", 1140 pr_debug(" rx_packets=%-7ld tx_packets=%ld\n",
1139 (long)pstats->rx_packets, (long)pstats->tx_packets); 1141 (long)pstats->rx_packets, (long)pstats->tx_packets);
1140 pr_debug(" rx_errors=%-7ld tx_errors=%ld\n", 1142 pr_debug(" rx_errors=%-7ld tx_errors=%ld\n",
1141 (long)pstats->rx_errors, (long)pstats->tx_errors); 1143 (long)pstats->rx_errors, (long)pstats->tx_errors);
1142 pr_debug(" rx_dropped=%-7ld tx_dropped=%ld\n", 1144 pr_debug(" rx_dropped=%-7ld tx_dropped=%ld\n",
1143 (long)pstats->rx_dropped, (long)pstats->tx_dropped); 1145 (long)pstats->rx_dropped, (long)pstats->tx_dropped);
1144 pr_debug(" multicast=%-7ld collisions=%ld\n", 1146 pr_debug(" multicast=%-7ld collisions=%ld\n",
1145 (long)pstats->multicast, (long)pstats->collisions); 1147 (long)pstats->multicast, (long)pstats->collisions);
1146 1148
1147 pr_debug(" rx_length_errors=%-7ld rx_over_errors=%ld\n", 1149 pr_debug(" rx_length_errors=%-7ld rx_over_errors=%ld\n",
1148 (long)pstats->rx_length_errors, (long)pstats->rx_over_errors); 1150 (long)pstats->rx_length_errors, (long)pstats->rx_over_errors);
1149 pr_debug(" rx_crc_errors=%-7ld rx_frame_errors=%ld\n", 1151 pr_debug(" rx_crc_errors=%-7ld rx_frame_errors=%ld\n",
1150 (long)pstats->rx_crc_errors, (long)pstats->rx_frame_errors); 1152 (long)pstats->rx_crc_errors, (long)pstats->rx_frame_errors);
1151 pr_debug(" rx_fifo_errors=%-7ld rx_missed_errors=%ld\n", 1153 pr_debug(" rx_fifo_errors=%-7ld rx_missed_errors=%ld\n",
1152 (long)pstats->rx_fifo_errors, (long)pstats->rx_missed_errors); 1154 (long)pstats->rx_fifo_errors, (long)pstats->rx_missed_errors);
1153 1155
1154 pr_debug(" tx_aborted_errors=%-7ld tx_carrier_errors=%ld\n", 1156 pr_debug(" tx_aborted_errors=%-7ld tx_carrier_errors=%ld\n",
1155 (long)pstats->tx_aborted_errors, (long)pstats->tx_carrier_errors); 1157 (long)pstats->tx_aborted_errors, (long)pstats->tx_carrier_errors);
1156 pr_debug(" tx_fifo_errors=%-7ld tx_heartbeat_errors=%ld\n", 1158 pr_debug(" tx_fifo_errors=%-7ld tx_heartbeat_errors=%ld\n",
1157 (long)pstats->tx_fifo_errors, (long)pstats->tx_heartbeat_errors); 1159 (long)pstats->tx_fifo_errors, (long)pstats->tx_heartbeat_errors);
1158 pr_debug(" tx_window_errors=%ld\n", 1160 pr_debug(" tx_window_errors=%ld\n",
1159 (long)pstats->tx_window_errors); 1161 (long)pstats->tx_window_errors);
1160 } /* pr_linux_stats */ 1162 } /* pr_linux_stats */
1161 1163
1162 /* ---------------------------------------------------------------------------- 1164 /* ----------------------------------------------------------------------------
1163 pr_mace_stats 1165 pr_mace_stats
1164 ---------------------------------------------------------------------------- */ 1166 ---------------------------------------------------------------------------- */
1165 static void pr_mace_stats(mace_statistics *pstats) 1167 static void pr_mace_stats(mace_statistics *pstats)
1166 { 1168 {
1167 pr_debug("pr_mace_stats\n"); 1169 pr_debug("pr_mace_stats\n");
1168 1170
1169 pr_debug(" xmtsv=%-7d uflo=%d\n", 1171 pr_debug(" xmtsv=%-7d uflo=%d\n",
1170 pstats->xmtsv, pstats->uflo); 1172 pstats->xmtsv, pstats->uflo);
1171 pr_debug(" lcol=%-7d more=%d\n", 1173 pr_debug(" lcol=%-7d more=%d\n",
1172 pstats->lcol, pstats->more); 1174 pstats->lcol, pstats->more);
1173 pr_debug(" one=%-7d defer=%d\n", 1175 pr_debug(" one=%-7d defer=%d\n",
1174 pstats->one, pstats->defer); 1176 pstats->one, pstats->defer);
1175 pr_debug(" lcar=%-7d rtry=%d\n", 1177 pr_debug(" lcar=%-7d rtry=%d\n",
1176 pstats->lcar, pstats->rtry); 1178 pstats->lcar, pstats->rtry);
1177 1179
1178 /* MACE_XMTRC */ 1180 /* MACE_XMTRC */
1179 pr_debug(" exdef=%-7d xmtrc=%d\n", 1181 pr_debug(" exdef=%-7d xmtrc=%d\n",
1180 pstats->exdef, pstats->xmtrc); 1182 pstats->exdef, pstats->xmtrc);
1181 1183
1182 /* RFS1--Receive Status (RCVSTS) */ 1184 /* RFS1--Receive Status (RCVSTS) */
1183 pr_debug(" oflo=%-7d clsn=%d\n", 1185 pr_debug(" oflo=%-7d clsn=%d\n",
1184 pstats->oflo, pstats->clsn); 1186 pstats->oflo, pstats->clsn);
1185 pr_debug(" fram=%-7d fcs=%d\n", 1187 pr_debug(" fram=%-7d fcs=%d\n",
1186 pstats->fram, pstats->fcs); 1188 pstats->fram, pstats->fcs);
1187 1189
1188 /* RFS2--Runt Packet Count (RNTPC) */ 1190 /* RFS2--Runt Packet Count (RNTPC) */
1189 /* RFS3--Receive Collision Count (RCVCC) */ 1191 /* RFS3--Receive Collision Count (RCVCC) */
1190 pr_debug(" rfs_rntpc=%-7d rfs_rcvcc=%d\n", 1192 pr_debug(" rfs_rntpc=%-7d rfs_rcvcc=%d\n",
1191 pstats->rfs_rntpc, pstats->rfs_rcvcc); 1193 pstats->rfs_rntpc, pstats->rfs_rcvcc);
1192 1194
1193 /* MACE_IR */ 1195 /* MACE_IR */
1194 pr_debug(" jab=%-7d babl=%d\n", 1196 pr_debug(" jab=%-7d babl=%d\n",
1195 pstats->jab, pstats->babl); 1197 pstats->jab, pstats->babl);
1196 pr_debug(" cerr=%-7d rcvcco=%d\n", 1198 pr_debug(" cerr=%-7d rcvcco=%d\n",
1197 pstats->cerr, pstats->rcvcco); 1199 pstats->cerr, pstats->rcvcco);
1198 pr_debug(" rntpco=%-7d mpco=%d\n", 1200 pr_debug(" rntpco=%-7d mpco=%d\n",
1199 pstats->rntpco, pstats->mpco); 1201 pstats->rntpco, pstats->mpco);
1200 1202
1201 /* MACE_MPC */ 1203 /* MACE_MPC */
1202 pr_debug(" mpc=%d\n", pstats->mpc); 1204 pr_debug(" mpc=%d\n", pstats->mpc);
1203 1205
1204 /* MACE_RNTPC */ 1206 /* MACE_RNTPC */
1205 pr_debug(" rntpc=%d\n", pstats->rntpc); 1207 pr_debug(" rntpc=%d\n", pstats->rntpc);
1206 1208
1207 /* MACE_RCVCC */ 1209 /* MACE_RCVCC */
1208 pr_debug(" rcvcc=%d\n", pstats->rcvcc); 1210 pr_debug(" rcvcc=%d\n", pstats->rcvcc);
1209 1211
1210 } /* pr_mace_stats */ 1212 } /* pr_mace_stats */
1211 1213
1212 /* ---------------------------------------------------------------------------- 1214 /* ----------------------------------------------------------------------------
1213 update_stats 1215 update_stats
1214 Update statistics. We change to register window 1, so this 1216 Update statistics. We change to register window 1, so this
1215 should be run single-threaded if the device is active. This is 1217 should be run single-threaded if the device is active. This is
1216 expected to be a rare operation, and it's simpler for the rest 1218 expected to be a rare operation, and it's simpler for the rest
1217 of the driver to assume that window 0 is always valid rather 1219 of the driver to assume that window 0 is always valid rather
1218 than use a special window-state variable. 1220 than use a special window-state variable.
1219 1221
1220 oflo & uflo should _never_ occur since it would mean the Xilinx 1222 oflo & uflo should _never_ occur since it would mean the Xilinx
1221 was not able to transfer data between the MACE FIFO and the 1223 was not able to transfer data between the MACE FIFO and the
1222 card's SRAM fast enough. If this happens, something is 1224 card's SRAM fast enough. If this happens, something is
1223 seriously wrong with the hardware. 1225 seriously wrong with the hardware.
1224 ---------------------------------------------------------------------------- */ 1226 ---------------------------------------------------------------------------- */
1225 static void update_stats(unsigned int ioaddr, struct net_device *dev) 1227 static void update_stats(unsigned int ioaddr, struct net_device *dev)
1226 { 1228 {
1227 mace_private *lp = netdev_priv(dev); 1229 mace_private *lp = netdev_priv(dev);
1228 1230
1229 lp->mace_stats.rcvcc += mace_read(lp, ioaddr, MACE_RCVCC); 1231 lp->mace_stats.rcvcc += mace_read(lp, ioaddr, MACE_RCVCC);
1230 lp->mace_stats.rntpc += mace_read(lp, ioaddr, MACE_RNTPC); 1232 lp->mace_stats.rntpc += mace_read(lp, ioaddr, MACE_RNTPC);
1231 lp->mace_stats.mpc += mace_read(lp, ioaddr, MACE_MPC); 1233 lp->mace_stats.mpc += mace_read(lp, ioaddr, MACE_MPC);
1232 /* At this point, mace_stats is fully updated for this call. 1234 /* At this point, mace_stats is fully updated for this call.
1233 We may now update the linux_stats. */ 1235 We may now update the linux_stats. */
1234 1236
1235 /* The MACE has no equivalent for linux_stats field which are commented 1237 /* The MACE has no equivalent for linux_stats field which are commented
1236 out. */ 1238 out. */
1237 1239
1238 /* lp->linux_stats.multicast; */ 1240 /* lp->linux_stats.multicast; */
1239 lp->linux_stats.collisions = 1241 lp->linux_stats.collisions =
1240 lp->mace_stats.rcvcco * 256 + lp->mace_stats.rcvcc; 1242 lp->mace_stats.rcvcco * 256 + lp->mace_stats.rcvcc;
1241 /* Collision: The MACE may retry sending a packet 15 times 1243 /* Collision: The MACE may retry sending a packet 15 times
1242 before giving up. The retry count is in XMTRC. 1244 before giving up. The retry count is in XMTRC.
1243 Does each retry constitute a collision? 1245 Does each retry constitute a collision?
1244 If so, why doesn't the RCVCC record these collisions? */ 1246 If so, why doesn't the RCVCC record these collisions? */
1245 1247
1246 /* detailed rx_errors: */ 1248 /* detailed rx_errors: */
1247 lp->linux_stats.rx_length_errors = 1249 lp->linux_stats.rx_length_errors =
1248 lp->mace_stats.rntpco * 256 + lp->mace_stats.rntpc; 1250 lp->mace_stats.rntpco * 256 + lp->mace_stats.rntpc;
1249 /* lp->linux_stats.rx_over_errors */ 1251 /* lp->linux_stats.rx_over_errors */
1250 lp->linux_stats.rx_crc_errors = lp->mace_stats.fcs; 1252 lp->linux_stats.rx_crc_errors = lp->mace_stats.fcs;
1251 lp->linux_stats.rx_frame_errors = lp->mace_stats.fram; 1253 lp->linux_stats.rx_frame_errors = lp->mace_stats.fram;
1252 lp->linux_stats.rx_fifo_errors = lp->mace_stats.oflo; 1254 lp->linux_stats.rx_fifo_errors = lp->mace_stats.oflo;
1253 lp->linux_stats.rx_missed_errors = 1255 lp->linux_stats.rx_missed_errors =
1254 lp->mace_stats.mpco * 256 + lp->mace_stats.mpc; 1256 lp->mace_stats.mpco * 256 + lp->mace_stats.mpc;
1255 1257
1256 /* detailed tx_errors */ 1258 /* detailed tx_errors */
1257 lp->linux_stats.tx_aborted_errors = lp->mace_stats.rtry; 1259 lp->linux_stats.tx_aborted_errors = lp->mace_stats.rtry;
1258 lp->linux_stats.tx_carrier_errors = lp->mace_stats.lcar; 1260 lp->linux_stats.tx_carrier_errors = lp->mace_stats.lcar;
1259 /* LCAR usually results from bad cabling. */ 1261 /* LCAR usually results from bad cabling. */
1260 lp->linux_stats.tx_fifo_errors = lp->mace_stats.uflo; 1262 lp->linux_stats.tx_fifo_errors = lp->mace_stats.uflo;
1261 lp->linux_stats.tx_heartbeat_errors = lp->mace_stats.cerr; 1263 lp->linux_stats.tx_heartbeat_errors = lp->mace_stats.cerr;
1262 /* lp->linux_stats.tx_window_errors; */ 1264 /* lp->linux_stats.tx_window_errors; */
1263 } /* update_stats */ 1265 } /* update_stats */
1264 1266
1265 /* ---------------------------------------------------------------------------- 1267 /* ----------------------------------------------------------------------------
1266 mace_get_stats 1268 mace_get_stats
1267 Gathers ethernet statistics from the MACE chip. 1269 Gathers ethernet statistics from the MACE chip.
1268 ---------------------------------------------------------------------------- */ 1270 ---------------------------------------------------------------------------- */
1269 static struct net_device_stats *mace_get_stats(struct net_device *dev) 1271 static struct net_device_stats *mace_get_stats(struct net_device *dev)
1270 { 1272 {
1271 mace_private *lp = netdev_priv(dev); 1273 mace_private *lp = netdev_priv(dev);
1272 1274
1273 update_stats(dev->base_addr, dev); 1275 update_stats(dev->base_addr, dev);
1274 1276
1275 pr_debug("%s: updating the statistics.\n", dev->name); 1277 pr_debug("%s: updating the statistics.\n", dev->name);
1276 pr_linux_stats(&lp->linux_stats); 1278 pr_linux_stats(&lp->linux_stats);
1277 pr_mace_stats(&lp->mace_stats); 1279 pr_mace_stats(&lp->mace_stats);
1278 1280
1279 return &lp->linux_stats; 1281 return &lp->linux_stats;
1280 } /* net_device_stats */ 1282 } /* net_device_stats */
1281 1283
1282 /* ---------------------------------------------------------------------------- 1284 /* ----------------------------------------------------------------------------
1283 updateCRC 1285 updateCRC
1284 Modified from Am79C90 data sheet. 1286 Modified from Am79C90 data sheet.
1285 ---------------------------------------------------------------------------- */ 1287 ---------------------------------------------------------------------------- */
1286 1288
1287 #ifdef BROKEN_MULTICAST 1289 #ifdef BROKEN_MULTICAST
1288 1290
1289 static void updateCRC(int *CRC, int bit) 1291 static void updateCRC(int *CRC, int bit)
1290 { 1292 {
1291 static const int poly[]={ 1293 static const int poly[]={
1292 1,1,1,0, 1,1,0,1, 1294 1,1,1,0, 1,1,0,1,
1293 1,0,1,1, 1,0,0,0, 1295 1,0,1,1, 1,0,0,0,
1294 1,0,0,0, 0,0,1,1, 1296 1,0,0,0, 0,0,1,1,
1295 0,0,1,0, 0,0,0,0 1297 0,0,1,0, 0,0,0,0
1296 }; /* CRC polynomial. poly[n] = coefficient of the x**n term of the 1298 }; /* CRC polynomial. poly[n] = coefficient of the x**n term of the
1297 CRC generator polynomial. */ 1299 CRC generator polynomial. */
1298 1300
1299 int j; 1301 int j;
1300 1302
1301 /* shift CRC and control bit (CRC[32]) */ 1303 /* shift CRC and control bit (CRC[32]) */
1302 for (j = 32; j > 0; j--) 1304 for (j = 32; j > 0; j--)
1303 CRC[j] = CRC[j-1]; 1305 CRC[j] = CRC[j-1];
1304 CRC[0] = 0; 1306 CRC[0] = 0;
1305 1307
1306 /* If bit XOR(control bit) = 1, set CRC = CRC XOR polynomial. */ 1308 /* If bit XOR(control bit) = 1, set CRC = CRC XOR polynomial. */
1307 if (bit ^ CRC[32]) 1309 if (bit ^ CRC[32])
1308 for (j = 0; j < 32; j++) 1310 for (j = 0; j < 32; j++)
1309 CRC[j] ^= poly[j]; 1311 CRC[j] ^= poly[j];
1310 } /* updateCRC */ 1312 } /* updateCRC */
1311 1313
1312 /* ---------------------------------------------------------------------------- 1314 /* ----------------------------------------------------------------------------
1313 BuildLAF 1315 BuildLAF
1314 Build logical address filter. 1316 Build logical address filter.
1315 Modified from Am79C90 data sheet. 1317 Modified from Am79C90 data sheet.
1316 1318
1317 Input 1319 Input
1318 ladrf: logical address filter (contents initialized to 0) 1320 ladrf: logical address filter (contents initialized to 0)
1319 adr: ethernet address 1321 adr: ethernet address
1320 ---------------------------------------------------------------------------- */ 1322 ---------------------------------------------------------------------------- */
1321 static void BuildLAF(int *ladrf, int *adr) 1323 static void BuildLAF(int *ladrf, int *adr)
1322 { 1324 {
1323 int CRC[33]={1}; /* CRC register, 1 word/bit + extra control bit */ 1325 int CRC[33]={1}; /* CRC register, 1 word/bit + extra control bit */
1324 1326
1325 int i, byte; /* temporary array indices */ 1327 int i, byte; /* temporary array indices */
1326 int hashcode; /* the output object */ 1328 int hashcode; /* the output object */
1327 1329
1328 CRC[32]=0; 1330 CRC[32]=0;
1329 1331
1330 for (byte = 0; byte < 6; byte++) 1332 for (byte = 0; byte < 6; byte++)
1331 for (i = 0; i < 8; i++) 1333 for (i = 0; i < 8; i++)
1332 updateCRC(CRC, (adr[byte] >> i) & 1); 1334 updateCRC(CRC, (adr[byte] >> i) & 1);
1333 1335
1334 hashcode = 0; 1336 hashcode = 0;
1335 for (i = 0; i < 6; i++) 1337 for (i = 0; i < 6; i++)
1336 hashcode = (hashcode << 1) + CRC[i]; 1338 hashcode = (hashcode << 1) + CRC[i];
1337 1339
1338 byte = hashcode >> 3; 1340 byte = hashcode >> 3;
1339 ladrf[byte] |= (1 << (hashcode & 7)); 1341 ladrf[byte] |= (1 << (hashcode & 7));
1340 1342
1341 #ifdef PCMCIA_DEBUG 1343 #ifdef PCMCIA_DEBUG
1342 if (0) 1344 if (0)
1343 printk(KERN_DEBUG " adr =%pM\n", adr); 1345 printk(KERN_DEBUG " adr =%pM\n", adr);
1344 printk(KERN_DEBUG " hashcode = %d(decimal), ladrf[0:63] =", hashcode); 1346 printk(KERN_DEBUG " hashcode = %d(decimal), ladrf[0:63] =", hashcode);
1345 for (i = 0; i < 8; i++) 1347 for (i = 0; i < 8; i++)
1346 pr_cont(" %02X", ladrf[i]); 1348 pr_cont(" %02X", ladrf[i]);
1347 pr_cont("\n"); 1349 pr_cont("\n");
1348 #endif 1350 #endif
1349 } /* BuildLAF */ 1351 } /* BuildLAF */
1350 1352
1351 /* ---------------------------------------------------------------------------- 1353 /* ----------------------------------------------------------------------------
1352 restore_multicast_list 1354 restore_multicast_list
1353 Restores the multicast filter for MACE chip to the last 1355 Restores the multicast filter for MACE chip to the last
1354 set_multicast_list() call. 1356 set_multicast_list() call.
1355 1357
1356 Input 1358 Input
1357 multicast_num_addrs 1359 multicast_num_addrs
1358 multicast_ladrf[] 1360 multicast_ladrf[]
1359 ---------------------------------------------------------------------------- */ 1361 ---------------------------------------------------------------------------- */
1360 static void restore_multicast_list(struct net_device *dev) 1362 static void restore_multicast_list(struct net_device *dev)
1361 { 1363 {
1362 mace_private *lp = netdev_priv(dev); 1364 mace_private *lp = netdev_priv(dev);
1363 int num_addrs = lp->multicast_num_addrs; 1365 int num_addrs = lp->multicast_num_addrs;
1364 int *ladrf = lp->multicast_ladrf; 1366 int *ladrf = lp->multicast_ladrf;
1365 unsigned int ioaddr = dev->base_addr; 1367 unsigned int ioaddr = dev->base_addr;
1366 int i; 1368 int i;
1367 1369
1368 pr_debug("%s: restoring Rx mode to %d addresses.\n", 1370 pr_debug("%s: restoring Rx mode to %d addresses.\n",
1369 dev->name, num_addrs); 1371 dev->name, num_addrs);
1370 1372
1371 if (num_addrs > 0) { 1373 if (num_addrs > 0) {
1372 1374
1373 pr_debug("Attempt to restore multicast list detected.\n"); 1375 pr_debug("Attempt to restore multicast list detected.\n");
1374 1376
1375 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_LOGADDR); 1377 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_LOGADDR);
1376 /* Poll ADDRCHG bit */ 1378 /* Poll ADDRCHG bit */
1377 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG) 1379 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
1378 ; 1380 ;
1379 /* Set LADRF register */ 1381 /* Set LADRF register */
1380 for (i = 0; i < MACE_LADRF_LEN; i++) 1382 for (i = 0; i < MACE_LADRF_LEN; i++)
1381 mace_write(lp, ioaddr, MACE_LADRF, ladrf[i]); 1383 mace_write(lp, ioaddr, MACE_LADRF, ladrf[i]);
1382 1384
1383 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_RCVFCSE | MACE_UTR_LOOP_EXTERNAL); 1385 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_RCVFCSE | MACE_UTR_LOOP_EXTERNAL);
1384 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); 1386 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1385 1387
1386 } else if (num_addrs < 0) { 1388 } else if (num_addrs < 0) {
1387 1389
1388 /* Promiscuous mode: receive all packets */ 1390 /* Promiscuous mode: receive all packets */
1389 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL); 1391 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1390 mace_write(lp, ioaddr, MACE_MACCC, 1392 mace_write(lp, ioaddr, MACE_MACCC,
1391 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV 1393 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1392 ); 1394 );
1393 1395
1394 } else { 1396 } else {
1395 1397
1396 /* Normal mode */ 1398 /* Normal mode */
1397 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL); 1399 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1398 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); 1400 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1399 1401
1400 } 1402 }
1401 } /* restore_multicast_list */ 1403 } /* restore_multicast_list */
1402 1404
1403 /* ---------------------------------------------------------------------------- 1405 /* ----------------------------------------------------------------------------
1404 set_multicast_list 1406 set_multicast_list
1405 Set or clear the multicast filter for this adaptor. 1407 Set or clear the multicast filter for this adaptor.
1406 1408
1407 Input 1409 Input
1408 num_addrs == -1 Promiscuous mode, receive all packets 1410 num_addrs == -1 Promiscuous mode, receive all packets
1409 num_addrs == 0 Normal mode, clear multicast list 1411 num_addrs == 0 Normal mode, clear multicast list
1410 num_addrs > 0 Multicast mode, receive normal and MC packets, and do 1412 num_addrs > 0 Multicast mode, receive normal and MC packets, and do
1411 best-effort filtering. 1413 best-effort filtering.
1412 Output 1414 Output
1413 multicast_num_addrs 1415 multicast_num_addrs
1414 multicast_ladrf[] 1416 multicast_ladrf[]
1415 ---------------------------------------------------------------------------- */ 1417 ---------------------------------------------------------------------------- */
1416 1418
1417 static void set_multicast_list(struct net_device *dev) 1419 static void set_multicast_list(struct net_device *dev)
1418 { 1420 {
1419 mace_private *lp = netdev_priv(dev); 1421 mace_private *lp = netdev_priv(dev);
1420 int adr[ETH_ALEN] = {0}; /* Ethernet address */ 1422 int adr[ETH_ALEN] = {0}; /* Ethernet address */
1421 struct netdev_hw_addr *ha; 1423 struct netdev_hw_addr *ha;
1422 1424
1423 #ifdef PCMCIA_DEBUG 1425 #ifdef PCMCIA_DEBUG
1424 { 1426 {
1425 static int old; 1427 static int old;
1426 if (netdev_mc_count(dev) != old) { 1428 if (netdev_mc_count(dev) != old) {
1427 old = netdev_mc_count(dev); 1429 old = netdev_mc_count(dev);
1428 pr_debug("%s: setting Rx mode to %d addresses.\n", 1430 pr_debug("%s: setting Rx mode to %d addresses.\n",
1429 dev->name, old); 1431 dev->name, old);
1430 } 1432 }
1431 } 1433 }
1432 #endif 1434 #endif
1433 1435
1434 /* Set multicast_num_addrs. */ 1436 /* Set multicast_num_addrs. */
1435 lp->multicast_num_addrs = netdev_mc_count(dev); 1437 lp->multicast_num_addrs = netdev_mc_count(dev);
1436 1438
1437 /* Set multicast_ladrf. */ 1439 /* Set multicast_ladrf. */
1438 if (num_addrs > 0) { 1440 if (num_addrs > 0) {
1439 /* Calculate multicast logical address filter */ 1441 /* Calculate multicast logical address filter */
1440 memset(lp->multicast_ladrf, 0, MACE_LADRF_LEN); 1442 memset(lp->multicast_ladrf, 0, MACE_LADRF_LEN);
1441 netdev_for_each_mc_addr(ha, dev) { 1443 netdev_for_each_mc_addr(ha, dev) {
1442 memcpy(adr, ha->addr, ETH_ALEN); 1444 memcpy(adr, ha->addr, ETH_ALEN);
1443 BuildLAF(lp->multicast_ladrf, adr); 1445 BuildLAF(lp->multicast_ladrf, adr);
1444 } 1446 }
1445 } 1447 }
1446 1448
1447 restore_multicast_list(dev); 1449 restore_multicast_list(dev);
1448 1450
1449 } /* set_multicast_list */ 1451 } /* set_multicast_list */
1450 1452
1451 #endif /* BROKEN_MULTICAST */ 1453 #endif /* BROKEN_MULTICAST */
1452 1454
1453 static void restore_multicast_list(struct net_device *dev) 1455 static void restore_multicast_list(struct net_device *dev)
1454 { 1456 {
1455 unsigned int ioaddr = dev->base_addr; 1457 unsigned int ioaddr = dev->base_addr;
1456 mace_private *lp = netdev_priv(dev); 1458 mace_private *lp = netdev_priv(dev);
1457 1459
1458 pr_debug("%s: restoring Rx mode to %d addresses.\n", dev->name, 1460 pr_debug("%s: restoring Rx mode to %d addresses.\n", dev->name,
1459 lp->multicast_num_addrs); 1461 lp->multicast_num_addrs);
1460 1462
1461 if (dev->flags & IFF_PROMISC) { 1463 if (dev->flags & IFF_PROMISC) {
1462 /* Promiscuous mode: receive all packets */ 1464 /* Promiscuous mode: receive all packets */
1463 mace_write(lp,ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL); 1465 mace_write(lp,ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1464 mace_write(lp, ioaddr, MACE_MACCC, 1466 mace_write(lp, ioaddr, MACE_MACCC,
1465 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV 1467 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1466 ); 1468 );
1467 } else { 1469 } else {
1468 /* Normal mode */ 1470 /* Normal mode */
1469 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL); 1471 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1470 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); 1472 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1471 } 1473 }
1472 } /* restore_multicast_list */ 1474 } /* restore_multicast_list */
1473 1475
1474 static void set_multicast_list(struct net_device *dev) 1476 static void set_multicast_list(struct net_device *dev)
1475 { 1477 {
1476 mace_private *lp = netdev_priv(dev); 1478 mace_private *lp = netdev_priv(dev);
1477 1479
1478 #ifdef PCMCIA_DEBUG 1480 #ifdef PCMCIA_DEBUG
1479 { 1481 {
1480 static int old; 1482 static int old;
1481 if (netdev_mc_count(dev) != old) { 1483 if (netdev_mc_count(dev) != old) {
1482 old = netdev_mc_count(dev); 1484 old = netdev_mc_count(dev);
1483 pr_debug("%s: setting Rx mode to %d addresses.\n", 1485 pr_debug("%s: setting Rx mode to %d addresses.\n",
1484 dev->name, old); 1486 dev->name, old);
1485 } 1487 }
1486 } 1488 }
1487 #endif 1489 #endif
1488 1490
1489 lp->multicast_num_addrs = netdev_mc_count(dev); 1491 lp->multicast_num_addrs = netdev_mc_count(dev);
1490 restore_multicast_list(dev); 1492 restore_multicast_list(dev);
1491 1493
1492 } /* set_multicast_list */ 1494 } /* set_multicast_list */
1493 1495
1494 static const struct pcmcia_device_id nmclan_ids[] = { 1496 static const struct pcmcia_device_id nmclan_ids[] = {
1495 PCMCIA_DEVICE_PROD_ID12("New Media Corporation", "Ethernet", 0x085a850b, 0x00b2e941), 1497 PCMCIA_DEVICE_PROD_ID12("New Media Corporation", "Ethernet", 0x085a850b, 0x00b2e941),
1496 PCMCIA_DEVICE_PROD_ID12("Portable Add-ons", "Ethernet+", 0xebf1d60, 0xad673aaf), 1498 PCMCIA_DEVICE_PROD_ID12("Portable Add-ons", "Ethernet+", 0xebf1d60, 0xad673aaf),
1497 PCMCIA_DEVICE_NULL, 1499 PCMCIA_DEVICE_NULL,
1498 }; 1500 };
1499 MODULE_DEVICE_TABLE(pcmcia, nmclan_ids); 1501 MODULE_DEVICE_TABLE(pcmcia, nmclan_ids);
1500 1502
1501 static struct pcmcia_driver nmclan_cs_driver = { 1503 static struct pcmcia_driver nmclan_cs_driver = {
1502 .owner = THIS_MODULE, 1504 .owner = THIS_MODULE,
1503 .name = "nmclan_cs", 1505 .name = "nmclan_cs",
1504 .probe = nmclan_probe, 1506 .probe = nmclan_probe,
1505 .remove = nmclan_detach, 1507 .remove = nmclan_detach,
1506 .id_table = nmclan_ids, 1508 .id_table = nmclan_ids,
1507 .suspend = nmclan_suspend, 1509 .suspend = nmclan_suspend,
1508 .resume = nmclan_resume, 1510 .resume = nmclan_resume,
1509 }; 1511 };
1510 module_pcmcia_driver(nmclan_cs_driver); 1512 module_pcmcia_driver(nmclan_cs_driver);
1511 1513