ARM: 8076/1: mm: add support for HW coherent systems in PL310 cache

When a PL310 cache is used on a system that provides hardware coherency, the outer cache sync operation is useless, and can be skipped. Moreover, on some systems, it is harmful as it causes deadlocks between the Marvell coherency mechanism, the Marvell PCIe controller and the Cortex-A9. To avoid this, this commit introduces a new Device Tree property 'arm,io-coherent' for the L2 cache controller node, valid only for the PL310 cache. It identifies the usage of the PL310 cache in an I/O coherent configuration. Internally, it makes the driver disable the outer cache sync operation. Note that technically speaking, a fully coherent system wouldn't require any of the other .outer_cache operations. However, in practice, when booting secondary CPUs, these are not yet coherent, and therefore a set of cache maintenance operations are necessary at this point. This explains why we keep the other .outer_cache operations and only ->sync is disabled. While in theory any write to a PL310 register could cause the deadlock, in practice, disabling ->sync is sufficient to workaround the deadlock, since the other cache maintenance operations are only used in very specific situations. Contrary to previous versions of this patch, this new version does not simply NULL-ify the ->sync member, because the l2c_init_data structures are now 'const' and therefore cannot be modified, which is a good thing. Therefore, this patch introduces a separate l2c_init_data instance, called of_l2c310_coherent_data. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

ARM: 8076/1: mm: add support for HW coherent systems in PL310 cache
When a PL310 cache is used on a system that provides hardware coherency, the outer cache sync operation is useless, and can be skipped. Moreover, on some systems, it is harmful as it causes deadlocks between the Marvell coherency mechanism, the Marvell PCIe controller and the Cortex-A9. To avoid this, this commit introduces a new Device Tree property 'arm,io-coherent' for the L2 cache controller node, valid only for the PL310 cache. It identifies the usage of the PL310 cache in an I/O coherent configuration. Internally, it makes the driver disable the outer cache sync operation. Note that technically speaking, a fully coherent system wouldn't require any of the other .outer_cache operations. However, in practice, when booting secondary CPUs, these are not yet coherent, and therefore a set of cache maintenance operations are necessary at this point. This explains why we keep the other .outer_cache operations and only ->sync is disabled. While in theory any write to a PL310 register could cause the deadlock, in practice, disabling ->sync is sufficient to workaround the deadlock, since the other cache maintenance operations are only used in very specific situations. Contrary to previous versions of this patch, this new version does not simply NULL-ify the ->sync member, because the l2c_init_data structures are now 'const' and therefore cannot be modified, which is a good thing. Therefore, this patch introduces a separate l2c_init_data instance, called of_l2c310_coherent_data. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Thomas Petazzoni · Russell King
1 parent b8d8772e53
Showing 2 changed files with 34 additions and 0 deletions Side-by-side Diff
Documentation/devicetree/bindings/arm/l2cc.txt
arch/arm/mm/cache-l2x0.c
@@ -40,6 +40,9 @@
 - arm,filter-ranges : <start length> Starting address and length of window to
   filter. Addresses in the filter window are directed to the M1 port. Other
   addresses will go to the M0 port.
+- arm,io-coherent : indicates that the system is operating in an hardware
+  I/O coherent mode. Valid only when the arm,pl310-cache compatible
+  string is used.
 - interrupts : 1 combined interrupt.
 - cache-id-part: cache id part number to be used if it is not present
   on hardware
@@ -1069,6 +1069,33 @@
 };
  
 /*
+ * This is a variant of the of_l2c310_data with .sync set to
+ * NULL. Outer sync operations are not needed when the system is I/O
+ * coherent, and potentially harmful in certain situations (PCIe/PL310
+ * deadlock on Armada 375/38x due to hardware I/O coherency). The
+ * other operations are kept because they are infrequent (therefore do
+ * not cause the deadlock in practice) and needed for secondary CPU
+ * boot and other power management activities.
+ */
+static const struct l2c_init_data of_l2c310_coherent_data __initconst = {
+	.type = "L2C-310 Coherent",
+	.way_size_0 = SZ_8K,
+	.num_lock = 8,
+	.of_parse = l2c310_of_parse,
+	.enable = l2c310_enable,
+	.fixup = l2c310_fixup,
+	.save  = l2c310_save,
+	.outer_cache = {
+		.inv_range   = l2c210_inv_range,
+		.clean_range = l2c210_clean_range,
+		.flush_range = l2c210_flush_range,
+		.flush_all   = l2c210_flush_all,
+		.disable     = l2c310_disable,
+		.resume      = l2c310_resume,
+	},
+};
+
+/*
  * Note that the end addresses passed to Linux primitives are
  * noninclusive, while the hardware cache range operations use
  * inclusive start and end addresses.
@@ -1486,6 +1513,10 @@
 	l2x0_saved_regs.phy_base = res.start;
  
 	data = of_match_node(l2x0_ids, np)->data;
+
+	if (of_device_is_compatible(np, "arm,pl310-cache") &&
+	    of_property_read_bool(np, "arm,io-coherent"))
+		data = &of_l2c310_coherent_data;
  
 	old_aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
 	if (old_aux != ((old_aux & aux_mask) | aux_val)) {
...	...	@@ -40,6 +40,9 @@
40	40	- arm,filter-ranges : <start length> Starting address and length of window to
41	41	filter. Addresses in the filter window are directed to the M1 port. Other
42	42	addresses will go to the M0 port.
	43	+- arm,io-coherent : indicates that the system is operating in an hardware
	44	+ I/O coherent mode. Valid only when the arm,pl310-cache compatible
	45	+ string is used.
43	46	- interrupts : 1 combined interrupt.
44	47	- cache-id-part: cache id part number to be used if it is not present
45	48	on hardware
...	...	@@ -1069,6 +1069,33 @@
1069	1069	};
1070	1070
1071	1071	/*
	1072	+ * This is a variant of the of_l2c310_data with .sync set to
	1073	+ * NULL. Outer sync operations are not needed when the system is I/O
	1074	+ * coherent, and potentially harmful in certain situations (PCIe/PL310
	1075	+ * deadlock on Armada 375/38x due to hardware I/O coherency). The
	1076	+ * other operations are kept because they are infrequent (therefore do
	1077	+ * not cause the deadlock in practice) and needed for secondary CPU
	1078	+ * boot and other power management activities.
	1079	+ */
	1080	+static const struct l2c_init_data of_l2c310_coherent_data __initconst = {
	1081	+ .type = "L2C-310 Coherent",
	1082	+ .way_size_0 = SZ_8K,
	1083	+ .num_lock = 8,
	1084	+ .of_parse = l2c310_of_parse,
	1085	+ .enable = l2c310_enable,
	1086	+ .fixup = l2c310_fixup,
	1087	+ .save = l2c310_save,
	1088	+ .outer_cache = {
	1089	+ .inv_range = l2c210_inv_range,
	1090	+ .clean_range = l2c210_clean_range,
	1091	+ .flush_range = l2c210_flush_range,
	1092	+ .flush_all = l2c210_flush_all,
	1093	+ .disable = l2c310_disable,
	1094	+ .resume = l2c310_resume,
	1095	+ },
	1096	+};
	1097	+
	1098	+/*
1072	1099	* Note that the end addresses passed to Linux primitives are
1073	1100	* noninclusive, while the hardware cache range operations use
1074	1101	* inclusive start and end addresses.
...	...	@@ -1486,6 +1513,10 @@
1486	1513	l2x0_saved_regs.phy_base = res.start;
1487	1514
1488	1515	data = of_match_node(l2x0_ids, np)->data;
	1516	+
	1517	+ if (of_device_is_compatible(np, "arm,pl310-cache") &&
	1518	+ of_property_read_bool(np, "arm,io-coherent"))
	1519	+ data = &of_l2c310_coherent_data;
1489	1520
1490	1521	old_aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
1491	1522	if (old_aux != ((old_aux & aux_mask) \| aux_val)) {