Eric Lee / smarc-ti-linux-kernel

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Commit 98f87a7ba278e6b9064b8022728c9c14ed467ebe

Authored by Michael Turquette
2 parents 97bf6af1f9 9880d4277f
Exists in ti-lsk-linux-4.1.y and in 10 other branches dlt-processor-sdk-linux-03.00.00.04, processor-sdk-linux-02.00.01, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04

Merge tag 'v3.19-rockhip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel… 

…/git/mmind/linux-rockchip into clk-fixes

- two currently unused clocks that need to stay enabled
- fix the lock bit locations of the rk3066 plls
- fix rk3288 core divider values to the ones actually
  specified by the soc vendor

Showing 2 changed files Side-by-side Diff

drivers/clk/rockchip/clk-rk3188.c
Diff comments   View file @ 98f87a7
... ... @@ -210,6 +210,17 @@
210 210 PNAME(mux_mac_p) = { "gpll", "dpll" };
211 211 PNAME(mux_sclk_macref_p) = { "mac_src", "ext_rmii" };
212 212  
  213 +static struct rockchip_pll_clock rk3066_pll_clks[] __initdata = {
  214 + [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
  215 + RK2928_MODE_CON, 0, 5, 0, rk3188_pll_rates),
  216 + [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
  217 + RK2928_MODE_CON, 4, 4, 0, NULL),
  218 + [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
  219 + RK2928_MODE_CON, 8, 6, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
  220 + [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
  221 + RK2928_MODE_CON, 12, 7, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
  222 +};
  223 +
213 224 static struct rockchip_pll_clock rk3188_pll_clks[] __initdata = {
214 225 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
215 226 RK2928_MODE_CON, 0, 6, 0, rk3188_pll_rates),
216 227  
... ... @@ -427,11 +438,11 @@
427 438 /* hclk_peri gates */
428 439 GATE(0, "hclk_peri_axi_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS),
429 440 GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 6, GFLAGS),
430   - GATE(0, "hclk_emem_peri", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 7, GFLAGS),
  441 + GATE(0, "hclk_emem_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 7, GFLAGS),
431 442 GATE(HCLK_EMAC, "hclk_emac", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS),
432 443 GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
433   - GATE(0, "hclk_usb_peri", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 5, GFLAGS),
434   - GATE(HCLK_OTG0, "hclk_usbotg0", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 13, GFLAGS),
  444 + GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 5, GFLAGS),
  445 + GATE(HCLK_OTG0, "hclk_usbotg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS),
435 446 GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 5, GFLAGS),
436 447 GATE(HCLK_PIDF, "hclk_pidfilter", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 6, GFLAGS),
437 448 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS),
... ... @@ -592,7 +603,8 @@
592 603 GATE(0, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS),
593 604 GATE(0, "hclk_hdmi", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
594 605  
595   - GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS),
  606 + GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED,
  607 + RK2928_CLKGATE_CON(5), 14, GFLAGS),
596 608  
597 609 GATE(0, "aclk_cif1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 7, GFLAGS),
598 610  
... ... @@ -680,7 +692,8 @@
680 692 GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
681 693 GATE(0, "hclk_imem1", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 15, GFLAGS),
682 694  
683   - GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
  695 + GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED,
  696 + RK2928_CLKGATE_CON(7), 3, GFLAGS),
684 697 GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
685 698  
686 699 GATE(PCLK_TIMER3, "pclk_timer3", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS),
... ... @@ -735,8 +748,8 @@
735 748 static void __init rk3066a_clk_init(struct device_node *np)
736 749 {
737 750 rk3188_common_clk_init(np);
738   - rockchip_clk_register_plls(rk3188_pll_clks,
739   - ARRAY_SIZE(rk3188_pll_clks),
  751 + rockchip_clk_register_plls(rk3066_pll_clks,
  752 + ARRAY_SIZE(rk3066_pll_clks),
740 753 RK3066_GRF_SOC_STATUS);
741 754 rockchip_clk_register_branches(rk3066a_clk_branches,
742 755 ARRAY_SIZE(rk3066a_clk_branches));
drivers/clk/rockchip/clk-rk3288.c
Diff comments   View file @ 98f87a7
... ... @@ -145,20 +145,20 @@
145 145 }
146 146  
147 147 static struct rockchip_cpuclk_rate_table rk3288_cpuclk_rates[] __initdata = {
148   - RK3288_CPUCLK_RATE(1800000000, 2, 4, 2, 4, 4),
149   - RK3288_CPUCLK_RATE(1704000000, 2, 4, 2, 4, 4),
150   - RK3288_CPUCLK_RATE(1608000000, 2, 4, 2, 4, 4),
151   - RK3288_CPUCLK_RATE(1512000000, 2, 4, 2, 4, 4),
152   - RK3288_CPUCLK_RATE(1416000000, 2, 4, 2, 4, 4),
153   - RK3288_CPUCLK_RATE(1200000000, 2, 4, 2, 4, 4),
154   - RK3288_CPUCLK_RATE(1008000000, 2, 4, 2, 4, 4),
155   - RK3288_CPUCLK_RATE( 816000000, 2, 4, 2, 4, 4),
156   - RK3288_CPUCLK_RATE( 696000000, 2, 4, 2, 4, 4),
157   - RK3288_CPUCLK_RATE( 600000000, 2, 4, 2, 4, 4),
158   - RK3288_CPUCLK_RATE( 408000000, 2, 4, 2, 4, 4),
159   - RK3288_CPUCLK_RATE( 312000000, 2, 4, 2, 4, 4),
160   - RK3288_CPUCLK_RATE( 216000000, 2, 4, 2, 4, 4),
161   - RK3288_CPUCLK_RATE( 126000000, 2, 4, 2, 4, 4),
  148 + RK3288_CPUCLK_RATE(1800000000, 1, 3, 1, 3, 3),
  149 + RK3288_CPUCLK_RATE(1704000000, 1, 3, 1, 3, 3),
  150 + RK3288_CPUCLK_RATE(1608000000, 1, 3, 1, 3, 3),
  151 + RK3288_CPUCLK_RATE(1512000000, 1, 3, 1, 3, 3),
  152 + RK3288_CPUCLK_RATE(1416000000, 1, 3, 1, 3, 3),
  153 + RK3288_CPUCLK_RATE(1200000000, 1, 3, 1, 3, 3),
  154 + RK3288_CPUCLK_RATE(1008000000, 1, 3, 1, 3, 3),
  155 + RK3288_CPUCLK_RATE( 816000000, 1, 3, 1, 3, 3),
  156 + RK3288_CPUCLK_RATE( 696000000, 1, 3, 1, 3, 3),
  157 + RK3288_CPUCLK_RATE( 600000000, 1, 3, 1, 3, 3),
  158 + RK3288_CPUCLK_RATE( 408000000, 1, 3, 1, 3, 3),
  159 + RK3288_CPUCLK_RATE( 312000000, 1, 3, 1, 3, 3),
  160 + RK3288_CPUCLK_RATE( 216000000, 1, 3, 1, 3, 3),
  161 + RK3288_CPUCLK_RATE( 126000000, 1, 3, 1, 3, 3),
162 162 };
163 163  
164 164 static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = {