Commit a0c9a822bf37e6282eb6006b407ec5aec22e08fb

Authored by Michael S. Tsirkin
Committed by Marcelo Tosatti
1 parent e59717550e

KVM: dont clear TMR on EOI

Intel spec says that TMR needs to be set/cleared
when IRR is set, but kvm also clears it on  EOI.

I did some tests on a real (AMD based) system,
and I see same TMR values both before
and after EOI, so I think it's a minor bug in kvm.

This patch fixes TMR to be set/cleared on IRR set
only as per spec.

And now that we don't clear TMR, we can save
an atomic read of TMR on EOI that's not propagated
to ioapic, by checking whether ioapic needs
a specific vector first and calculating
the mode afterwards.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>

Showing 3 changed files with 21 additions and 9 deletions Side-by-side Diff

arch/x86/kvm/lapic.c
... ... @@ -92,6 +92,11 @@
92 92 return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
93 93 }
94 94  
  95 +static inline int apic_test_vector(int vec, void *bitmap)
  96 +{
  97 + return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  98 +}
  99 +
95 100 static inline void apic_set_vector(int vec, void *bitmap)
96 101 {
97 102 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
... ... @@ -480,7 +485,6 @@
480 485 static void apic_set_eoi(struct kvm_lapic *apic)
481 486 {
482 487 int vector = apic_find_highest_isr(apic);
483   - int trigger_mode;
484 488 /*
485 489 * Not every write EOI will has corresponding ISR,
486 490 * one example is when Kernel check timer on setup_IO_APIC
487 491  
... ... @@ -491,12 +495,15 @@
491 495 apic_clear_vector(vector, apic->regs + APIC_ISR);
492 496 apic_update_ppr(apic);
493 497  
494   - if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
495   - trigger_mode = IOAPIC_LEVEL_TRIG;
496   - else
497   - trigger_mode = IOAPIC_EDGE_TRIG;
498   - if (!(apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI))
  498 + if (!(apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
  499 + kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
  500 + int trigger_mode;
  501 + if (apic_test_vector(vector, apic->regs + APIC_TMR))
  502 + trigger_mode = IOAPIC_LEVEL_TRIG;
  503 + else
  504 + trigger_mode = IOAPIC_EDGE_TRIG;
499 505 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
  506 + }
500 507 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
501 508 }
502 509  
... ... @@ -254,13 +254,17 @@
254 254 }
255 255 }
256 256  
  257 +bool kvm_ioapic_handles_vector(struct kvm *kvm, int vector)
  258 +{
  259 + struct kvm_ioapic *ioapic = kvm->arch.vioapic;
  260 + smp_rmb();
  261 + return test_bit(vector, ioapic->handled_vectors);
  262 +}
  263 +
257 264 void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
258 265 {
259 266 struct kvm_ioapic *ioapic = kvm->arch.vioapic;
260 267  
261   - smp_rmb();
262   - if (!test_bit(vector, ioapic->handled_vectors))
263   - return;
264 268 spin_lock(&ioapic->lock);
265 269 __kvm_ioapic_update_eoi(ioapic, vector, trigger_mode);
266 270 spin_unlock(&ioapic->lock);
... ... @@ -71,6 +71,7 @@
71 71 int short_hand, int dest, int dest_mode);
72 72 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2);
73 73 void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode);
  74 +bool kvm_ioapic_handles_vector(struct kvm *kvm, int vector);
74 75 int kvm_ioapic_init(struct kvm *kvm);
75 76 void kvm_ioapic_destroy(struct kvm *kvm);
76 77 int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level);