Commit a1fc198046181304d28a018dba048b718f2d7ce4
Committed by
Shawn Guo
1 parent
f114040e3e
Exists in
ti-lsk-linux-4.1.y
and in
10 other branches
ARM: i.MX6: Fix "emi" clock name typo
Fix a typo error, the "emi" names refer to the eim clocks. The change fixes typo in EIM and EIM_SLOW pre-output dividers and selectors clock names. Notably EIM_SLOW clock itself is named correctly. Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> [vladimir_zapolskiy@mentor.com: ported to v3.17] Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Cc: Sascha Hauer <kernel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Showing 2 changed files with 11 additions and 11 deletions Side-by-side Diff
arch/arm/mach-imx/clk-imx6q.c
... | ... | @@ -50,8 +50,8 @@ |
50 | 50 | static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", }; |
51 | 51 | static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; |
52 | 52 | static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", }; |
53 | -static const char *emi_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", }; | |
54 | -static const char *emi_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", }; | |
53 | +static const char *eim_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", }; | |
54 | +static const char *eim_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", }; | |
55 | 55 | static const char *vdo_axi_sels[] = { "axi", "ahb", }; |
56 | 56 | static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", }; |
57 | 57 | static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div", |
... | ... | @@ -302,8 +302,8 @@ |
302 | 302 | clk[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); |
303 | 303 | clk[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); |
304 | 304 | clk[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels)); |
305 | - clk[IMX6QDL_CLK_EMI_SEL] = imx_clk_fixup_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels), imx_cscmr1_fixup); | |
306 | - clk[IMX6QDL_CLK_EMI_SLOW_SEL] = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels), imx_cscmr1_fixup); | |
305 | + clk[IMX6QDL_CLK_EIM_SEL] = imx_clk_fixup_mux("eim_sel", base + 0x1c, 27, 2, eim_sels, ARRAY_SIZE(eim_sels), imx_cscmr1_fixup); | |
306 | + clk[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_fixup_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels), imx_cscmr1_fixup); | |
307 | 307 | clk[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels)); |
308 | 308 | clk[IMX6QDL_CLK_VPU_AXI_SEL] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels)); |
309 | 309 | clk[IMX6QDL_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); |
... | ... | @@ -354,8 +354,8 @@ |
354 | 354 | clk[IMX6QDL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); |
355 | 355 | clk[IMX6QDL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); |
356 | 356 | clk[IMX6QDL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); |
357 | - clk[IMX6QDL_CLK_EMI_PODF] = imx_clk_fixup_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup); | |
358 | - clk[IMX6QDL_CLK_EMI_SLOW_PODF] = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup); | |
357 | + clk[IMX6QDL_CLK_EIM_PODF] = imx_clk_fixup_divider("eim_podf", "eim_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup); | |
358 | + clk[IMX6QDL_CLK_EIM_SLOW_PODF] = imx_clk_fixup_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup); | |
359 | 359 | clk[IMX6QDL_CLK_VPU_AXI_PODF] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3); |
360 | 360 | clk[IMX6QDL_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3); |
361 | 361 | clk[IMX6QDL_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3); |
... | ... | @@ -456,7 +456,7 @@ |
456 | 456 | clk[IMX6QDL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); |
457 | 457 | clk[IMX6QDL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); |
458 | 458 | clk[IMX6QDL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); |
459 | - clk[IMX6QDL_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "emi_slow_podf", base + 0x80, 10); | |
459 | + clk[IMX6QDL_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "eim_slow_podf", base + 0x80, 10); | |
460 | 460 | clk[IMX6QDL_CLK_VDO_AXI] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12); |
461 | 461 | clk[IMX6QDL_CLK_VPU_AXI] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14); |
462 | 462 | clk[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); |
include/dt-bindings/clock/imx6qdl-clock.h
... | ... | @@ -62,8 +62,8 @@ |
62 | 62 | #define IMX6QDL_CLK_USDHC3_SEL 50 |
63 | 63 | #define IMX6QDL_CLK_USDHC4_SEL 51 |
64 | 64 | #define IMX6QDL_CLK_ENFC_SEL 52 |
65 | -#define IMX6QDL_CLK_EMI_SEL 53 | |
66 | -#define IMX6QDL_CLK_EMI_SLOW_SEL 54 | |
65 | +#define IMX6QDL_CLK_EIM_SEL 53 | |
66 | +#define IMX6QDL_CLK_EIM_SLOW_SEL 54 | |
67 | 67 | #define IMX6QDL_CLK_VDO_AXI_SEL 55 |
68 | 68 | #define IMX6QDL_CLK_VPU_AXI_SEL 56 |
69 | 69 | #define IMX6QDL_CLK_CKO1_SEL 57 |
... | ... | @@ -106,8 +106,8 @@ |
106 | 106 | #define IMX6QDL_CLK_USDHC4_PODF 94 |
107 | 107 | #define IMX6QDL_CLK_ENFC_PRED 95 |
108 | 108 | #define IMX6QDL_CLK_ENFC_PODF 96 |
109 | -#define IMX6QDL_CLK_EMI_PODF 97 | |
110 | -#define IMX6QDL_CLK_EMI_SLOW_PODF 98 | |
109 | +#define IMX6QDL_CLK_EIM_PODF 97 | |
110 | +#define IMX6QDL_CLK_EIM_SLOW_PODF 98 | |
111 | 111 | #define IMX6QDL_CLK_VPU_AXI_PODF 99 |
112 | 112 | #define IMX6QDL_CLK_CKO1_PODF 100 |
113 | 113 | #define IMX6QDL_CLK_AXI 101 |