Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

Pull drm/intel fixes from Dave Airlie: "Just some intel fixes. I have some radeon ones but I need to get some patches dropped from the pull req" * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm/i915: Increase WM memory latency values on SNB drm/i915: restore backlight precision when converting from ACPI drm/i915: Use the first mode if there is no preferred mode in the EDID drm/i915/dp: force eDP lane count to max available lanes on BDW drm/i915/vlv: reset VLV media force wake request register drm/i915/SDVO: For sysfs link put directory and target in correct order drm/i915: use lane count and link rate from VBT as minimums for eDP drm/i915: clean up VBT eDP link param decoding drm/i915: consider the source max DP lane count too

Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm/intel fixes from Dave Airlie: "Just some intel fixes. I have some radeon ones but I need to get some patches dropped from the pull req" * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm/i915: Increase WM memory latency values on SNB drm/i915: restore backlight precision when converting from ACPI drm/i915: Use the first mode if there is no preferred mode in the EDID drm/i915/dp: force eDP lane count to max available lanes on BDW drm/i915/vlv: reset VLV media force wake request register drm/i915/SDVO: For sysfs link put directory and target in correct order drm/i915: use lane count and link rate from VBT as minimums for eDP drm/i915: clean up VBT eDP link param decoding drm/i915: consider the source max DP lane count too
Linus Torvalds
2 parents 172de656b9 4ba4801d73
Showing 7 changed files Side-by-side Diff
drivers/gpu/drm/i915/intel_bios.c
drivers/gpu/drm/i915/intel_dp.c
drivers/gpu/drm/i915/intel_fbdev.c
drivers/gpu/drm/i915/intel_panel.c
drivers/gpu/drm/i915/intel_pm.c
drivers/gpu/drm/i915/intel_sdvo.c
drivers/gpu/drm/i915/intel_uncore.c
@@ -560,46 +560,70 @@
  
 	dev_priv->vbt.edp_pps = *edp_pps;
  
-	dev_priv->vbt.edp_rate = edp_link_params->rate ? DP_LINK_BW_2_7 :
-		DP_LINK_BW_1_62;
+	switch (edp_link_params->rate) {
+	case EDP_RATE_1_62:
+		dev_priv->vbt.edp_rate = DP_LINK_BW_1_62;
+		break;
+	case EDP_RATE_2_7:
+		dev_priv->vbt.edp_rate = DP_LINK_BW_2_7;
+		break;
+	default:
+		DRM_DEBUG_KMS("VBT has unknown eDP link rate value %u\n",
+			      edp_link_params->rate);
+		break;
+	}
+
 	switch (edp_link_params->lanes) {
-	case 0:
+	case EDP_LANE_1:
 		dev_priv->vbt.edp_lanes = 1;
 		break;
-	case 1:
+	case EDP_LANE_2:
 		dev_priv->vbt.edp_lanes = 2;
 		break;
-	case 3:
-	default:
+	case EDP_LANE_4:
 		dev_priv->vbt.edp_lanes = 4;
 		break;
+	default:
+		DRM_DEBUG_KMS("VBT has unknown eDP lane count value %u\n",
+			      edp_link_params->lanes);
+		break;
 	}
+
 	switch (edp_link_params->preemphasis) {
-	case 0:
+	case EDP_PREEMPHASIS_NONE:
 		dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_0;
 		break;
-	case 1:
+	case EDP_PREEMPHASIS_3_5dB:
 		dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_3_5;
 		break;
-	case 2:
+	case EDP_PREEMPHASIS_6dB:
 		dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_6;
 		break;
-	case 3:
+	case EDP_PREEMPHASIS_9_5dB:
 		dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_9_5;
 		break;
+	default:
+		DRM_DEBUG_KMS("VBT has unknown eDP pre-emphasis value %u\n",
+			      edp_link_params->preemphasis);
+		break;
 	}
+
 	switch (edp_link_params->vswing) {
-	case 0:
+	case EDP_VSWING_0_4V:
 		dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_400;
 		break;
-	case 1:
+	case EDP_VSWING_0_6V:
 		dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_600;
 		break;
-	case 2:
+	case EDP_VSWING_0_8V:
 		dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_800;
 		break;
-	case 3:
+	case EDP_VSWING_1_2V:
 		dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_1200;
+		break;
+	default:
+		DRM_DEBUG_KMS("VBT has unknown eDP voltage swing value %u\n",
+			      edp_link_params->vswing);
 		break;
 	}
 }
@@ -121,6 +121,22 @@
 	return max_link_bw;
 }
  
+static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = intel_dig_port->base.base.dev;
+	u8 source_max, sink_max;
+
+	source_max = 4;
+	if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
+	    (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
+		source_max = 2;
+
+	sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
+
+	return min(source_max, sink_max);
+}
+
 /*
  * The units on the numbers in the next two are... bizarre.  Examples will
  * make it clearer; this one parallels an example in the eDP spec.
@@ -171,7 +187,7 @@
 	}
  
 	max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
-	max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
+	max_lanes = intel_dp_max_lane_count(intel_dp);
  
 	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 	mode_rate = intel_dp_link_required(target_clock, 18);
  
@@ -751,8 +767,10 @@
 	struct intel_crtc *intel_crtc = encoder->new_crtc;
 	struct intel_connector *intel_connector = intel_dp->attached_connector;
 	int lane_count, clock;
-	int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
+	int min_lane_count = 1;
+	int max_lane_count = intel_dp_max_lane_count(intel_dp);
 	/* Conveniently, the link BW constants become indices with a shift...*/
+	int min_clock = 0;
 	int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
 	int bpp, mode_rate;
 	static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
  
@@ -785,19 +803,38 @@
 	/* Walk through all bpp values. Luckily they're all nicely spaced with 2
 	 * bpc in between. */
 	bpp = pipe_config->pipe_bpp;
-	if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
-	    dev_priv->vbt.edp_bpp < bpp) {
-		DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
-			      dev_priv->vbt.edp_bpp);
-		bpp = dev_priv->vbt.edp_bpp;
+	if (is_edp(intel_dp)) {
+		if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
+			DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
+				      dev_priv->vbt.edp_bpp);
+			bpp = dev_priv->vbt.edp_bpp;
+		}
+
+		if (IS_BROADWELL(dev)) {
+			/* Yes, it's an ugly hack. */
+			min_lane_count = max_lane_count;
+			DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
+				      min_lane_count);
+		} else if (dev_priv->vbt.edp_lanes) {
+			min_lane_count = min(dev_priv->vbt.edp_lanes,
+					     max_lane_count);
+			DRM_DEBUG_KMS("using min %u lanes per VBT\n",
+				      min_lane_count);
+		}
+
+		if (dev_priv->vbt.edp_rate) {
+			min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
+			DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
+				      bws[min_clock]);
+		}
 	}
  
 	for (; bpp >= 6*3; bpp -= 2*3) {
 		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
 						   bpp);
  
-		for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
-			for (clock = 0; clock <= max_clock; clock++) {
+		for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
+			for (clock = min_clock; clock <= max_clock; clock++) {
 				link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
 				link_avail = intel_dp_max_data_rate(link_clock,
 								    lane_count);
@@ -387,6 +387,15 @@
 							  height);
 		}
  
+		/* No preferred mode marked by the EDID? Are there any modes? */
+		if (!modes[i] && !list_empty(&connector->modes)) {
+			DRM_DEBUG_KMS("using first mode listed on connector %s\n",
+				      drm_get_connector_name(connector));
+			modes[i] = list_first_entry(&connector->modes,
+						    struct drm_display_mode,
+						    head);
+		}
+
 		/* last resort: use current mode */
 		if (!modes[i]) {
 			/*
@@ -492,6 +492,7 @@
 	enum pipe pipe = intel_get_pipe_from_connector(connector);
 	u32 freq;
 	unsigned long flags;
+	u64 n;
  
 	if (!panel->backlight.present || pipe == INVALID_PIPE)
 		return;
@@ -502,10 +503,9 @@
  
 	/* scale to hardware max, but be careful to not overflow */
 	freq = panel->backlight.max;
-	if (freq < max)
-		level = level * freq / max;
-	else
-		level = freq / max * level;
+	n = (u64)level * freq;
+	do_div(n, max);
+	level = n;
  
 	panel->backlight.level = level;
 	if (panel->backlight.device)
@@ -2095,6 +2095,43 @@
 	}
 }
  
+static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
+				    uint16_t wm[5], uint16_t min)
+{
+	int level, max_level = ilk_wm_max_level(dev_priv->dev);
+
+	if (wm[0] >= min)
+		return false;
+
+	wm[0] = max(wm[0], min);
+	for (level = 1; level <= max_level; level++)
+		wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
+
+	return true;
+}
+
+static void snb_wm_latency_quirk(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	bool changed;
+
+	/*
+	 * The BIOS provided WM memory latency values are often
+	 * inadequate for high resolution displays. Adjust them.
+	 */
+	changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
+		ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
+		ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
+
+	if (!changed)
+		return;
+
+	DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
+	intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
+	intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
+	intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
+}
+
 static void ilk_setup_wm_latency(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2112,6 +2149,9 @@
 	intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
 	intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
 	intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
+
+	if (IS_GEN6(dev))
+		snb_wm_latency_quirk(dev);
 }
  
 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
@@ -2424,8 +2424,8 @@
 	if (ret < 0)
 		goto err1;
  
-	ret = sysfs_create_link(&encoder->ddc.dev.kobj,
-				&drm_connector->kdev->kobj,
+	ret = sysfs_create_link(&drm_connector->kdev->kobj,
+				&encoder->ddc.dev.kobj,
 				encoder->ddc.dev.kobj.name);
 	if (ret < 0)
 		goto err2;
@@ -185,6 +185,8 @@
 {
 	__raw_i915_write32(dev_priv, FORCEWAKE_VLV,
 			   _MASKED_BIT_DISABLE(0xffff));
+	__raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
+			   _MASKED_BIT_DISABLE(0xffff));
 	/* something from same cacheline, but !FORCEWAKE_VLV */
 	__raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
 }
...	...	@@ -560,46 +560,70 @@
560	560
561	561	dev_priv->vbt.edp_pps = *edp_pps;
562	562
563		- dev_priv->vbt.edp_rate = edp_link_params->rate ? DP_LINK_BW_2_7 :
564		- DP_LINK_BW_1_62;
	563	+ switch (edp_link_params->rate) {
	564	+ case EDP_RATE_1_62:
	565	+ dev_priv->vbt.edp_rate = DP_LINK_BW_1_62;
	566	+ break;
	567	+ case EDP_RATE_2_7:
	568	+ dev_priv->vbt.edp_rate = DP_LINK_BW_2_7;
	569	+ break;
	570	+ default:
	571	+ DRM_DEBUG_KMS("VBT has unknown eDP link rate value %u\n",
	572	+ edp_link_params->rate);
	573	+ break;
	574	+ }
	575	+
565	576	switch (edp_link_params->lanes) {
566		- case 0:
	577	+ case EDP_LANE_1:
567	578	dev_priv->vbt.edp_lanes = 1;
568	579	break;
569		- case 1:
	580	+ case EDP_LANE_2:
570	581	dev_priv->vbt.edp_lanes = 2;
571	582	break;
572		- case 3:
573		- default:
	583	+ case EDP_LANE_4:
574	584	dev_priv->vbt.edp_lanes = 4;
575	585	break;
	586	+ default:
	587	+ DRM_DEBUG_KMS("VBT has unknown eDP lane count value %u\n",
	588	+ edp_link_params->lanes);
	589	+ break;
576	590	}
	591	+
577	592	switch (edp_link_params->preemphasis) {
578		- case 0:
	593	+ case EDP_PREEMPHASIS_NONE:
579	594	dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_0;
580	595	break;
581		- case 1:
	596	+ case EDP_PREEMPHASIS_3_5dB:
582	597	dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_3_5;
583	598	break;
584		- case 2:
	599	+ case EDP_PREEMPHASIS_6dB:
585	600	dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_6;
586	601	break;
587		- case 3:
	602	+ case EDP_PREEMPHASIS_9_5dB:
588	603	dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_9_5;
589	604	break;
	605	+ default:
	606	+ DRM_DEBUG_KMS("VBT has unknown eDP pre-emphasis value %u\n",
	607	+ edp_link_params->preemphasis);
	608	+ break;
590	609	}
	610	+
591	611	switch (edp_link_params->vswing) {
592		- case 0:
	612	+ case EDP_VSWING_0_4V:
593	613	dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_400;
594	614	break;
595		- case 1:
	615	+ case EDP_VSWING_0_6V:
596	616	dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_600;
597	617	break;
598		- case 2:
	618	+ case EDP_VSWING_0_8V:
599	619	dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_800;
600	620	break;
601		- case 3:
	621	+ case EDP_VSWING_1_2V:
602	622	dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_1200;
	623	+ break;
	624	+ default:
	625	+ DRM_DEBUG_KMS("VBT has unknown eDP voltage swing value %u\n",
	626	+ edp_link_params->vswing);
603	627	break;
604	628	}
605	629	}
...	...	@@ -121,6 +121,22 @@
121	121	return max_link_bw;
122	122	}
123	123
	124	+static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
	125	+{
	126	+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	127	+ struct drm_device *dev = intel_dig_port->base.base.dev;
	128	+ u8 source_max, sink_max;
	129	+
	130	+ source_max = 4;
	131	+ if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
	132	+ (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
	133	+ source_max = 2;
	134	+
	135	+ sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
	136	+
	137	+ return min(source_max, sink_max);
	138	+}
	139	+
124	140	/*
125	141	* The units on the numbers in the next two are... bizarre. Examples will
126	142	* make it clearer; this one parallels an example in the eDP spec.
...	...	@@ -171,7 +187,7 @@
171	187	}
172	188
173	189	max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
174		- max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
	190	+ max_lanes = intel_dp_max_lane_count(intel_dp);
175	191
176	192	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
177	193	mode_rate = intel_dp_link_required(target_clock, 18);
178	194
...	...	@@ -751,8 +767,10 @@
751	767	struct intel_crtc *intel_crtc = encoder->new_crtc;
752	768	struct intel_connector *intel_connector = intel_dp->attached_connector;
753	769	int lane_count, clock;
754		- int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
	770	+ int min_lane_count = 1;
	771	+ int max_lane_count = intel_dp_max_lane_count(intel_dp);
755	772	/* Conveniently, the link BW constants become indices with a shift...*/
	773	+ int min_clock = 0;
756	774	int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
757	775	int bpp, mode_rate;
758	776	static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
759	777
...	...	@@ -785,19 +803,38 @@
785	803	/* Walk through all bpp values. Luckily they're all nicely spaced with 2
786	804	* bpc in between. */
787	805	bpp = pipe_config->pipe_bpp;
788		- if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
789		- dev_priv->vbt.edp_bpp < bpp) {
790		- DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
791		- dev_priv->vbt.edp_bpp);
792		- bpp = dev_priv->vbt.edp_bpp;
	806	+ if (is_edp(intel_dp)) {
	807	+ if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
	808	+ DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
	809	+ dev_priv->vbt.edp_bpp);
	810	+ bpp = dev_priv->vbt.edp_bpp;
	811	+ }
	812	+
	813	+ if (IS_BROADWELL(dev)) {
	814	+ /* Yes, it's an ugly hack. */
	815	+ min_lane_count = max_lane_count;
	816	+ DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
	817	+ min_lane_count);
	818	+ } else if (dev_priv->vbt.edp_lanes) {
	819	+ min_lane_count = min(dev_priv->vbt.edp_lanes,
	820	+ max_lane_count);
	821	+ DRM_DEBUG_KMS("using min %u lanes per VBT\n",
	822	+ min_lane_count);
	823	+ }
	824	+
	825	+ if (dev_priv->vbt.edp_rate) {
	826	+ min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
	827	+ DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
	828	+ bws[min_clock]);
	829	+ }
793	830	}
794	831
795	832	for (; bpp >= 63; bpp -= 23) {
796	833	mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
797	834	bpp);
798	835
799		- for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
800		- for (clock = 0; clock <= max_clock; clock++) {
	836	+ for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
	837	+ for (clock = min_clock; clock <= max_clock; clock++) {
801	838	link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
802	839	link_avail = intel_dp_max_data_rate(link_clock,
803	840	lane_count);
...	...	@@ -387,6 +387,15 @@
387	387	height);
388	388	}
389	389
	390	+ /* No preferred mode marked by the EDID? Are there any modes? */
	391	+ if (!modes[i] && !list_empty(&connector->modes)) {
	392	+ DRM_DEBUG_KMS("using first mode listed on connector %s\n",
	393	+ drm_get_connector_name(connector));
	394	+ modes[i] = list_first_entry(&connector->modes,
	395	+ struct drm_display_mode,
	396	+ head);
	397	+ }
	398	+
390	399	/* last resort: use current mode */
391	400	if (!modes[i]) {
392	401	/*
...	...	@@ -492,6 +492,7 @@
492	492	enum pipe pipe = intel_get_pipe_from_connector(connector);
493	493	u32 freq;
494	494	unsigned long flags;
	495	+ u64 n;
495	496
496	497	if (!panel->backlight.present \|\| pipe == INVALID_PIPE)
497	498	return;
...	...	@@ -502,10 +503,9 @@
502	503
503	504	/* scale to hardware max, but be careful to not overflow */
504	505	freq = panel->backlight.max;
505		- if (freq < max)
506		- level = level * freq / max;
507		- else
508		- level = freq / max * level;
	506	+ n = (u64)level * freq;
	507	+ do_div(n, max);
	508	+ level = n;
509	509
510	510	panel->backlight.level = level;
511	511	if (panel->backlight.device)
...	...	@@ -2095,6 +2095,43 @@
2095	2095	}
2096	2096	}
2097	2097
	2098	+static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
	2099	+ uint16_t wm[5], uint16_t min)
	2100	+{
	2101	+ int level, max_level = ilk_wm_max_level(dev_priv->dev);
	2102	+
	2103	+ if (wm[0] >= min)
	2104	+ return false;
	2105	+
	2106	+ wm[0] = max(wm[0], min);
	2107	+ for (level = 1; level <= max_level; level++)
	2108	+ wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
	2109	+
	2110	+ return true;
	2111	+}
	2112	+
	2113	+static void snb_wm_latency_quirk(struct drm_device *dev)
	2114	+{
	2115	+ struct drm_i915_private *dev_priv = dev->dev_private;
	2116	+ bool changed;
	2117	+
	2118	+ /*
	2119	+ * The BIOS provided WM memory latency values are often
	2120	+ * inadequate for high resolution displays. Adjust them.
	2121	+ */
	2122	+ changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) \|
	2123	+ ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) \|
	2124	+ ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
	2125	+
	2126	+ if (!changed)
	2127	+ return;
	2128	+
	2129	+ DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
	2130	+ intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
	2131	+ intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
	2132	+ intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
	2133	+}
	2134	+
2098	2135	static void ilk_setup_wm_latency(struct drm_device *dev)
2099	2136	{
2100	2137	struct drm_i915_private *dev_priv = dev->dev_private;
...	...	@@ -2112,6 +2149,9 @@
2112	2149	intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2113	2150	intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2114	2151	intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
	2152	+
	2153	+ if (IS_GEN6(dev))
	2154	+ snb_wm_latency_quirk(dev);
2115	2155	}
2116	2156
2117	2157	static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
...	...	@@ -2424,8 +2424,8 @@
2424	2424	if (ret < 0)
2425	2425	goto err1;
2426	2426
2427		- ret = sysfs_create_link(&encoder->ddc.dev.kobj,
2428		- &drm_connector->kdev->kobj,
	2427	+ ret = sysfs_create_link(&drm_connector->kdev->kobj,
	2428	+ &encoder->ddc.dev.kobj,
2429	2429	encoder->ddc.dev.kobj.name);
2430	2430	if (ret < 0)
2431	2431	goto err2;
...	...	@@ -185,6 +185,8 @@
185	185	{
186	186	__raw_i915_write32(dev_priv, FORCEWAKE_VLV,
187	187	_MASKED_BIT_DISABLE(0xffff));
	188	+ __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
	189	+ _MASKED_BIT_DISABLE(0xffff));
188	190	/* something from same cacheline, but !FORCEWAKE_VLV */
189	191	__raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
190	192	}