Eric Lee / smarc-ti-linux-kernel

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Commit a8a658a2f93e75c212e95e9b0778cfa15b3d3417

Authored by LCPD Auto Merger
2 parents 49ab7c8222 cb546a47d3
Exists in smarct4x-processor-sdk-linux-02.00.01 and in 3 other branches processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-02.00.01, smarct4x-800-processor-sdk-linux-02.00.01

Merge branch 'ti-linux-4.1.y' of git.ti.com:ti-linux-kernel/ti-linux-kernel into ti-lsk-linux-4.1.y 

TI-Feature: ti_linux_base_lsk
TI-Tree: git@git.ti.com:ti-linux-kernel/ti-linux-kernel.git
TI-Branch: ti-linux-4.1.y

* 'ti-linux-4.1.y' of git.ti.com:ti-linux-kernel/ti-linux-kernel:
  spi: davinci: use dev_err() for error reporting
  spi: davinci: fix spurious i/o error
  ARM: dts: dra72-evm: Mark uart1 rxd as wakeup capable
  ARM: dts: dra72-evm: We don't support NAND on dra72-evm

Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>

Showing 2 changed files Side-by-side Diff

arch/arm/boot/dts/dra72-evm.dts
Diff comments   View file @ a8a658a
... ... @@ -651,6 +651,8 @@
651 651  
652 652 &uart1 {
653 653 status = "okay";
  654 + interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
  655 + <&dra7_pmx_core 0x3e0>;
654 656 };
655 657  
656 658 &uart3 {
... ... @@ -663,7 +665,12 @@
663 665 };
664 666  
665 667 &gpmc {
666   - status = "okay";
  668 + /*
  669 + * For the existing IOdelay configuration via U-Boot we don't
  670 + * support NAND on dra72-evm. Keep it disabled. Enabling it
  671 + * requires a different configuration by U-Boot.
  672 + */
  673 + status = "disabled";
667 674 ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
668 675 nand@0,0 {
669 676 /* To use NAND, DIP switch SW5 must be set like so:
drivers/spi/spi-davinci.c
Diff comments   View file @ a8a658a
... ... @@ -484,33 +484,33 @@
484 484 struct device *sdev = dspi->bitbang.master->dev.parent;
485 485  
486 486 if (int_status & SPIFLG_TIMEOUT_MASK) {
487   - dev_dbg(sdev, "SPI Time-out Error\n");
  487 + dev_err(sdev, "SPI Time-out Error\n");
488 488 return -ETIMEDOUT;
489 489 }
490 490 if (int_status & SPIFLG_DESYNC_MASK) {
491   - dev_dbg(sdev, "SPI Desynchronization Error\n");
  491 + dev_err(sdev, "SPI Desynchronization Error\n");
492 492 return -EIO;
493 493 }
494 494 if (int_status & SPIFLG_BITERR_MASK) {
495   - dev_dbg(sdev, "SPI Bit error\n");
  495 + dev_err(sdev, "SPI Bit error\n");
496 496 return -EIO;
497 497 }
498 498  
499 499 if (dspi->version == SPI_VERSION_2) {
500 500 if (int_status & SPIFLG_DLEN_ERR_MASK) {
501   - dev_dbg(sdev, "SPI Data Length Error\n");
  501 + dev_err(sdev, "SPI Data Length Error\n");
502 502 return -EIO;
503 503 }
504 504 if (int_status & SPIFLG_PARERR_MASK) {
505   - dev_dbg(sdev, "SPI Parity Error\n");
  505 + dev_err(sdev, "SPI Parity Error\n");
506 506 return -EIO;
507 507 }
508 508 if (int_status & SPIFLG_OVRRUN_MASK) {
509   - dev_dbg(sdev, "SPI Data Overrun error\n");
  509 + dev_err(sdev, "SPI Data Overrun error\n");
510 510 return -EIO;
511 511 }
512 512 if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
513   - dev_dbg(sdev, "SPI Buffer Init Active\n");
  513 + dev_err(sdev, "SPI Buffer Init Active\n");
514 514 return -EBUSY;
515 515 }
516 516 }
... ... @@ -710,7 +710,8 @@
710 710  
711 711 /* Wait for the transfer to complete */
712 712 if (spicfg->io_type != SPI_IO_TYPE_POLL) {
713   - wait_for_completion_interruptible(&(dspi->done));
  713 + if (wait_for_completion_timeout(&dspi->done, HZ) == 0)
  714 + errors = SPIFLG_TIMEOUT_MASK;
714 715 } else {
715 716 while (dspi->rcount > 0 || dspi->wcount > 0) {
716 717 errors = davinci_spi_process_events(dspi);