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Commit b02e7f3ef0beb72da8fc64542f0ac977996ec56b

Authored by Brian Norris
1 parent becd0cb866
Exists in ti-lsk-linux-4.1.y and in 10 other branches dlt-processor-sdk-linux-03.00.00.04, processor-sdk-linux-02.00.01, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04

mtd: spi-nor: re-name OPCODE_* to SPINOR_OP_* 

Qualify these with a better namespace, and prepare them for use in more
drivers.

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Huang Shijie <b32955@freescale.com>

Showing 4 changed files with 90 additions and 90 deletions Side-by-side Diff

drivers/mtd/devices/m25p80.c
Diff comments   View file @ b02e7f3
... ... @@ -86,7 +86,7 @@
86 86  
87 87 spi_message_init(&m);
88 88  
89   - if (nor->program_opcode == OPCODE_AAI_WP && nor->sst_write_second)
  89 + if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
90 90 cmd_sz = 1;
91 91  
92 92 flash->command[0] = nor->program_opcode;
... ... @@ -171,7 +171,7 @@
171 171 return ret;
172 172  
173 173 /* Send write enable, then erase commands. */
174   - ret = nor->write_reg(nor, OPCODE_WREN, NULL, 0, 0);
  174 + ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0);
175 175 if (ret)
176 176 return ret;
177 177  
drivers/mtd/spi-nor/fsl-quadspi.c
Diff comments   View file @ b02e7f3
... ... @@ -294,12 +294,12 @@
294 294 lut_base = SEQID_QUAD_READ * 4;
295 295  
296 296 if (q->nor_size <= SZ_16M) {
297   - cmd = OPCODE_QUAD_READ;
  297 + cmd = SPINOR_OP_QUAD_READ;
298 298 addrlen = ADDR24BIT;
299 299 dummy = 8;
300 300 } else {
301 301 /* use the 4-byte address */
302   - cmd = OPCODE_QUAD_READ;
  302 + cmd = SPINOR_OP_QUAD_READ;
303 303 addrlen = ADDR32BIT;
304 304 dummy = 8;
305 305 }
306 306  
307 307  
... ... @@ -311,17 +311,17 @@
311 311  
312 312 /* Write enable */
313 313 lut_base = SEQID_WREN * 4;
314   - writel(LUT0(CMD, PAD1, OPCODE_WREN), base + QUADSPI_LUT(lut_base));
  314 + writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base));
315 315  
316 316 /* Page Program */
317 317 lut_base = SEQID_PP * 4;
318 318  
319 319 if (q->nor_size <= SZ_16M) {
320   - cmd = OPCODE_PP;
  320 + cmd = SPINOR_OP_PP;
321 321 addrlen = ADDR24BIT;
322 322 } else {
323 323 /* use the 4-byte address */
324   - cmd = OPCODE_PP;
  324 + cmd = SPINOR_OP_PP;
325 325 addrlen = ADDR32BIT;
326 326 }
327 327  
328 328  
329 329  
... ... @@ -331,18 +331,18 @@
331 331  
332 332 /* Read Status */
333 333 lut_base = SEQID_RDSR * 4;
334   - writel(LUT0(CMD, PAD1, OPCODE_RDSR) | LUT1(READ, PAD1, 0x1),
  334 + writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(READ, PAD1, 0x1),
335 335 base + QUADSPI_LUT(lut_base));
336 336  
337 337 /* Erase a sector */
338 338 lut_base = SEQID_SE * 4;
339 339  
340 340 if (q->nor_size <= SZ_16M) {
341   - cmd = OPCODE_SE;
  341 + cmd = SPINOR_OP_SE;
342 342 addrlen = ADDR24BIT;
343 343 } else {
344 344 /* use the 4-byte address */
345   - cmd = OPCODE_SE;
  345 + cmd = SPINOR_OP_SE;
346 346 addrlen = ADDR32BIT;
347 347 }
348 348  
349 349  
350 350  
351 351  
352 352  
353 353  
354 354  
... ... @@ -351,35 +351,35 @@
351 351  
352 352 /* Erase the whole chip */
353 353 lut_base = SEQID_CHIP_ERASE * 4;
354   - writel(LUT0(CMD, PAD1, OPCODE_CHIP_ERASE),
  354 + writel(LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),
355 355 base + QUADSPI_LUT(lut_base));
356 356  
357 357 /* READ ID */
358 358 lut_base = SEQID_RDID * 4;
359   - writel(LUT0(CMD, PAD1, OPCODE_RDID) | LUT1(READ, PAD1, 0x8),
  359 + writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(READ, PAD1, 0x8),
360 360 base + QUADSPI_LUT(lut_base));
361 361  
362 362 /* Write Register */
363 363 lut_base = SEQID_WRSR * 4;
364   - writel(LUT0(CMD, PAD1, OPCODE_WRSR) | LUT1(WRITE, PAD1, 0x2),
  364 + writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(WRITE, PAD1, 0x2),
365 365 base + QUADSPI_LUT(lut_base));
366 366  
367 367 /* Read Configuration Register */
368 368 lut_base = SEQID_RDCR * 4;
369   - writel(LUT0(CMD, PAD1, OPCODE_RDCR) | LUT1(READ, PAD1, 0x1),
  369 + writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(READ, PAD1, 0x1),
370 370 base + QUADSPI_LUT(lut_base));
371 371  
372 372 /* Write disable */
373 373 lut_base = SEQID_WRDI * 4;
374   - writel(LUT0(CMD, PAD1, OPCODE_WRDI), base + QUADSPI_LUT(lut_base));
  374 + writel(LUT0(CMD, PAD1, SPINOR_OP_WRDI), base + QUADSPI_LUT(lut_base));
375 375  
376 376 /* Enter 4 Byte Mode (Micron) */
377 377 lut_base = SEQID_EN4B * 4;
378   - writel(LUT0(CMD, PAD1, OPCODE_EN4B), base + QUADSPI_LUT(lut_base));
  378 + writel(LUT0(CMD, PAD1, SPINOR_OP_EN4B), base + QUADSPI_LUT(lut_base));
379 379  
380 380 /* Enter 4 Byte Mode (Spansion) */
381 381 lut_base = SEQID_BRWR * 4;
382   - writel(LUT0(CMD, PAD1, OPCODE_BRWR), base + QUADSPI_LUT(lut_base));
  382 + writel(LUT0(CMD, PAD1, SPINOR_OP_BRWR), base + QUADSPI_LUT(lut_base));
383 383  
384 384 fsl_qspi_lock_lut(q);
385 385 }
386 386  
387 387  
388 388  
389 389  
390 390  
391 391  
392 392  
393 393  
394 394  
395 395  
396 396  
... ... @@ -388,29 +388,29 @@
388 388 static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
389 389 {
390 390 switch (cmd) {
391   - case OPCODE_QUAD_READ:
  391 + case SPINOR_OP_QUAD_READ:
392 392 return SEQID_QUAD_READ;
393   - case OPCODE_WREN:
  393 + case SPINOR_OP_WREN:
394 394 return SEQID_WREN;
395   - case OPCODE_WRDI:
  395 + case SPINOR_OP_WRDI:
396 396 return SEQID_WRDI;
397   - case OPCODE_RDSR:
  397 + case SPINOR_OP_RDSR:
398 398 return SEQID_RDSR;
399   - case OPCODE_SE:
  399 + case SPINOR_OP_SE:
400 400 return SEQID_SE;
401   - case OPCODE_CHIP_ERASE:
  401 + case SPINOR_OP_CHIP_ERASE:
402 402 return SEQID_CHIP_ERASE;
403   - case OPCODE_PP:
  403 + case SPINOR_OP_PP:
404 404 return SEQID_PP;
405   - case OPCODE_RDID:
  405 + case SPINOR_OP_RDID:
406 406 return SEQID_RDID;
407   - case OPCODE_WRSR:
  407 + case SPINOR_OP_WRSR:
408 408 return SEQID_WRSR;
409   - case OPCODE_RDCR:
  409 + case SPINOR_OP_RDCR:
410 410 return SEQID_RDCR;
411   - case OPCODE_EN4B:
  411 + case SPINOR_OP_EN4B:
412 412 return SEQID_EN4B;
413   - case OPCODE_BRWR:
  413 + case SPINOR_OP_BRWR:
414 414 return SEQID_BRWR;
415 415 default:
416 416 dev_err(q->dev, "Unsupported cmd 0x%.2x\n", cmd);
... ... @@ -688,7 +688,7 @@
688 688 if (ret)
689 689 return ret;
690 690  
691   - if (opcode == OPCODE_CHIP_ERASE)
  691 + if (opcode == SPINOR_OP_CHIP_ERASE)
692 692 fsl_qspi_invalid(q);
693 693  
694 694 } else if (len > 0) {
... ... @@ -750,7 +750,7 @@
750 750 return ret;
751 751  
752 752 /* Send write enable, then erase commands. */
753   - ret = nor->write_reg(nor, OPCODE_WREN, NULL, 0, 0);
  753 + ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0);
754 754 if (ret)
755 755 return ret;
756 756  
drivers/mtd/spi-nor/spi-nor.c
Diff comments   View file @ b02e7f3
... ... @@ -38,7 +38,7 @@
38 38 int ret;
39 39 u8 val;
40 40  
41   - ret = nor->read_reg(nor, OPCODE_RDSR, &val, 1);
  41 + ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
42 42 if (ret < 0) {
43 43 pr_err("error %d reading SR\n", (int) ret);
44 44 return ret;
... ... @@ -57,7 +57,7 @@
57 57 int ret;
58 58 u8 val;
59 59  
60   - ret = nor->read_reg(nor, OPCODE_RDCR, &val, 1);
  60 + ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
61 61 if (ret < 0) {
62 62 dev_err(nor->dev, "error %d reading CR\n", ret);
63 63 return ret;
... ... @@ -91,7 +91,7 @@
91 91 static inline int write_sr(struct spi_nor *nor, u8 val)
92 92 {
93 93 nor->cmd_buf[0] = val;
94   - return nor->write_reg(nor, OPCODE_WRSR, nor->cmd_buf, 1, 0);
  94 + return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
95 95 }
96 96  
97 97 /*
... ... @@ -100,7 +100,7 @@
100 100 */
101 101 static inline int write_enable(struct spi_nor *nor)
102 102 {
103   - return nor->write_reg(nor, OPCODE_WREN, NULL, 0, 0);
  103 + return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0);
104 104 }
105 105  
106 106 /*
... ... @@ -108,7 +108,7 @@
108 108 */
109 109 static inline int write_disable(struct spi_nor *nor)
110 110 {
111   - return nor->write_reg(nor, OPCODE_WRDI, NULL, 0, 0);
  111 + return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0, 0);
112 112 }
113 113  
114 114 static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
... ... @@ -132,7 +132,7 @@
132 132 if (need_wren)
133 133 write_enable(nor);
134 134  
135   - cmd = enable ? OPCODE_EN4B : OPCODE_EX4B;
  135 + cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
136 136 status = nor->write_reg(nor, cmd, NULL, 0, 0);
137 137 if (need_wren)
138 138 write_disable(nor);
... ... @@ -141,7 +141,7 @@
141 141 default:
142 142 /* Spansion style */
143 143 nor->cmd_buf[0] = enable << 7;
144   - return nor->write_reg(nor, OPCODE_BRWR, nor->cmd_buf, 1, 0);
  144 + return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1, 0);
145 145 }
146 146 }
147 147  
... ... @@ -193,7 +193,7 @@
193 193 /* Send write enable, then erase commands. */
194 194 write_enable(nor);
195 195  
196   - return nor->write_reg(nor, OPCODE_CHIP_ERASE, NULL, 0, 0);
  196 + return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0, 0);
197 197 }
198 198  
199 199 static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
... ... @@ -253,7 +253,7 @@
253 253 }
254 254  
255 255 /* REVISIT in some cases we could speed up erasing large regions
256   - * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up
  256 + * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
257 257 * to use "small sector erase", but that's not always optimal.
258 258 */
259 259  
... ... @@ -385,7 +385,7 @@
385 385 u32 jedec_id;
386 386 u16 ext_id;
387 387  
388   - /* The size listed here is what works with OPCODE_SE, which isn't
  388 + /* The size listed here is what works with SPINOR_OP_SE, which isn't
389 389 * necessarily called a "sector" by the vendor.
390 390 */
391 391 unsigned sector_size;
392 392  
... ... @@ -395,11 +395,11 @@
395 395 u16 addr_width;
396 396  
397 397 u16 flags;
398   -#define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */
  398 +#define SECT_4K 0x01 /* SPINOR_OP_BE_4K works uniformly */
399 399 #define SPI_NOR_NO_ERASE 0x02 /* No erase command needed */
400 400 #define SST_WRITE 0x04 /* use SST byte programming */
401 401 #define SPI_NOR_NO_FR 0x08 /* Can't do fastread */
402   -#define SECT_4K_PMC 0x10 /* OPCODE_BE_4K_PMC works uniformly */
  402 +#define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */
403 403 #define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */
404 404 #define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */
405 405 };
... ... @@ -598,7 +598,7 @@
598 598 u16 ext_jedec;
599 599 struct flash_info *info;
600 600  
601   - tmp = nor->read_reg(nor, OPCODE_RDID, id, 5);
  601 + tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, 5);
602 602 if (tmp < 0) {
603 603 dev_dbg(nor->dev, " error %d reading JEDEC ID\n", tmp);
604 604 return ERR_PTR(tmp);
... ... @@ -670,7 +670,7 @@
670 670 actual = to % 2;
671 671 /* Start write from odd address. */
672 672 if (actual) {
673   - nor->program_opcode = OPCODE_BP;
  673 + nor->program_opcode = SPINOR_OP_BP;
674 674  
675 675 /* write one byte. */
676 676 nor->write(nor, to, 1, retlen, buf);
... ... @@ -682,7 +682,7 @@
682 682  
683 683 /* Write out most of the data here. */
684 684 for (; actual < len - 1; actual += 2) {
685   - nor->program_opcode = OPCODE_AAI_WP;
  685 + nor->program_opcode = SPINOR_OP_AAI_WP;
686 686  
687 687 /* write two bytes. */
688 688 nor->write(nor, to, 2, retlen, buf + actual);
... ... @@ -703,7 +703,7 @@
703 703 if (actual != len) {
704 704 write_enable(nor);
705 705  
706   - nor->program_opcode = OPCODE_BP;
  706 + nor->program_opcode = SPINOR_OP_BP;
707 707 nor->write(nor, to, 1, retlen, buf + actual);
708 708  
709 709 ret = wait_till_ready(nor);
... ... @@ -777,7 +777,7 @@
777 777 write_enable(nor);
778 778  
779 779 nor->cmd_buf[0] = val | SR_QUAD_EN_MX;
780   - nor->write_reg(nor, OPCODE_WRSR, nor->cmd_buf, 1, 0);
  780 + nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
781 781  
782 782 if (wait_till_ready(nor))
783 783 return 1;
... ... @@ -802,7 +802,7 @@
802 802 nor->cmd_buf[0] = val & 0xff;
803 803 nor->cmd_buf[1] = (val >> 8);
804 804  
805   - return nor->write_reg(nor, OPCODE_WRSR, nor->cmd_buf, 2, 0);
  805 + return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2, 0);
806 806 }
807 807  
808 808 static int spansion_quad_enable(struct spi_nor *nor)
809 809  
810 810  
... ... @@ -967,13 +967,13 @@
967 967  
968 968 /* prefer "small sector" erase if possible */
969 969 if (info->flags & SECT_4K) {
970   - nor->erase_opcode = OPCODE_BE_4K;
  970 + nor->erase_opcode = SPINOR_OP_BE_4K;
971 971 mtd->erasesize = 4096;
972 972 } else if (info->flags & SECT_4K_PMC) {
973   - nor->erase_opcode = OPCODE_BE_4K_PMC;
  973 + nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
974 974 mtd->erasesize = 4096;
975 975 } else {
976   - nor->erase_opcode = OPCODE_SE;
  976 + nor->erase_opcode = SPINOR_OP_SE;
977 977 mtd->erasesize = info->sector_size;
978 978 }
979 979  
980 980  
981 981  
982 982  
983 983  
... ... @@ -1014,23 +1014,23 @@
1014 1014 /* Default commands */
1015 1015 switch (nor->flash_read) {
1016 1016 case SPI_NOR_QUAD:
1017   - nor->read_opcode = OPCODE_QUAD_READ;
  1017 + nor->read_opcode = SPINOR_OP_QUAD_READ;
1018 1018 break;
1019 1019 case SPI_NOR_DUAL:
1020   - nor->read_opcode = OPCODE_DUAL_READ;
  1020 + nor->read_opcode = SPINOR_OP_DUAL_READ;
1021 1021 break;
1022 1022 case SPI_NOR_FAST:
1023   - nor->read_opcode = OPCODE_FAST_READ;
  1023 + nor->read_opcode = SPINOR_OP_FAST_READ;
1024 1024 break;
1025 1025 case SPI_NOR_NORMAL:
1026   - nor->read_opcode = OPCODE_NORM_READ;
  1026 + nor->read_opcode = SPINOR_OP_NORM_READ;
1027 1027 break;
1028 1028 default:
1029 1029 dev_err(dev, "No Read opcode defined\n");
1030 1030 return -EINVAL;
1031 1031 }
1032 1032  
1033   - nor->program_opcode = OPCODE_PP;
  1033 + nor->program_opcode = SPINOR_OP_PP;
1034 1034  
1035 1035 if (info->addr_width)
1036 1036 nor->addr_width = info->addr_width;
1037 1037  
1038 1038  
1039 1039  
1040 1040  
1041 1041  
... ... @@ -1041,21 +1041,21 @@
1041 1041 /* Dedicated 4-byte command set */
1042 1042 switch (nor->flash_read) {
1043 1043 case SPI_NOR_QUAD:
1044   - nor->read_opcode = OPCODE_QUAD_READ_4B;
  1044 + nor->read_opcode = SPINOR_OP_QUAD_READ_4B;
1045 1045 break;
1046 1046 case SPI_NOR_DUAL:
1047   - nor->read_opcode = OPCODE_DUAL_READ_4B;
  1047 + nor->read_opcode = SPINOR_OP_DUAL_READ_4B;
1048 1048 break;
1049 1049 case SPI_NOR_FAST:
1050   - nor->read_opcode = OPCODE_FAST_READ_4B;
  1050 + nor->read_opcode = SPINOR_OP_FAST_READ_4B;
1051 1051 break;
1052 1052 case SPI_NOR_NORMAL:
1053   - nor->read_opcode = OPCODE_NORM_READ_4B;
  1053 + nor->read_opcode = SPINOR_OP_NORM_READ_4B;
1054 1054 break;
1055 1055 }
1056   - nor->program_opcode = OPCODE_PP_4B;
  1056 + nor->program_opcode = SPINOR_OP_PP_4B;
1057 1057 /* No small sector erase for 4-byte command set */
1058   - nor->erase_opcode = OPCODE_SE_4B;
  1058 + nor->erase_opcode = SPINOR_OP_SE_4B;
1059 1059 mtd->erasesize = info->sector_size;
1060 1060 } else
1061 1061 set_4byte(nor, info->jedec_id, 1);
include/linux/mtd/spi-nor.h
Diff comments   View file @ b02e7f3
... ... @@ -11,41 +11,41 @@
11 11 #define __LINUX_MTD_SPI_NOR_H
12 12  
13 13 /* Flash opcodes. */
14   -#define OPCODE_WREN 0x06 /* Write enable */
15   -#define OPCODE_RDSR 0x05 /* Read status register */
16   -#define OPCODE_WRSR 0x01 /* Write status register 1 byte */
17   -#define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */
18   -#define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */
19   -#define OPCODE_DUAL_READ 0x3b /* Read data bytes (Dual SPI) */
20   -#define OPCODE_QUAD_READ 0x6b /* Read data bytes (Quad SPI) */
21   -#define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */
22   -#define OPCODE_BE_4K 0x20 /* Erase 4KiB block */
23   -#define OPCODE_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
24   -#define OPCODE_BE_32K 0x52 /* Erase 32KiB block */
25   -#define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */
26   -#define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */
27   -#define OPCODE_RDID 0x9f /* Read JEDEC ID */
28   -#define OPCODE_RDCR 0x35 /* Read configuration register */
  14 +#define SPINOR_OP_WREN 0x06 /* Write enable */
  15 +#define SPINOR_OP_RDSR 0x05 /* Read status register */
  16 +#define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
  17 +#define SPINOR_OP_NORM_READ 0x03 /* Read data bytes (low frequency) */
  18 +#define SPINOR_OP_FAST_READ 0x0b /* Read data bytes (high frequency) */
  19 +#define SPINOR_OP_DUAL_READ 0x3b /* Read data bytes (Dual SPI) */
  20 +#define SPINOR_OP_QUAD_READ 0x6b /* Read data bytes (Quad SPI) */
  21 +#define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
  22 +#define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
  23 +#define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
  24 +#define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
  25 +#define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
  26 +#define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
  27 +#define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
  28 +#define SPINOR_OP_RDCR 0x35 /* Read configuration register */
29 29  
30 30 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
31   -#define OPCODE_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */
32   -#define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */
33   -#define OPCODE_DUAL_READ_4B 0x3c /* Read data bytes (Dual SPI) */
34   -#define OPCODE_QUAD_READ_4B 0x6c /* Read data bytes (Quad SPI) */
35   -#define OPCODE_PP_4B 0x12 /* Page program (up to 256 bytes) */
36   -#define OPCODE_SE_4B 0xdc /* Sector erase (usually 64KiB) */
  31 +#define SPINOR_OP_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */
  32 +#define SPINOR_OP_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */
  33 +#define SPINOR_OP_DUAL_READ_4B 0x3c /* Read data bytes (Dual SPI) */
  34 +#define SPINOR_OP_QUAD_READ_4B 0x6c /* Read data bytes (Quad SPI) */
  35 +#define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
  36 +#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
37 37  
38 38 /* Used for SST flashes only. */
39   -#define OPCODE_BP 0x02 /* Byte program */
40   -#define OPCODE_WRDI 0x04 /* Write disable */
41   -#define OPCODE_AAI_WP 0xad /* Auto address increment word program */
  39 +#define SPINOR_OP_BP 0x02 /* Byte program */
  40 +#define SPINOR_OP_WRDI 0x04 /* Write disable */
  41 +#define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
42 42  
43 43 /* Used for Macronix and Winbond flashes. */
44   -#define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */
45   -#define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */
  44 +#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
  45 +#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
46 46  
47 47 /* Used for Spansion flashes only. */
48   -#define OPCODE_BRWR 0x17 /* Bank register write */
  48 +#define SPINOR_OP_BRWR 0x17 /* Bank register write */
49 49  
50 50 /* Status Register bits. */
51 51 #define SR_WIP 1 /* Write in progress */