mei: clean reset bit before reset

H_RST bit in H_CSR register may be found lit before reset is started, for example if preceding reset flow hasn't completed. In that case asserting H_RST will be ignored, therefore we need to clean H_RST bit to start a successful reset sequence. Cc: <stable@vger.kernel.org> #3.10+ Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

mei: clean reset bit before reset
H_RST bit in H_CSR register may be found lit before reset is started, for example if preceding reset flow hasn't completed. In that case asserting H_RST will be ignored, therefore we need to clean H_RST bit to start a successful reset sequence. Cc: <stable@vger.kernel.org> #3.10+ Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Alexander Usyskin · Greg Kroah-Hartman · Eric Lee · Eric Lee · Eric Lee · Eric Lee
1 parent b7392d2247
Showing 1 changed file with 12 additions and 0 deletions Side-by-side Diff
drivers/misc/mei/hw-me.c
@@ -234,6 +234,18 @@
 	struct mei_me_hw *hw = to_me_hw(dev);
 	u32 hcsr = mei_hcsr_read(hw);
  
+	/* H_RST may be found lit before reset is started,
+	 * for example if preceding reset flow hasn't completed.
+	 * In that case asserting H_RST will be ignored, therefore
+	 * we need to clean H_RST bit to start a successful reset sequence.
+	 */
+	if ((hcsr & H_RST) == H_RST) {
+		dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr);
+		hcsr &= ~H_RST;
+		mei_me_reg_write(hw, H_CSR, hcsr);
+		hcsr = mei_hcsr_read(hw);
+	}
+
 	hcsr |= H_RST | H_IG | H_IS;
  
 	if (intr_enable)
...	...	@@ -234,6 +234,18 @@
234	234	struct mei_me_hw *hw = to_me_hw(dev);
235	235	u32 hcsr = mei_hcsr_read(hw);
236	236
	237	+ /* H_RST may be found lit before reset is started,
	238	+ * for example if preceding reset flow hasn't completed.
	239	+ * In that case asserting H_RST will be ignored, therefore
	240	+ * we need to clean H_RST bit to start a successful reset sequence.
	241	+ */
	242	+ if ((hcsr & H_RST) == H_RST) {
	243	+ dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr);
	244	+ hcsr &= ~H_RST;
	245	+ mei_me_reg_write(hw, H_CSR, hcsr);
	246	+ hcsr = mei_hcsr_read(hw);
	247	+ }
	248	+
237	249	hcsr \|= H_RST \| H_IG \| H_IS;
238	250
239	251	if (intr_enable)