Commit b79055952badbd73710685643bab44104f2509ea
Committed by
Jason Cooper
Jason Cooper
1 parent
2b28037632
Exists in
ti-lsk-linux-4.1.y
and in
10 other branches
genirq: Generic chip: Add big endian I/O accessors
Use io{read,write}32be if the caller specified IRQ_GC_BE_IO when creating
the irqchip.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Acked-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lkml.kernel.org/r/1415342669-30640-5-git-send-email-cernekee@gmail.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Showing 2 changed files with 18 additions and 0 deletions Side-by-side Diff
include/linux/irq.h
| ... | ... | @@ -738,12 +738,14 @@ |
| 738 | 738 | * the parent irq. Usually GPIO implementations |
| 739 | 739 | * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private |
| 740 | 740 | * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask |
| 741 | + * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE) | |
| 741 | 742 | */ |
| 742 | 743 | enum irq_gc_flags { |
| 743 | 744 | IRQ_GC_INIT_MASK_CACHE = 1 << 0, |
| 744 | 745 | IRQ_GC_INIT_NESTED_LOCK = 1 << 1, |
| 745 | 746 | IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2, |
| 746 | 747 | IRQ_GC_NO_MASK = 1 << 3, |
| 748 | + IRQ_GC_BE_IO = 1 << 4, | |
| 747 | 749 | }; |
| 748 | 750 | |
| 749 | 751 | /* |
kernel/irq/generic-chip.c
| ... | ... | @@ -191,6 +191,16 @@ |
| 191 | 191 | return 0; |
| 192 | 192 | } |
| 193 | 193 | |
| 194 | +static u32 irq_readl_be(void __iomem *addr) | |
| 195 | +{ | |
| 196 | + return ioread32be(addr); | |
| 197 | +} | |
| 198 | + | |
| 199 | +static void irq_writel_be(u32 val, void __iomem *addr) | |
| 200 | +{ | |
| 201 | + iowrite32be(val, addr); | |
| 202 | +} | |
| 203 | + | |
| 194 | 204 | static void |
| 195 | 205 | irq_init_generic_chip(struct irq_chip_generic *gc, const char *name, |
| 196 | 206 | int num_ct, unsigned int irq_base, |
| 197 | 207 | |
| ... | ... | @@ -300,7 +310,13 @@ |
| 300 | 310 | dgc->gc[i] = gc = tmp; |
| 301 | 311 | irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip, |
| 302 | 312 | NULL, handler); |
| 313 | + | |
| 303 | 314 | gc->domain = d; |
| 315 | + if (gcflags & IRQ_GC_BE_IO) { | |
| 316 | + gc->reg_readl = &irq_readl_be; | |
| 317 | + gc->reg_writel = &irq_writel_be; | |
| 318 | + } | |
| 319 | + | |
| 304 | 320 | raw_spin_lock_irqsave(&gc_lock, flags); |
| 305 | 321 | list_add_tail(&gc->list, &gc_list); |
| 306 | 322 | raw_spin_unlock_irqrestore(&gc_lock, flags); |