Eric Lee / smarc-ti-linux-kernel

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Commit bda4d986a6a42710b971d5e3780fe22dce7e6afc

Authored by Markos Chandras
Committed by Ralf Baechle
1 parent 5bc05971d3
Exists in master and in 13 other branches dlt-processor-sdk-linux-03.00.00.04, processor-sdk-linux-02.00.01, smarc-ti-linux-3.15.y, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04, ti-linux-3.15.y, ti-lsk-linux-4.1.y

MIPS: lib: memcpy: Split source and destination prefetch macros 

In preparation for EVA support, the PREF macro is split into two
separate macros, PREFS and PREFD, for source and destination data
prefetching respectively.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>

Showing 1 changed file with 22 additions and 14 deletions Side-by-side Diff

arch/mips/lib/memcpy.S
Diff comments   View file @ bda4d98
... ... @@ -89,6 +89,9 @@
89 89 /* Instruction type */
90 90 #define LD_INSN 1
91 91 #define ST_INSN 2
  92 +/* Pretech type */
  93 +#define SRC_PREFETCH 1
  94 +#define DST_PREFETCH 2
92 95  
93 96 /*
94 97 * Wrapper to add an entry in the exception table
... ... @@ -174,6 +177,11 @@
174 177 #define LOADB(reg, addr, handler) EXC(lb, LD_INSN, reg, addr, handler)
175 178 #define STOREB(reg, addr, handler) EXC(sb, ST_INSN, reg, addr, handler)
176 179  
  180 +#define _PREF(hint, addr, type) PREF(hint, addr)
  181 +
  182 +#define PREFS(hint, addr) _PREF(hint, addr, SRC_PREFETCH)
  183 +#define PREFD(hint, addr) _PREF(hint, addr, DST_PREFETCH)
  184 +
177 185 #ifdef CONFIG_CPU_LITTLE_ENDIAN
178 186 #define LDFIRST LOADR
179 187 #define LDREST LOADL
180 188  
181 189  
... ... @@ -237,16 +245,16 @@
237 245 *
238 246 * If len < NBYTES use byte operations.
239 247 */
240   - PREF( 0, 0(src) )
241   - PREF( 1, 0(dst) )
  248 + PREFS( 0, 0(src) )
  249 + PREFD( 1, 0(dst) )
242 250 sltu t2, len, NBYTES
243 251 and t1, dst, ADDRMASK
244   - PREF( 0, 1*32(src) )
245   - PREF( 1, 1*32(dst) )
  252 + PREFS( 0, 1*32(src) )
  253 + PREFD( 1, 1*32(dst) )
246 254 bnez t2, .Lcopy_bytes_checklen
247 255 and t0, src, ADDRMASK
248   - PREF( 0, 2*32(src) )
249   - PREF( 1, 2*32(dst) )
  256 + PREFS( 0, 2*32(src) )
  257 + PREFD( 1, 2*32(dst) )
250 258 bnez t1, .Ldst_unaligned
251 259 nop
252 260 bnez t0, .Lsrc_unaligned_dst_aligned
... ... @@ -258,8 +266,8 @@
258 266 SRL t0, len, LOG_NBYTES+3 # +3 for 8 units/iter
259 267 beqz t0, .Lcleanup_both_aligned # len < 8*NBYTES
260 268 and rem, len, (8*NBYTES-1) # rem = len % (8*NBYTES)
261   - PREF( 0, 3*32(src) )
262   - PREF( 1, 3*32(dst) )
  269 + PREFS( 0, 3*32(src) )
  270 + PREFD( 1, 3*32(dst) )
263 271 .align 4
264 272 1:
265 273 R10KCBARRIER(0(ra))
... ... @@ -282,8 +290,8 @@
282 290 STORE(t7, UNIT(-3)(dst), .Ls_exc_p3u)
283 291 STORE(t0, UNIT(-2)(dst), .Ls_exc_p2u)
284 292 STORE(t1, UNIT(-1)(dst), .Ls_exc_p1u)
285   - PREF( 0, 8*32(src) )
286   - PREF( 1, 8*32(dst) )
  293 + PREFS( 0, 8*32(src) )
  294 + PREFD( 1, 8*32(dst) )
287 295 bne len, rem, 1b
288 296 nop
289 297  
290 298  
... ... @@ -378,10 +386,10 @@
378 386  
379 387 .Lsrc_unaligned_dst_aligned:
380 388 SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter
381   - PREF( 0, 3*32(src) )
  389 + PREFS( 0, 3*32(src) )
382 390 beqz t0, .Lcleanup_src_unaligned
383 391 and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES
384   - PREF( 1, 3*32(dst) )
  392 + PREFD( 1, 3*32(dst) )
385 393 1:
386 394 /*
387 395 * Avoid consecutive LD*'s to the same register since some mips
... ... @@ -399,7 +407,7 @@
399 407 LDFIRST(t3, FIRST(3)(src), .Ll_exc_copy)
400 408 LDREST(t2, REST(2)(src), .Ll_exc_copy)
401 409 LDREST(t3, REST(3)(src), .Ll_exc_copy)
402   - PREF( 0, 9*32(src) ) # 0 is PREF_LOAD (not streamed)
  410 + PREFS( 0, 9*32(src) ) # 0 is PREF_LOAD (not streamed)
403 411 ADD src, src, 4*NBYTES
404 412 #ifdef CONFIG_CPU_SB1
405 413 nop # improves slotting
... ... @@ -408,7 +416,7 @@
408 416 STORE(t1, UNIT(1)(dst), .Ls_exc_p3u)
409 417 STORE(t2, UNIT(2)(dst), .Ls_exc_p2u)
410 418 STORE(t3, UNIT(3)(dst), .Ls_exc_p1u)
411   - PREF( 1, 9*32(dst) ) # 1 is PREF_STORE (not streamed)
  419 + PREFD( 1, 9*32(dst) ) # 1 is PREF_STORE (not streamed)
412 420 .set reorder /* DADDI_WAR */
413 421 ADD dst, dst, 4*NBYTES
414 422 bne len, rem, 1b