Eric Lee / smarc-ti-linux-kernel

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Commit bf038227a01263dc29fa7053e600ec5a939d0bbd

Authored by Xishi Qiu
Committed by Jiri Kosina
1 parent 0d7a0a8a74
Exists in master and in 16 other branches dlt-processor-sdk-linux-03.00.00.04, processor-sdk-linux-01.00.00, processor-sdk-linux-02.00.01, smarc-ti-linux-3.14.y, smarc-ti-linux-3.15.y, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04, ti-linux-3.14.y, ti-linux-3.15.y, ti-lsk-linux-4.1.y

doc: Documentation/DMA-attributes.txt fix typo 

Fix some typos in Documentation/DMA-attributes.txt.

Signed-off-by: Xishi Qiu <qiuxishi@huawei.com>
Acked-by: Rob Landley <rob@landley.net>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>

Showing 1 changed file with 3 additions and 3 deletions Side-by-side Diff

Documentation/DMA-attributes.txt
Diff comments   View file @ bf03822
... ... @@ -13,7 +13,7 @@
13 13 strictly order DMA from a device across all intervening busses and
14 14 bridges. This barrier is not specific to a particular type of
15 15 interconnect, it applies to the system as a whole, and so its
16   -implementation must account for the idiosyncracies of the system all
  16 +implementation must account for the idiosyncrasies of the system all
17 17 the way from the DMA device to memory.
18 18  
19 19 As an example of a situation where DMA_ATTR_WRITE_BARRIER would be
... ... @@ -60,7 +60,7 @@
60 60 Buffers allocated with this attribute can be only passed to user space
61 61 by calling dma_mmap_attrs(). By using this API, you are guaranteeing
62 62 that you won't dereference the pointer returned by dma_alloc_attr(). You
63   -can threat it as a cookie that must be passed to dma_mmap_attrs() and
  63 +can treat it as a cookie that must be passed to dma_mmap_attrs() and
64 64 dma_free_attrs(). Make sure that both of these also get this attribute
65 65 set on each call.
66 66  
... ... @@ -82,7 +82,7 @@
82 82 (usually it means that the cache has been flushed or invalidated
83 83 depending on the dma direction). However, next calls to
84 84 dma_map_{single,page,sg}() for other devices will perform exactly the
85   -same sychronization operation on the CPU cache. CPU cache sychronization
  85 +same synchronization operation on the CPU cache. CPU cache synchronization
86 86 might be a time consuming operation, especially if the buffers are
87 87 large, so it is highly recommended to avoid it if possible.
88 88 DMA_ATTR_SKIP_CPU_SYNC allows platform code to skip synchronization of