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Commit c62ac500008b9cd98a4a4288cdfe92e87d5a4237

Authored by Murali Karicheri
Committed by Kishon Vijay Abraham I
1 parent 2b681b1619
Exists in smarct4x-processor-sdk-linux-02.00.01 and in 3 other branches processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-02.00.01, smarct4x-800-processor-sdk-linux-02.00.01

phy: keystone: remove comments per vendor recommendation 

Vendor has recommended to remove all comments from the driver code.
This patch updates the code for the same.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>

Showing 1 changed file with 3 additions and 148 deletions Side-by-side Diff

drivers/phy/phy-keystone-serdes.c
Diff comments   View file @ c62ac50
... ... @@ -60,9 +60,6 @@
60 60 #include <linux/phy/phy.h>
61 61 #include <linux/platform_device.h>
62 62  
63   -/*
64   - * Keystone2 SERDES registers
65   - */
66 63 #define KSERDES_SS_OFFSET 0x1fc0
67 64 #define MOD_VER_REG (KSERDES_SS_OFFSET + 0x00)
68 65 #define MEM_ADR_REG (KSERDES_SS_OFFSET + 0x04)
... ... @@ -86,9 +83,6 @@
86 83 #define CMU1_SS_OFFSET 0x0c00
87 84 #define CMU1_REG(x) (CMU1_SS_OFFSET + x)
88 85  
89   -/*
90   - * XGE PCS-R registers
91   - */
92 86 #define PCSR_OFFSET(x) (x * 0x80)
93 87  
94 88 #define PCSR_TX_CTL(x) (PCSR_OFFSET(x) + 0x00)
95 89  
... ... @@ -102,17 +96,9 @@
102 96 #define reg_rmw(addr, value, mask) \
103 97 writel(((readl(addr) & (~(mask))) | (value & (mask))), (addr))
104 98  
105   -/*
106   - * Replaces bit field [msb:lsb] in register located
107   - * at (base + offset) by val
108   - */
109 99 #define FINSR(base, offset, msb, lsb, val) \
110 100 reg_rmw((base) + (offset), ((val) << (lsb)), GENMASK((msb), (lsb)))
111 101  
112   -/*
113   - * This version of FEXTR is NOT safe for msb = 31, lsb = 0
114   - * but then why would we need FEXTR for that case.
115   - */
116 102 #define FEXTR(val, msb, lsb) \
117 103 (((val) >> (lsb)) & ((1 << ((msb) - (lsb) + 1)) - 1))
118 104  
119 105  
... ... @@ -127,11 +113,9 @@
127 113 #define MAX_COMPARATORS 5
128 114 #define OFFSET_SAMPLES 100
129 115  
130   -/* yes comparator starts from 1 */
131 116 #define for_each_comparator(i) \
132 117 for (i = 1; i < MAX_COMPARATORS; i++)
133 118  
134   -/* CPU CTRL bits */
135 119 #define CPU_EN BIT(31)
136 120 #define CPU_GO BIT(30)
137 121 #define POR_EN BIT(29)
138 122  
... ... @@ -153,12 +137,10 @@
153 137  
154 138 #define SERDES_REG_INDEX 0
155 139  
156   -/* SERDES internal memory */
157 140 #define KSERDES_XFW_MEM_SIZE SZ_64K
158 141 #define KSERDES_XFW_CONFIG_MEM_SIZE SZ_64
159 142 #define KSERDES_XFW_NUM_PARAMS 5
160 143  
161   -/* Last 64B of the 64KB internal mem is for parameters */
162 144 #define KSERDES_XFW_CONFIG_START_ADDR \
163 145 (KSERDES_XFW_MEM_SIZE - KSERDES_XFW_CONFIG_MEM_SIZE)
164 146  
... ... @@ -174,7 +156,6 @@
174 156 static const char * const ks2_xgbe_serdes_firmwares[] = {"ks2_xgbe_serdes.bin"};
175 157 static const char * const ks2_pcie_serdes_firmwares[] = {"ks2_pcie_serdes.bin"};
176 158  
177   -/* SERDES Link Rate Kbps */
178 159 enum kserdes_link_rate {
179 160 KSERDES_LINK_RATE_1P25G = 1250000,
180 161 KSERDES_LINK_RATE_3P125G = 3125000,
... ... @@ -189,7 +170,6 @@
189 170 KSERDES_LINK_RATE_12P5G = 12500000,
190 171 };
191 172  
192   -/* SERDES Lane Control Rate */
193 173 enum kserdes_lane_ctrl_rate {
194 174 KSERDES_FULL_RATE,
195 175 KSERDES_HALF_RATE,
196 176  
... ... @@ -245,14 +225,12 @@
245 225 void __iomem *regs;
246 226 struct regmap *peripheral_regmap;
247 227 struct regmap *pcsr_regmap;
248   - /* non-fw specific */
249 228 const char *init_fw;
250 229 struct serdes_cfg *init_cfg;
251 230 int init_cfg_len;
252 231 enum kserdes_link_rate link_rate;
253 232 bool rx_force_enable;
254 233 struct kserdes_lane_config lane[KSERDES_MAX_LANES];
255   - /* fw specific */
256 234 bool firmware;
257 235 struct kserdes_fw_config fw;
258 236 };
259 237  
... ... @@ -398,9 +376,7 @@
398 376  
399 377 static u32 _kserdes_read_select_tbus(void __iomem *sregs, int select, int ofs)
400 378 {
401   - /* set tbus address */
402 379 _kserdes_write_tbus_addr(sregs, select, ofs);
403   - /* get tbus value */
404 380 return _kserdes_read_tbus_val(sregs);
405 381 }
406 382  
407 383  
... ... @@ -445,10 +421,8 @@
445 421 for_each_enable_lane(sc, lane)
446 422 kserdes_cdfe_enable(sc, lane);
447 423  
448   - /* setting initial rx */
449 424 FINSR(sc->regs, CML_REG(0x108), 23, 16, 0x04);
450 425  
451   - /* setting rx */
452 426 FINSR(sc->regs, CML_REG(0xbc), 28, 24, 0x0);
453 427  
454 428 for_each_lane(sc, lane)
455 429  
... ... @@ -457,10 +431,8 @@
457 431  
458 432 static inline void kserdes_set_lane_starts(struct kserdes_config *sc, u32 lane)
459 433 {
460   - /* att start -1 for short channel */
461 434 FINSR(sc->regs, LANEX_REG(lane, 0x8c), 11, 8,
462 435 sc->lane[lane].rx_start.att);
463   - /* boost start -3 for short channel */
464 436 FINSR(sc->regs, LANEX_REG(lane, 0x8c), 15, 12,
465 437 sc->lane[lane].rx_start.boost);
466 438 }
... ... @@ -473,7 +445,6 @@
473 445 kserdes_phyb_cfg(sc);
474 446 }
475 447  
476   - /* Set ATT and BOOST start values for each lane */
477 448 for_each_enable_lane(sc, lane)
478 449 kserdes_set_lane_starts(sc, lane);
479 450 }
... ... @@ -482,7 +453,6 @@
482 453 {
483 454 u32 val_0, val_1, val;
484 455  
485   - /* Assert Reset while preserving control bits */
486 456 val_0 = _kserdes_read_select_tbus(sc->regs, lane + 1, 0);
487 457  
488 458 val_1 = _kserdes_read_select_tbus(sc->regs, lane + 1, 1);
... ... @@ -494,7 +464,6 @@
494 464 val |= (1 << 14);
495 465 val &= ~0x60;
496 466  
497   - /* Only modify the reset bit and the overlay bit */
498 467 FINSR(sc->regs, LANEX_REG(lane, 0x028), 29, 15, val);
499 468 }
500 469  
... ... @@ -515,7 +484,6 @@
515 484 cm = sc->lane[lane].tx_coeff.cm;
516 485  
517 486 if (sc->phy_type == KSERDES_PHY_XGE) {
518   - /* TX Control override enable */
519 487 FINSR(sc->regs, LANEX_REG(lane, 0x8), 11, 8, (cm & 0xf));
520 488 FINSR(sc->regs, LANEX_REG(lane, 0x8), 4, 0, (c1 & 0x1f));
521 489 FINSR(sc->regs, LANEX_REG(lane, 0x8), 7, 5, (c2 & 0x7));
522 490  
523 491  
524 492  
... ... @@ -558,14 +526,10 @@
558 526 struct kserdes_tx_coeff *tc = &sc->lane[lane].tx_coeff;
559 527  
560 528 if (sc->phy_type == KSERDES_PHY_XGE) {
561   - /* Tx Swing */
562 529 FINSR(sc->regs, LANEX_REG(lane, 0x004), 29, 26, tc->att);
563   - /* Regulator voltage */
564 530 FINSR(sc->regs, LANEX_REG(lane, 0x0a4), 2, 0, tc->vreg);
565 531 } else {
566   - /* Tx Swing */
567 532 FINSR(sc->regs, LANEX_REG(lane, 0x004), 28, 25, tc->att);
568   - /* Regulator voltage */
569 533 FINSR(sc->regs, LANEX_REG(lane, 0x084), 7, 5, tc->vreg);
570 534 }
571 535  
572 536  
573 537  
574 538  
575 539  
... ... @@ -607,41 +571,24 @@
607 571 u32 ofs = 28;
608 572 u32 ret, i;
609 573  
610   - /*
611   - * assume all enable lanes not-ok (1) and all others
612   - * ok (0) to start
613   - */
614 574 for_each_enable_lane(sc, i)
615 575 lanes_not_ok |= (1 << i);
616 576  
617   - /*
618   - * This is not a mistake. For 2-laner, we
619   - * check bit 29 and 30, NOT 28 and 29.
620   - */
621 577 if (!FOUR_LANE(sc->regs))
622 578 ofs = 29;
623 579  
624 580 do {
625 581 time_check = jiffies;
626 582 for_each_enable_lane(sc, i) {
627   - /*
628   - * no need to check again if this lane's status
629   - * is already good
630   - */
631 583 if (!(lanes_not_ok & (1 << i)))
632 584 continue;
633 585  
634 586 ret = kserdes_readl(sc->regs, CML_REG(0x1f8));
635 587  
636   - /*
637   - * clear corresponding lane_not_ok bit if
638   - * status is good (1)
639   - */
640 588 if (ret & BIT(ofs + i))
641 589 lanes_not_ok &= ~(1 << i);
642 590 }
643 591  
644   - /* get out if all lanes are good to go */
645 592 if (!lanes_not_ok)
646 593 return 0;
647 594  
648 595  
649 596  
650 597  
... ... @@ -659,34 +606,21 @@
659 606 u32 lanes_not_ok = 0;
660 607 u32 ret, i;
661 608  
662   - /*
663   - * assume all enable lanes not-ok (1) and all others
664   - * ok (0) to start
665   - */
666 609 for_each_enable_lane(sc, i)
667 610 lanes_not_ok |= (1 << i);
668 611  
669 612 do {
670 613 time_check = jiffies;
671 614 for_each_enable_lane(sc, i) {
672   - /*
673   - * no need to check again if this lane's status
674   - * is already good
675   - */
676 615 if (!(lanes_not_ok & (1 << i)))
677 616 continue;
678 617  
679 618 ret = _kserdes_read_select_tbus(sc->regs, i + 1, 0x02);
680 619  
681   - /*
682   - * clear corresponding lane_not_ok bit if
683   - * status is good (0)
684   - */
685 620 if (!(ret & BIT(4)))
686 621 lanes_not_ok &= ~(1 << i);
687 622 }
688 623  
689   - /* get out if all lanes are good to go */
690 624 if (!lanes_not_ok)
691 625 return 0;
692 626  
... ... @@ -708,7 +642,6 @@
708 642 if (sc->phy_type == KSERDES_PHY_XGE) {
709 643 FINSR(sc->regs, LANEX_REG(lane, 0x60), 0, 0, 0x1);
710 644 }
711   - /* release reset */
712 645 _kserdes_lane_reset(sc->regs, lane, 0);
713 646 }
714 647  
... ... @@ -722,7 +655,6 @@
722 655 if (!poll)
723 656 goto done;
724 657  
725   - /* Check Lane OK */
726 658 if (sc->phy_type == KSERDES_PHY_PCIE)
727 659 ret = kserdes_deassert_reset_poll_pcie(sc);
728 660 else
... ... @@ -744,7 +676,6 @@
744 676 FINSR(sregs, LANE_CTRL_STS_REG(lane), 15, 13, 0x7);
745 677 }
746 678  
747   -/* Caller should make sure sgmii cannot be fullrate */
748 679 static inline int _kserdes_set_lane_ctrl_rate(void __iomem *sregs, u32 lane,
749 680 enum kserdes_lane_ctrl_rate rate)
750 681 {
751 682  
... ... @@ -764,9 +695,7 @@
764 695 return -EINVAL;
765 696 }
766 697  
767   - /* Tx */
768 698 FINSR(sregs, LANE_CTRL_STS_REG(lane), 28, 26, rate_mode);
769   - /* Rx */
770 699 FINSR(sregs, LANE_CTRL_STS_REG(lane), 12, 10, rate_mode);
771 700 return 0;
772 701 }
773 702  
... ... @@ -794,11 +723,9 @@
794 723 return;
795 724 }
796 725  
797   - /* Config RXEQ Gain for all lanes */
798 726 FINSR(sc->regs, LANEX_REG(lane, 0x30), 11, 11, 0x1);
799 727 FINSR(sc->regs, LANEX_REG(lane, 0x30), 13, 12, 0x0);
800 728  
801   - /* set NES bit if loopback enabled */
802 729 if (sc->lane[lane].loopback)
803 730 _kserdes_set_lane_loopback(sc->regs, lane, sc->link_rate);
804 731  
805 732  
... ... @@ -869,10 +796,8 @@
869 796 {
870 797 u32 val, i;
871 798  
872   - /* Check PLL OK Status Bit */
873 799 val = _kserdes_get_pll_status(sc->regs);
874 800 if (!val) {
875   - /* pll is not ready */
876 801 goto done;
877 802 }
878 803  
879 804  
... ... @@ -882,15 +807,10 @@
882 807 goto done;
883 808 }
884 809  
885   - /* Check Lane OK Status Bits */
886 810 for_each_enable_lane(sc, i)
887 811 val &= _kserdes_get_lane_status(sc->regs, i, sc->phy_type);
888 812  
889 813 done:
890   - /*
891   - * if any of the status is 0, this is 0
892   - * i.e. serdes status is not good
893   - */
894 814 return val;
895 815 }
896 816  
897 817  
898 818  
... ... @@ -931,15 +851,12 @@
931 851 }
932 852 }
933 853  
934   -/* lane is 0-based */
935 854 static void
936 855 _kserdes_write_offsets_xge(void __iomem *sregs, u32 lane, u32 cmp,
937 856 struct kserdes_cmp_tap_ofs *ofs)
938 857 {
939   - /* set comparator number */
940 858 FINSR(sregs, CML_REG(0x8c), 23, 21, cmp);
941 859  
942   - /* read offsets */
943 860 FINSR(sregs, CMU0_REG(0xfc), 26, 16, ((lane + 2) << 8) + 0x11);
944 861 ofs->cmp = (_kserdes_read_tbus_val(sregs) & 0x0ff0) >> 4;
945 862  
946 863  
947 864  
... ... @@ -986,15 +903,11 @@
986 903 }
987 904 }
988 905  
989   -/* lane is 0-based */
990 906 static void
991 907 kserdes_get_cmp_tap_offsets_non_xge(void __iomem *sregs, u32 lane, u32 cmp,
992 908 struct kserdes_cmp_tap_ofs *ofs)
993 909 {
994   - /* set comparator number */
995 910 FINSR(sregs, CML_REG(0x8c), 23, 21, cmp);
996   -
997   - /* read offsets */
998 911 FINSR(sregs, CMU0_REG(0x8), 31, 24, ((lane + 1) << 5) + 0x12);
999 912 ofs->cmp = (_kserdes_read_tbus_val(sregs) & 0x0ff0) >> 4;
1000 913 }
... ... @@ -1046,7 +959,6 @@
1046 959 kserdes_add_offsets_non_xge(sc, sofs);
1047 960 }
1048 961  
1049   - /* take the average */
1050 962 for_each_lane(sc, lane) {
1051 963 lofs = &sofs->lane_ofs[lane];
1052 964 for_each_comparator(cmp) {
1053 965  
... ... @@ -1197,13 +1109,11 @@
1197 1109 /* amount of time to sleep is by experiment */
1198 1110 usleep_range(10, 20);
1199 1111  
1200   - /* Get offset */
1201 1112 kserdes_get_average_offsets(sc, OFFSET_SAMPLES, sofs);
1202 1113 kserdes_set_offsets(sc, sofs);
1203 1114 /* amount of time to sleep is by experiment */
1204 1115 usleep_range(10, 20);
1205 1116  
1206   - /* re-acquire signal detect */
1207 1117 for_each_lane(sc, lane)
1208 1118 kserdes_force_signal_detect_high(sc, lane);
1209 1119  
... ... @@ -1236,7 +1146,6 @@
1236 1146 u32 i, att_read[KSERDES_MAX_LANES], att_start[KSERDES_MAX_LANES];
1237 1147 int ret;
1238 1148  
1239   - /* First read initial att start value */
1240 1149 for_each_lane(sc, i) {
1241 1150 att_start[i] = kserdes_readl(sc->regs, LANEX_REG(i, 0x8c));
1242 1151 att_start[i] = (att_start[i] >> 8) & 0xf;
... ... @@ -1270,7 +1179,6 @@
1270 1179 }
1271 1180 }
1272 1181  
1273   - /* write back initial att start value */
1274 1182 for_each_lane(sc, i)
1275 1183 FINSR(sc->regs, LANEX_REG(i, 0x8c), 11, 8, att_start[i]);
1276 1184  
... ... @@ -1286,7 +1194,6 @@
1286 1194 u32 boost_read;
1287 1195 int ret;
1288 1196  
1289   - /* check lane rx valid */
1290 1197 ret = kserdes_wait_lane_rx_valid(sc, lane);
1291 1198 if (ret) {
1292 1199 dev_err(sc->dev, "lane %d wait rx valid failed: %d\n",
1293 1200  
... ... @@ -1294,14 +1201,12 @@
1294 1201 return ret;
1295 1202 }
1296 1203  
1297   - /* check boost value */
1298 1204 boost_read = _kserdes_read_select_tbus(
1299 1205 sc->regs, lane + 1,
1300 1206 (sc->phy_type == KSERDES_PHY_XGE) ?
1301 1207 0x10 : 0x11);
1302 1208 boost_read = (boost_read >> 8) & 0xf;
1303 1209  
1304   - /* if boost = 0, increment by 1 */
1305 1210 if (!boost_read) {
1306 1211 FINSR(sc->regs, LANEX_REG(lane, 0x2c), 2, 2, 0x1);
1307 1212 FINSR(sc->regs, LANEX_REG(lane, 0x2c), 18, 12, 0x2);
... ... @@ -1333,7 +1238,6 @@
1333 1238 u32 att_start, att_read, boost_read;
1334 1239 int ret;
1335 1240  
1336   - /* some setups */
1337 1241 if (sc->phy_type == KSERDES_PHY_XGE) {
1338 1242 tbus_ofs = 0x10;
1339 1243 rxeq_init_reg_ofs = 0x9c;
... ... @@ -1346,7 +1250,6 @@
1346 1250 rxeq_ln_force_bit = 11;
1347 1251 }
1348 1252  
1349   - /* First save a copy of initial att start value */
1350 1253 att_start = kserdes_readl(sregs, LANEX_REG(lane, 0x8c));
1351 1254 att_start = (att_start >> 8) & 0xf;
1352 1255  
... ... @@ -1362,7 +1265,6 @@
1362 1265 FINSR(sregs, LANEX_REG(lane, rxeq_ln_reg_ofs),
1363 1266 rxeq_ln_force_bit, rxeq_ln_force_bit, 0x0);
1364 1267  
1365   - /* check lane rx valid */
1366 1268 ret = kserdes_wait_lane_rx_valid(sc, lane);
1367 1269 if (ret) {
1368 1270 dev_err(sc->dev, "lane %d wait rx valid failed: %d\n",
1369 1271  
... ... @@ -1371,11 +1273,9 @@
1371 1273 /* amount of time to sleep is by experiment */
1372 1274 usleep_range(300, 400);
1373 1275  
1374   - /* check boost value */
1375 1276 boost_read = _kserdes_read_select_tbus(sregs, lane + 1, tbus_ofs);
1376 1277 boost_read = (boost_read >> 8) & 0xf;
1377 1278  
1378   - /* increment boost by 1 if it's 0 */
1379 1279 if (!boost_read) {
1380 1280 FINSR(sregs, LANEX_REG(lane, 0x2c), 2, 2, 0x1);
1381 1281 FINSR(sregs, LANEX_REG(lane, 0x2c), 18, 12, 0x2);
1382 1282  
1383 1283  
1384 1284  
1385 1285  
... ... @@ -1412,24 +1312,16 @@
1412 1312 for_each_enable_lane(sc, i)
1413 1313 lanes_enable |= (1 << i);
1414 1314  
1415   - /*
1416   - * disable transmitter on all lanes to prevent
1417   - * receiver from adapting
1418   - */
1419 1315 for_each_lane(sc, i)
1420 1316 kserdes_set_tx_idle(sc, i);
1421 1317  
1422   - /* apply highspeed config for link rates greater than 8Gbaud */
1423 1318 kserdes_highspeed_cfg(sc);
1424 1319  
1425   - /* assert serdes reset */
1426 1320 kserdes_assert_reset(sc);
1427 1321  
1428   - /* apply the TX and RX FIR coefficients to the lanes */
1429 1322 for_each_enable_lane(sc, i)
1430 1323 kserdes_set_tx_rx_fir_coeff(sc, i);
1431 1324  
1432   - /* Force Signal Detect Low. This resets the RX */
1433 1325 for_each_enable_lane(sc, i)
1434 1326 kserdes_force_signal_detect_low(sc, i);
1435 1327  
... ... @@ -1439,7 +1331,6 @@
1439 1331 return ret;
1440 1332 }
1441 1333  
1442   - /* allow signal detect enable */
1443 1334 for_each_enable_lane(sc, i)
1444 1335 kserdes_set_lane_rate(sc, i);
1445 1336  
1446 1337  
1447 1338  
1448 1339  
1449 1340  
... ... @@ -1451,21 +1342,16 @@
1451 1342 return ret;
1452 1343 }
1453 1344  
1454   - /* Get tx termination */
1455 1345 val = _kserdes_get_tx_termination(sc->regs, 0, sc->phy_type);
1456 1346  
1457   - /* Apply tx termination */
1458 1347 kserdes_set_tx_terminations(sc, val);
1459 1348  
1460   - /* enable transmitter on all lanes */
1461 1349 for_each_enable_lane(sc, i)
1462 1350 kserdes_clr_tx_idle(sc, i);
1463 1351  
1464   - /* allow Signal Detect Enable */
1465 1352 for_each_enable_lane(sc, i)
1466 1353 kserdes_force_signal_detect_high(sc, i);
1467 1354  
1468   - /* Wait for RX Valid on all lanes */
1469 1355 for_each_enable_lane(sc, i) {
1470 1356 ret = kserdes_wait_lane_rx_valid(sc, i);
1471 1357 if (ret) {
1472 1358  
... ... @@ -1475,11 +1361,9 @@
1475 1361 }
1476 1362 }
1477 1363  
1478   - /* Apply Attenuation and Boost config if rx force flag is set */
1479 1364 if (!sc->rx_force_enable)
1480 1365 kserdes_rx_att_boost_cfg(sc);
1481 1366  
1482   - /* Enable MAC RX to allow MAC to take control */
1483 1367 _kserdes_clear_wait_after(sc->regs);
1484 1368  
1485 1369 return lanes_enable;
... ... @@ -1499,7 +1383,6 @@
1499 1383  
1500 1384 static inline void _kserdes_reset(void __iomem *sregs)
1501 1385 {
1502   - /* Toggle POR_EN bit */
1503 1386 FINSR(sregs, CPU_CTRL_REG, 29, 29, 0x1);
1504 1387 /* amount of time to sleep is by experiment */
1505 1388 usleep_range(10, 20);
... ... @@ -1510,7 +1393,6 @@
1510 1393  
1511 1394 static inline void kserdes_xge_pll_enable(struct kserdes_config *sc)
1512 1395 {
1513   - /* phyb reset clear */
1514 1396 if (!sc->firmware)
1515 1397 FINSR(sc->regs, CML_REG(0), 7, 0, 0x1f);
1516 1398  
1517 1399  
... ... @@ -1524,11 +1406,9 @@
1524 1406  
1525 1407 static inline void _kserdes_xge_enable_pcs(void __iomem *sregs, u32 lane)
1526 1408 {
1527   - /* set bus-width to 16 bit mode */
1528 1409 FINSR(sregs, LANE_CTRL_STS_REG(lane), 23, 21, 0x7);
1529 1410 FINSR(sregs, LANE_CTRL_STS_REG(lane), 5, 3, 0x7);
1530 1411  
1531   - /* enable PCS overlay and lane select 10GKR */
1532 1412 FINSR(sregs, LANE_CTRL_STS_REG(lane), 16, 16, 0x1);
1533 1413 FINSR(sregs, LANE_CTRL_STS_REG(lane), 19, 19, 0x1);
1534 1414 }
... ... @@ -1537,7 +1417,6 @@
1537 1417 {
1538 1418 u32 lane_ctrl_rate = sc->lane[lane].ctrl_rate;
1539 1419  
1540   - /* Set Lane Control Rate */
1541 1420 if (sc->link_rate == KSERDES_LINK_RATE_10P3125G)
1542 1421 _kserdes_set_lane_ctrl_rate(sc->regs, lane, lane_ctrl_rate);
1543 1422 else if (sc->link_rate == KSERDES_LINK_RATE_1P25G)
... ... @@ -1561,7 +1440,6 @@
1561 1440  
1562 1441 static inline void _kserdes_reset_rx(void __iomem *sregs, int lane)
1563 1442 {
1564   - /* toggle signal detect */
1565 1443 _kserdes_force_signal_detect_low(sregs, lane);
1566 1444 /* amount of time to sleep is by experiment */
1567 1445 usleep_range(1000, 2000);
1568 1446  
... ... @@ -1577,10 +1455,8 @@
1577 1455 int ret;
1578 1456  
1579 1457 for_each_enable_lane(sc, i) {
1580   - /* Rx Signal Loss bit in serdes lane control and status reg*/
1581 1458 loss = (kserdes_readl(sc->regs, LANE_CTRL_STS_REG(i))) & 0x01;
1582 1459  
1583   - /* Block Errors and Block Lock bits in PCSR rx status reg */
1584 1460 ret = regmap_read(sc->pcsr_regmap, PCSR_RX_STATUS(i),
1585 1461 &pcsr_rx_stat);
1586 1462  
1587 1463  
1588 1464  
... ... @@ -1590,23 +1466,17 @@
1590 1466 blk_lock = (pcsr_rx_stat >> 30) & 0x1;
1591 1467 blk_errs = (pcsr_rx_stat >> 16) & 0x0ff;
1592 1468  
1593   - /* If Block error, attempt recovery! */
1594 1469 if (blk_errs)
1595 1470 blk_lock = 0;
1596 1471  
1597 1472 switch (current_state[i]) {
1598 1473 case 0:
1599   - /* if good link lock the signal detect ON! */
1600 1474 if (!loss && blk_lock) {
1601 1475 dev_dbg(sc->dev, "XGE PCSR Linked Lane: %d\n",
1602 1476 i);
1603 1477 FINSR(sc->regs, LANEX_REG(i, 0x04), 2, 1, 0x3);
1604 1478 current_state[i] = 1;
1605 1479 } else {
1606   - /*
1607   - * if no lock, then reset rx
1608   - * by toggling sig detect
1609   - */
1610 1480 if (!blk_lock) {
1611 1481 dev_dbg(sc->dev,
1612 1482 "XGE PCSR Recover Lane: %d\n",
1613 1483  
1614 1484  
... ... @@ -1618,19 +1488,13 @@
1618 1488 break;
1619 1489 case 1:
1620 1490 if (!blk_lock) {
1621   - /* Link Lost? */
1622 1491 current_state[i] = 2;
1623 1492 }
1624 1493 break;
1625 1494 case 2:
1626 1495 if (blk_lock) {
1627   - /* Nope just noise */
1628 1496 current_state[i] = 1;
1629 1497 } else {
1630   - /*
1631   - * Lost the block lock, reset rx
1632   - * and go back to sync state
1633   - */
1634 1498 _kserdes_reset_rx(sc->regs, i);
1635 1499 current_state[i] = 0;
1636 1500 }
... ... @@ -1642,7 +1506,6 @@
1642 1506 }
1643 1507  
1644 1508 if (blk_errs) {
1645   - /* Reset the Error counts! */
1646 1509 regmap_update_bits(sc->pcsr_regmap, PCSR_RX_CTL(i),
1647 1510 GENMASK(7, 0), 0x19);
1648 1511 regmap_update_bits(sc->pcsr_regmap, PCSR_RX_CTL(i),
... ... @@ -1707,10 +1570,6 @@
1707 1570 int lanes_up_map = 0;
1708 1571  
1709 1572 if (sc->firmware) {
1710   - /*
1711   - * firmware started in serdes_init and
1712   - * doesn't need lanes enable
1713   - */
1714 1573 return 0;
1715 1574 }
1716 1575  
... ... @@ -1747,9 +1606,9 @@
1747 1606 val_0 = kserdes_readl(sc->regs, LANEX_REG(lane, 0x04));
1748 1607 val_1 = kserdes_readl(sc->regs, LANEX_REG(lane, 0x08));
1749 1608  
1750   - tx_ctrl = ((((val_0 >> 18) & 0x1) << 24) | /* TX_CTRL_O_24 */
1751   - (((val_1 >> 0) & 0xffff) << 8) | /* TX_CTRL_O_23_8 */
1752   - (((val_0 >> 24) & 0xff) << 0)); /* TX_CTRL_O_7_0 */
  1609 + tx_ctrl = ((((val_0 >> 18) & 0x1) << 24) |
  1610 + (((val_1 >> 0) & 0xffff) << 8) |
  1611 + (((val_0 >> 24) & 0xff) << 0));
1753 1612  
1754 1613 if (phy_a) {
1755 1614 fw->cm = (val_1 >> 12) & 0xf;
1756 1615  
1757 1616  
... ... @@ -1784,15 +1643,12 @@
1784 1643  
1785 1644 lane_config <<= 8;
1786 1645  
1787   - /* initialize internal parameter area */
1788 1646 kserdes_writel(sc->regs, MEM_ADR_REG, KSERDES_XFW_CONFIG_START_ADDR);
1789 1647  
1790   - /* clean out unused config area */
1791 1648 for (i = KSERDES_XFW_CONFIG_START_ADDR;
1792 1649 i < KSERDES_XFW_PARAM_START_ADDR; i += 4)
1793 1650 kserdes_writel(sc->regs, MEM_DATINC_REG, 0x00000000);
1794 1651  
1795   - /* Flush 64 bytes 10,11,12,13 */
1796 1652 kserdes_writel(sc->regs, MEM_DATINC_REG, XFM_FLUSH_CMD);
1797 1653 kserdes_writel(sc->regs, MEM_DATINC_REG, fw->fast_train);
1798 1654 kserdes_writel(sc->regs, MEM_DATINC_REG, 0x00000000);
... ... @@ -2057,7 +1913,6 @@
2057 1913  
2058 1914 sc->dev = dev;
2059 1915  
2060   - /* Set the defaults base on phy type */
2061 1916 kserdes_set_defaults(sc, sc->phy_type);
2062 1917  
2063 1918 if (sc->phy_type == KSERDES_PHY_XGE) {