Eric Lee / smarc-ti-linux-kernel | Embedian Git Server

Commit cb84c2b401d9cead5508cfed57b59b6d5feffdac

Authored by Guenter Roeck 2014-12-10 06:21:45 +0800

Committed by Richard Kuo 2014-12-17 03:27:12 +0800

hexagon: Fix build failures in linux-next

hexagon:defconfig fails to build in linux-next since commit 332fd7c4fef5
("genirq: Generic chip: Change irq_reg_{readl,writel} arguments").

The primary build failure is

arch/hexagon/include/asm/cacheflush.h: In function 'copy_to_user_page':
arch/hexagon/include/asm/cacheflush.h:89:22: error: 'VM_EXEC' undeclared

This is the result of including of <linux/io.h> from <linux/irq.h>,
which is now necessary due to the use of readl and writel from irq.h.
This causes recursive inclusions in hexagon code; cacheflush.h is included
from mm.h prior to the definition of VM_EXEC.

Fix the problem by moving copy_to_user_page from the hexagon include file to
arch/hexagon/mm/cache.c, similar to other architectures. After this change,
several redefinitions of readl and writel are reported. Those are caused
by recursive inclusions of io.h and asm/cacheflush.h. Fix those problems by
reducing the number of files included from those files. Also, it was necessary
to stop including asm-generic/cacheflush.h from asm/cacheflush.h. Instead,
functionality originally provided by asm-generic/cacheflush.h is now coded
in asm/cacheflush.h directly.

Cc: Kevin Cernekee <cernekee@gmail.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
signed-off-by: Richard Kuo <rkuo@codeaurora.org>

Showing 5 changed files with 31 additions and 22 deletions Inline Diff

arch/hexagon/include/asm/cacheflush.h
arch/hexagon/include/asm/io.h
arch/hexagon/kernel/setup.c
arch/hexagon/mm/cache.c
arch/hexagon/mm/ioremap.c

arch/hexagon/include/asm/cacheflush.h

Diff comments View file @ cb84c2b

 /*
  * Cache flush operations for the Hexagon architecture
  *
  * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
  * only version 2 as published by the Free Software Foundation.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  * 02110-1301, USA.
  */
 #ifndef _ASM_CACHEFLUSH_H
 #define _ASM_CACHEFLUSH_H
-#include <linux/cache.h>
+#include <linux/mm_types.h>
-#include <linux/mm.h>
-#include <asm/string.h>
-#include <asm-generic/cacheflush.h>
 /* Cache flushing:
  *
  *  - flush_cache_all() flushes entire cache
  *  - flush_cache_mm(mm) flushes the specified mm context's cache lines
  *  - flush_cache_page(mm, vmaddr, pfn) flushes a single page
  *  - flush_cache_range(vma, start, end) flushes a range of pages
  *  - flush_icache_range(start, end) flush a range of instructions
  *  - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
  *  - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
  *
  *  Need to doublecheck which one is really needed for ptrace stuff to work.
  */
 #define LINESIZE	32
 #define LINEBITS	5
+#define flush_cache_all()			do { } while (0)
+#define flush_cache_mm(mm)			do { } while (0)
+#define flush_cache_dup_mm(mm)			do { } while (0)
+#define flush_cache_range(vma, start, end)	do { } while (0)
+#define flush_cache_page(vma, vmaddr, pfn)	do { } while (0)
+#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
+#define flush_dcache_page(page)			do { } while (0)
+#define flush_dcache_mmap_lock(mapping)		do { } while (0)
+#define flush_dcache_mmap_unlock(mapping)	do { } while (0)
+#define flush_icache_page(vma, pg)		do { } while (0)
+#define flush_icache_user_range(vma, pg, adr, len)	do { } while (0)
+#define flush_cache_vmap(start, end)		do { } while (0)
+#define flush_cache_vunmap(start, end)		do { } while (0)
 /*
  * Flush Dcache range through current map.
  */
 extern void flush_dcache_range(unsigned long start, unsigned long end);
 /*
  * Flush Icache range through current map.
  */
-#undef flush_icache_range
 extern void flush_icache_range(unsigned long start, unsigned long end);
 /*
  * Memory-management related flushes are there to ensure in non-physically
  * indexed cache schemes that stale lines belonging to a given ASID aren't
  * in the cache to confuse things.  The prototype Hexagon Virtual Machine
  * only uses a single ASID for all user-mode maps, which should
  * mean that they aren't necessary.  A brute-force, flush-everything
  * implementation, with the name xxxxx_hexagon() is present in
  * arch/hexagon/mm/cache.c, but let's not wire it up until we know
  * it is needed.
  */
 extern void flush_cache_all_hexagon(void);
 /*
  * This may or may not ever have to be non-null, depending on the
  * virtual machine MMU.  For a native kernel, it's definitiely  a no-op
  *
  * This is also the place where deferred cache coherency stuff seems
  * to happen, classically...  but instead we do it like ia64 and
  * clean the cache when the PTE is set.
  *
  */
 static inline void update_mmu_cache(struct vm_area_struct *vma,
 					unsigned long address, pte_t *ptep)
 {
 	/*  generic_ptrace_pokedata doesn't wind up here, does it?  */
 }
-#undef copy_to_user_page
+void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
-static inline void copy_to_user_page(struct vm_area_struct *vma,
+		       unsigned long vaddr, void *dst, void *src, int len);
-					     struct page *page,
-					     unsigned long vaddr,
-					     void *dst, void *src, int len)
-{
-	memcpy(dst, src, len);

arch/hexagon/include/asm/io.h

Diff comments View file @ cb84c2b

 /*
  * IO definitions for the Hexagon architecture
  *
  * Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
  * only version 2 as published by the Free Software Foundation.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  * 02110-1301, USA.
  */
 #ifndef _ASM_IO_H
 #define _ASM_IO_H
 #ifdef __KERNEL__
 #include <linux/types.h>
-#include <linux/delay.h>
-#include <linux/vmalloc.h>
-#include <asm/string.h>
-#include <asm/mem-layout.h>
 #include <asm/iomap.h>
 #include <asm/page.h>
 #include <asm/cacheflush.h>
-#include <asm/tlbflush.h>
 /*
  * We don't have PCI yet.
  * _IO_BASE is pointing at what should be unused virtual space.
  */
 #define IO_SPACE_LIMIT 0xffff
 #define _IO_BASE ((void __iomem *)0xfe000000)
 #define IOMEM(x)        ((void __force __iomem *)(x))
 extern int remap_area_pages(unsigned long start, unsigned long phys_addr,
 				unsigned long end, unsigned long flags);
 extern void __iounmap(const volatile void __iomem *addr);
 /* Defined in lib/io.c, needed for smc91x driver. */
 extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
 extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen);
 extern void __raw_readsl(const void __iomem *addr, void *data, int wordlen);
 extern void __raw_writesl(void __iomem *addr, const void *data, int wordlen);
 #define readsw(p, d, l)	__raw_readsw(p, d, l)
 #define writesw(p, d, l) __raw_writesw(p, d, l)
 #define readsl(p, d, l)   __raw_readsl(p, d, l)
 #define writesl(p, d, l)  __raw_writesl(p, d, l)
 /*
  * virt_to_phys - map virtual address to physical
  * @address:  address to map
  */
 static inline unsigned long virt_to_phys(volatile void *address)
 {
 	return __pa(address);
 }
 /*
  * phys_to_virt - map physical address to virtual
  * @address: address to map
  */
 static inline void *phys_to_virt(unsigned long address)
 {
 	return __va(address);
 }
 /*
  * convert a physical pointer to a virtual kernel pointer for
  * /dev/mem access.
  */
 #define xlate_dev_kmem_ptr(p)    __va(p)
 #define xlate_dev_mem_ptr(p)    __va(p)
 /*
  * IO port access primitives.  Hexagon doesn't have special IO access
  * instructions; all I/O is memory mapped.
  *
  * in/out are used for "ports", but we don't have "port instructions",
  * so these are really just memory mapped too.
  */
 /*
  * readb - read byte from memory mapped device
  * @addr:  pointer to memory
  *
  * Operates on "I/O bus memory space"
  */
 static inline u8 readb(const volatile void __iomem *addr)
 {
 	u8 val;
 	asm volatile(
 		"%0 = memb(%1);"
 		: "=&r" (val)
 		: "r" (addr)
 	);
 	return val;
 }
 static inline u16 readw(const volatile void __iomem *addr)
 {
 	u16 val;
 	asm volatile(
 		"%0 = memh(%1);"
 		: "=&r" (val)
 		: "r" (addr)
 	);
 	return val;
 }
 static inline u32 readl(const volatile void __iomem *addr)
 {
 	u32 val;
 	asm volatile(
 		"%0 = memw(%1);"
 		: "=&r" (val)
 		: "r" (addr)
 	);
 	return val;
 }
 /*
  * writeb - write a byte to a memory location
  * @data: data to write to
  * @addr:  pointer to memory
  *
  */
 static inline void writeb(u8 data, volatile void __iomem *addr)
 {
 	asm volatile(
 		"memb(%0) = %1;"
 		:
 		: "r" (addr), "r" (data)
 		: "memory"
 	);
 }
 static inline void writew(u16 data, volatile void __iomem *addr)
 {
 	asm volatile(
 		"memh(%0) = %1;"
 		:
 		: "r" (addr), "r" (data)
 		: "memory"
 	);
 }
 static inline void writel(u32 data, volatile void __iomem *addr)
 {
 	asm volatile(
 		"memw(%0) = %1;"
 		:
 		: "r" (addr), "r" (data)
 		: "memory"
 	);
 }
 #define __raw_writeb writeb
 #define __raw_writew writew
 #define __raw_writel writel
 #define __raw_readb readb
 #define __raw_readw readw
 #define __raw_readl readl
 /*
  * http://comments.gmane.org/gmane.linux.ports.arm.kernel/117626
  */
 #define readb_relaxed __raw_readb
 #define readw_relaxed __raw_readw
 #define readl_relaxed __raw_readl
 #define writeb_relaxed __raw_writeb
 #define writew_relaxed __raw_writew
 #define writel_relaxed __raw_writel
 #define mmiowb()
 /*
  * Need an mtype somewhere in here, for cache type deals?
  * This is probably too long for an inline.
  */
 void __iomem *ioremap_nocache(unsigned long phys_addr, unsigned long size);
 static inline void __iomem *ioremap(unsigned long phys_addr, unsigned long size)
 {
 	return ioremap_nocache(phys_addr, size);
 }
 static inline void iounmap(volatile void __iomem *addr)
 {
 	__iounmap(addr);
 }
 #define __raw_writel writel
 static inline void memcpy_fromio(void *dst, const volatile void __iomem *src,
 	int count)
 {
 	memcpy(dst, (void *) src, count);
 }
 static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
 	int count)
 {
 	memcpy((void *) dst, src, count);
 }
 #define PCI_IO_ADDR	(volatile void __iomem *)
 /*
  * inb - read byte from I/O port or something
  * @port:  address in I/O space
  *
  * Operates on "I/O bus I/O space"
  */
 static inline u8 inb(unsigned long port)
 {
 	return readb(_IO_BASE + (port & IO_SPACE_LIMIT));
 }
 static inline u16 inw(unsigned long port)
 {
 	return readw(_IO_BASE + (port & IO_SPACE_LIMIT));
 }
 static inline u32 inl(unsigned long port)
 {
 	return readl(_IO_BASE + (port & IO_SPACE_LIMIT));
 }
 /*
  * outb - write a byte to a memory location
  * @data: data to write to
  * @addr:  address in I/O space
  */
 static inline void outb(u8 data, unsigned long port)
 {
 	writeb(data, _IO_BASE + (port & IO_SPACE_LIMIT));
 }
 static inline void outw(u16 data, unsigned long port)
 {
 	writew(data, _IO_BASE + (port & IO_SPACE_LIMIT));
 }
 static inline void outl(u32 data, unsigned long port)
 {
 	writel(data, _IO_BASE + (port & IO_SPACE_LIMIT));
 }
 #define outb_p outb
 #define outw_p outw
 #define outl_p outl
 #define inb_p inb
 #define inw_p inw
 #define inl_p inl
 static inline void insb(unsigned long port, void *buffer, int count)
 {
 	if (count) {
 		u8 *buf = buffer;
 		do {
 			u8 x = inb(port);
 			*buf++ = x;
 		} while (--count);
 	}
 }
 static inline void insw(unsigned long port, void *buffer, int count)
 {
 	if (count) {
 		u16 *buf = buffer;
 		do {
 			u16 x = inw(port);
 			*buf++ = x;
 		} while (--count);
 	}
 }
 static inline void insl(unsigned long port, void *buffer, int count)
 {
 	if (count) {
 		u32 *buf = buffer;
 		do {
 			u32 x = inw(port);
 			*buf++ = x;
 		} while (--count);
 	}
 }
 static inline void outsb(unsigned long port, const void *buffer, int count)
 {
 	if (count) {
 		const u8 *buf = buffer;
 		do {
 			outb(*buf++, port);
 		} while (--count);
 	}
 }
 static inline void outsw(unsigned long port, const void *buffer, int count)
 {
 	if (count) {
 		const u16 *buf = buffer;
 		do {
 			outw(*buf++, port);
 		} while (--count);
 	}
 }
 static inline void outsl(unsigned long port, const void *buffer, int count)
 {
 	if (count) {
 		const u32 *buf = buffer;
 		do {
 			outl(*buf++, port);
 		} while (--count);
 	}
 }
 #define flush_write_buffers() do { } while (0)
 #endif /* __KERNEL__ */
 #endif

arch/hexagon/kernel/setup.c

Diff comments View file @ cb84c2b

 /*
  * Arch related setup for Hexagon
  *
  * Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
  * only version 2 as published by the Free Software Foundation.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  * 02110-1301, USA.
  */
 #include <linux/init.h>
+#include <linux/delay.h>
 #include <linux/bootmem.h>
 #include <linux/mmzone.h>
 #include <linux/mm.h>
 #include <linux/seq_file.h>
 #include <linux/console.h>
 #include <linux/of_fdt.h>
 #include <asm/io.h>
 #include <asm/sections.h>
 #include <asm/setup.h>
 #include <asm/processor.h>
 #include <asm/hexagon_vm.h>
 #include <asm/vm_mmu.h>
 #include <asm/time.h>
 char cmd_line[COMMAND_LINE_SIZE];
 static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
 int on_simulator;
 void calibrate_delay(void)
 {
 	loops_per_jiffy = thread_freq_mhz * 1000000 / HZ;
 }
 /*
  * setup_arch -  high level architectural setup routine
  * @cmdline_p: pointer to pointer to command-line arguments
  */
 void __init setup_arch(char **cmdline_p)
 {
 	char *p = &external_cmdline_buffer;
 	/*
 	 * These will eventually be pulled in via either some hypervisor
 	 * or devicetree description.  Hardwiring for now.
 	 */
 	pcycle_freq_mhz = 600;
 	thread_freq_mhz = 100;
 	sleep_clk_freq = 32000;
 	/*
 	 * Set up event bindings to handle exceptions and interrupts.
 	 */
 	__vmsetvec(_K_VM_event_vector);
 	printk(KERN_INFO "PHYS_OFFSET=0x%08x\n", PHYS_OFFSET);
 	/*
 	 * Simulator has a few differences from the hardware.
 	 * For now, check uninitialized-but-mapped memory
 	 * prior to invoking setup_arch_memory().
 	 */
 	if (*(int *)((unsigned long)_end + 8) == 0x1f1f1f1f)
 		on_simulator = 1;
 	else
 		on_simulator = 0;
 	if (p[0] != '\0')
 		strlcpy(boot_command_line, p, COMMAND_LINE_SIZE);
 	else
 		strlcpy(boot_command_line, default_command_line,
 			COMMAND_LINE_SIZE);
 	/*
 	 * boot_command_line and the value set up by setup_arch
 	 * are both picked up by the init code. If no reason to
 	 * make them different, pass the same pointer back.
 	 */
 	strlcpy(cmd_line, boot_command_line, COMMAND_LINE_SIZE);
 	*cmdline_p = cmd_line;
 	parse_early_param();
 	setup_arch_memory();
 #ifdef CONFIG_SMP
 	smp_start_cpus();
 #endif
 }
 /*
  * Functions for dumping CPU info via /proc
  * Probably should move to kernel/proc.c or something.
  */
 static void *c_start(struct seq_file *m, loff_t *pos)
 {
 	return *pos < nr_cpu_ids ? (void *)((unsigned long) *pos + 1) : NULL;
 }
 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
 {
 	++*pos;
 	return c_start(m, pos);
 }
 static void c_stop(struct seq_file *m, void *v)
 {
 }
 /*
  * Eventually this will dump information about
  * CPU properties like ISA level, TLB size, etc.
  */
 static int show_cpuinfo(struct seq_file *m, void *v)
 {
 	int cpu = (unsigned long) v - 1;
 #ifdef CONFIG_SMP
 	if (!cpu_online(cpu))
 		return 0;
 #endif
 	seq_printf(m, "processor\t: %d\n", cpu);
 	seq_printf(m, "model name\t: Hexagon Virtual Machine\n");
 	seq_printf(m, "BogoMips\t: %lu.%02lu\n",
 		(loops_per_jiffy * HZ) / 500000,
 		((loops_per_jiffy * HZ) / 5000) % 100);
 	seq_printf(m, "\n");
 	return 0;
 }
 const struct seq_operations cpuinfo_op = {
 	.start  = &c_start,
 	.next   = &c_next,
 	.stop   = &c_stop,
 	.show   = &show_cpuinfo,
 };

arch/hexagon/mm/cache.c

Diff comments View file @ cb84c2b

 /*
  * Cache management functions for Hexagon
  *
  * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
  * only version 2 as published by the Free Software Foundation.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  * 02110-1301, USA.
  */
 #include <linux/mm.h>
 #include <asm/cacheflush.h>
 #include <asm/hexagon_vm.h>
 #define spanlines(start, end) \
 	(((end - (start & ~(LINESIZE - 1))) >> LINEBITS) + 1)
 void flush_dcache_range(unsigned long start, unsigned long end)
 {
 	unsigned long lines = spanlines(start, end-1);
 	unsigned long i, flags;
 	start &= ~(LINESIZE - 1);
 	local_irq_save(flags);
 	for (i = 0; i < lines; i++) {
 		__asm__ __volatile__ (
 		"	dccleaninva(%0);	"
 		:
 		: "r" (start)
 		);
 		start += LINESIZE;
 	}
 	local_irq_restore(flags);
 }
 void flush_icache_range(unsigned long start, unsigned long end)
 {
 	unsigned long lines = spanlines(start, end-1);
 	unsigned long i, flags;
 	start &= ~(LINESIZE - 1);
 	local_irq_save(flags);
 	for (i = 0; i < lines; i++) {
 		__asm__ __volatile__ (
 			"	dccleana(%0); "
 			"	icinva(%0);	"
 			:
 			: "r" (start)
 		);
 		start += LINESIZE;
 	}
 	__asm__ __volatile__ (
 		"isync"
 	);
 	local_irq_restore(flags);
 }
 EXPORT_SYMBOL(flush_icache_range);
 void hexagon_clean_dcache_range(unsigned long start, unsigned long end)
 {
 	unsigned long lines = spanlines(start, end-1);
 	unsigned long i, flags;
 	start &= ~(LINESIZE - 1);
 	local_irq_save(flags);
 	for (i = 0; i < lines; i++) {
 		__asm__ __volatile__ (
 		"	dccleana(%0);	"
 		:
 		: "r" (start)
 		);
 		start += LINESIZE;
 	}
 	local_irq_restore(flags);
 }
 void hexagon_inv_dcache_range(unsigned long start, unsigned long end)
 {
 	unsigned long lines = spanlines(start, end-1);
 	unsigned long i, flags;
 	start &= ~(LINESIZE - 1);
 	local_irq_save(flags);
 	for (i = 0; i < lines; i++) {
 		__asm__ __volatile__ (
 		"	dcinva(%0);	"
 		:
 		: "r" (start)
 		);
 		start += LINESIZE;
 	}
 	local_irq_restore(flags);
 }
 /*
  * This is just really brutal and shouldn't be used anyways,
  * especially on V2.  Left here just in case.
  */
 void flush_cache_all_hexagon(void)
 {
 	unsigned long flags;
 	local_irq_save(flags);
 	__vmcache_ickill();
 	__vmcache_dckill();
 	__vmcache_l2kill();
 	local_irq_restore(flags);
 	mb();
 }
+void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
+		       unsigned long vaddr, void *dst, void *src, int len)
+{
+	memcpy(dst, src, len);
+	if (vma->vm_flags & VM_EXEC) {
+		flush_icache_range((unsigned long) dst,
+		(unsigned long) dst + len);
+	}
+}

arch/hexagon/mm/ioremap.c

Diff comments View file @ cb84c2b

 /*
  * I/O remap functions for Hexagon
  *
  * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
  * only version 2 as published by the Free Software Foundation.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  * 02110-1301, USA.
  */
 #include <linux/io.h>
 #include <linux/vmalloc.h>
+#include <linux/mm.h>
 void __iomem *ioremap_nocache(unsigned long phys_addr, unsigned long size)
 {
 	unsigned long last_addr, addr;
 	unsigned long offset = phys_addr & ~PAGE_MASK;
 	struct vm_struct *area;
 	pgprot_t prot = __pgprot(_PAGE_PRESENT|_PAGE_READ|_PAGE_WRITE
 					|(__HEXAGON_C_DEV << 6));
 	last_addr = phys_addr + size - 1;
 	/*  Wrapping not allowed  */
 	if (!size || (last_addr < phys_addr))
 		return NULL;
 	/*  Rounds up to next page size, including whole-page offset */
 	size = PAGE_ALIGN(offset + size);
 	area = get_vm_area(size, VM_IOREMAP);
 	addr = (unsigned long)area->addr;
 	if (ioremap_page_range(addr, addr+size, phys_addr, prot)) {
 		vunmap((void *)addr);
 		return NULL;
 	}
 	return (void __iomem *) (offset + addr);
 }
 void __iounmap(const volatile void __iomem *addr)
 {
 	vunmap((void *) ((unsigned long) addr & PAGE_MASK));
 }