DMA: AT91: Get transfer width

In one dma transfer, the data transfer width can be configured and it is limited by source or destination peripheral width, tx_width will save the transfer width, but for memcpy, either source or destination transfer width is taken as tx_width. Signed-off-by: Elen Song <elen.song@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>

DMA: AT91: Get transfer width
In one dma transfer, the data transfer width can be configured and it is limited by source or destination peripheral width, tx_width will save the transfer width, but for memcpy, either source or destination transfer width is taken as tx_width. Signed-off-by: Elen Song <elen.song@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Elen Song · Vinod Koul
1 parent 6c22770f64
Showing 2 changed files with 5 additions and 0 deletions Side-by-side Diff
drivers/dma/at_hdmac.c
drivers/dma/at_hdmac_regs.h
@@ -615,6 +615,7 @@
 	/* First descriptor of the chain embedds additional information */
 	first->txd.cookie = -EBUSY;
 	first->len = len;
+	first->tx_width = src_width;
  
 	/* set end-of-link to the last link descriptor of list*/
 	set_desc_eol(desc);
@@ -761,6 +762,7 @@
 	/* First descriptor of the chain embedds additional information */
 	first->txd.cookie = -EBUSY;
 	first->len = total_len;
+	first->tx_width = reg_width;
  
 	/* first link descriptor of list is responsible of flags */
 	first->txd.flags = flags; /* client is in control of this ack */
@@ -919,6 +921,7 @@
 	/* First descriptor of the chain embedds additional information */
 	first->txd.cookie = -EBUSY;
 	first->len = buf_len;
+	first->tx_width = reg_width;
  
 	return &first->txd;
  
@@ -182,6 +182,7 @@
  * @txd: support for the async_tx api
  * @desc_node: node on the channed descriptors list
  * @len: total transaction bytecount
+ * @tx_width: transfer width
  */
 struct at_desc {
 	/* FIRST values the hardware uses */
@@ -192,6 +193,7 @@
 	struct dma_async_tx_descriptor	txd;
 	struct list_head		desc_node;
 	size_t				len;
+	u32				tx_width;
 };
  
 static inline struct at_desc *
...	...	@@ -615,6 +615,7 @@
615	615	/* First descriptor of the chain embedds additional information */
616	616	first->txd.cookie = -EBUSY;
617	617	first->len = len;
	618	+ first->tx_width = src_width;
618	619
619	620	/* set end-of-link to the last link descriptor of list*/
620	621	set_desc_eol(desc);
...	...	@@ -761,6 +762,7 @@
761	762	/* First descriptor of the chain embedds additional information */
762	763	first->txd.cookie = -EBUSY;
763	764	first->len = total_len;
	765	+ first->tx_width = reg_width;
764	766
765	767	/* first link descriptor of list is responsible of flags */
766	768	first->txd.flags = flags; /* client is in control of this ack */
...	...	@@ -919,6 +921,7 @@
919	921	/* First descriptor of the chain embedds additional information */
920	922	first->txd.cookie = -EBUSY;
921	923	first->len = buf_len;
	924	+ first->tx_width = reg_width;
922	925
923	926	return &first->txd;
924	927
...	...	@@ -182,6 +182,7 @@
182	182	* @txd: support for the async_tx api
183	183	* @desc_node: node on the channed descriptors list
184	184	* @len: total transaction bytecount
	185	+ * @tx_width: transfer width
185	186	*/
186	187	struct at_desc {
187	188	/* FIRST values the hardware uses */
...	...	@@ -192,6 +193,7 @@
192	193	struct dma_async_tx_descriptor txd;
193	194	struct list_head desc_node;
194	195	size_t len;
	196	+ u32 tx_width;
195	197	};
196	198
197	199	static inline struct at_desc *