Eric Lee / smarc-ti-linux-kernel

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Commit d0ac5d8e673aa7317c0d132ba3092935dac53298

Authored by Linus Torvalds
2 parents 12ba8571ab 966903a98f
Exists in ti-lsk-linux-4.1.y and in 10 other branches dlt-processor-sdk-linux-03.00.00.04, processor-sdk-linux-02.00.01, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04

Merge tag 'armsoc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC fixes from Olof Johansson:
 "We've been sitting on our fixes branch for a while, so this batch is
  unfortunately on the large side.

  A lot of these are tweaks and fixes to device trees, fixing various
  bugs around clocks, reg ranges, etc.  There's also a few defconfig
  updates (which are on the late side, no more of those).

  All in all the diffstat is bigger than ideal at this time, but nothing
  in here seems particularly risky"

* tag 'armsoc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (31 commits)
  reset: sunxi: fix spinlock initialization
  ARM: dts: disable CCI on exynos5420 based arndale-octa
  drivers: bus: check cci device tree node status
  ARM: rockchip: disable jtag/sdmmc autoswitching on rk3288
  ARM: nomadik: fix up leftover device tree pins
  ARM: at91: board-dt-sama5: add phy_fixup to override NAND_Tree
  ARM: at91/dt: sam9263: Add missing clocks to lcdc node
  ARM: at91: sama5d3: dt: correct the sound route
  ARM: at91/dt: sama5d4: fix the timer reg length
  ARM: exynos_defconfig: Enable LM90 driver
  ARM: exynos_defconfig: Enable options for display panel support
  arm: dts: Use pmu_system_controller phandle for dp phy
  ARM: shmobile: sh73a0 legacy: Set .control_parent for all irqpin instances
  ARM: dts: berlin: correct BG2Q's SM GPIO location.
  ARM: dts: berlin: add broken-cd and set bus width for eMMC in Marvell DMP DT
  ARM: dts: berlin: fix io clk and add missing core clk for BG2Q sdhci2 host
  ARM: dts: Revert disabling of smc91x for n900
  ARM: dts: imx51-babbage: Fix ULPI PHY reset modelling
  ARM: dts: dra7-evm: fix qspi device tree partition size
  ARM: omap2plus_defconfig: use CONFIG_CPUFREQ_DT
  ...

Showing 32 changed files Side-by-side Diff

arch/arm/boot/dts/at91sam9263.dtsi
Diff comments   View file @ d0ac5d8
... ... @@ -953,6 +953,8 @@
953 953 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>;
954 954 pinctrl-names = "default";
955 955 pinctrl-0 = <&pinctrl_fb>;
  956 + clocks = <&lcd_clk>, <&lcd_clk>;
  957 + clock-names = "lcdc_clk", "hclk";
956 958 status = "disabled";
957 959 };
958 960  
arch/arm/boot/dts/berlin2q-marvell-dmp.dts
Diff comments   View file @ d0ac5d8
... ... @@ -65,6 +65,8 @@
65 65 };
66 66  
67 67 &sdhci2 {
  68 + broken-cd;
  69 + bus-width = <8>;
68 70 non-removable;
69 71 status = "okay";
70 72 };
arch/arm/boot/dts/berlin2q.dtsi
Diff comments   View file @ d0ac5d8
... ... @@ -83,7 +83,8 @@
83 83 compatible = "mrvl,pxav3-mmc";
84 84 reg = <0xab1000 0x200>;
85 85 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
86   - clocks = <&chip CLKID_SDIO1XIN>;
  86 + clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>;
  87 + clock-names = "io", "core";
87 88 status = "disabled";
88 89 };
89 90  
... ... @@ -348,36 +349,6 @@
348 349 interrupt-parent = <&gic>;
349 350 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
350 351 };
351   -
352   - gpio4: gpio@5000 {
353   - compatible = "snps,dw-apb-gpio";
354   - reg = <0x5000 0x400>;
355   - #address-cells = <1>;
356   - #size-cells = <0>;
357   -
358   - porte: gpio-port@4 {
359   - compatible = "snps,dw-apb-gpio-port";
360   - gpio-controller;
361   - #gpio-cells = <2>;
362   - snps,nr-gpios = <32>;
363   - reg = <0>;
364   - };
365   - };
366   -
367   - gpio5: gpio@c000 {
368   - compatible = "snps,dw-apb-gpio";
369   - reg = <0xc000 0x400>;
370   - #address-cells = <1>;
371   - #size-cells = <0>;
372   -
373   - portf: gpio-port@5 {
374   - compatible = "snps,dw-apb-gpio-port";
375   - gpio-controller;
376   - #gpio-cells = <2>;
377   - snps,nr-gpios = <32>;
378   - reg = <0>;
379   - };
380   - };
381 352 };
382 353  
383 354 chip: chip-control@ea0000 {
... ... @@ -466,6 +437,21 @@
466 437 ranges = <0 0xfc0000 0x10000>;
467 438 interrupt-parent = <&sic>;
468 439  
  440 + sm_gpio1: gpio@5000 {
  441 + compatible = "snps,dw-apb-gpio";
  442 + reg = <0x5000 0x400>;
  443 + #address-cells = <1>;
  444 + #size-cells = <0>;
  445 +
  446 + portf: gpio-port@5 {
  447 + compatible = "snps,dw-apb-gpio-port";
  448 + gpio-controller;
  449 + #gpio-cells = <2>;
  450 + snps,nr-gpios = <32>;
  451 + reg = <0>;
  452 + };
  453 + };
  454 +
469 455 i2c2: i2c@7000 {
470 456 compatible = "snps,designware-i2c";
471 457 #address-cells = <1>;
... ... @@ -514,6 +500,21 @@
514 500 pinctrl-0 = <&uart1_pmux>;
515 501 pinctrl-names = "default";
516 502 status = "disabled";
  503 + };
  504 +
  505 + sm_gpio0: gpio@c000 {
  506 + compatible = "snps,dw-apb-gpio";
  507 + reg = <0xc000 0x400>;
  508 + #address-cells = <1>;
  509 + #size-cells = <0>;
  510 +
  511 + porte: gpio-port@4 {
  512 + compatible = "snps,dw-apb-gpio-port";
  513 + gpio-controller;
  514 + #gpio-cells = <2>;
  515 + snps,nr-gpios = <32>;
  516 + reg = <0>;
  517 + };
517 518 };
518 519  
519 520 sysctrl: pin-controller@d000 {
arch/arm/boot/dts/dra7-evm.dts
Diff comments   View file @ d0ac5d8
... ... @@ -499,23 +499,23 @@
499 499 };
500 500 partition@5 {
501 501 label = "QSPI.u-boot-spl-os";
502   - reg = <0x00140000 0x00010000>;
  502 + reg = <0x00140000 0x00080000>;
503 503 };
504 504 partition@6 {
505 505 label = "QSPI.u-boot-env";
506   - reg = <0x00150000 0x00010000>;
  506 + reg = <0x001c0000 0x00010000>;
507 507 };
508 508 partition@7 {
509 509 label = "QSPI.u-boot-env.backup1";
510   - reg = <0x00160000 0x0010000>;
  510 + reg = <0x001d0000 0x0010000>;
511 511 };
512 512 partition@8 {
513 513 label = "QSPI.kernel";
514   - reg = <0x00170000 0x0800000>;
  514 + reg = <0x001e0000 0x0800000>;
515 515 };
516 516 partition@9 {
517 517 label = "QSPI.file-system";
518   - reg = <0x00970000 0x01690000>;
  518 + reg = <0x009e0000 0x01620000>;
519 519 };
520 520 };
521 521 };
arch/arm/boot/dts/exynos5250.dtsi
Diff comments   View file @ d0ac5d8
... ... @@ -736,7 +736,7 @@
736 736  
737 737 dp_phy: video-phy@10040720 {
738 738 compatible = "samsung,exynos5250-dp-video-phy";
739   - reg = <0x10040720 4>;
  739 + samsung,pmu-syscon = <&pmu_system_controller>;
740 740 #phy-cells = <0>;
741 741 };
742 742  
arch/arm/boot/dts/exynos5420-arndale-octa.dts
Diff comments   View file @ d0ac5d8
... ... @@ -372,4 +372,8 @@
372 372 &usbdrd_dwc3_1 {
373 373 dr_mode = "host";
374 374 };
  375 +
  376 +&cci {
  377 + status = "disabled";
  378 +};
arch/arm/boot/dts/exynos5420.dtsi
Diff comments   View file @ d0ac5d8
... ... @@ -120,7 +120,7 @@
120 120 };
121 121 };
122 122  
123   - cci@10d20000 {
  123 + cci: cci@10d20000 {
124 124 compatible = "arm,cci-400";
125 125 #address-cells = <1>;
126 126 #size-cells = <1>;
... ... @@ -503,8 +503,8 @@
503 503 };
504 504  
505 505 dp_phy: video-phy@10040728 {
506   - compatible = "samsung,exynos5250-dp-video-phy";
507   - reg = <0x10040728 4>;
  506 + compatible = "samsung,exynos5420-dp-video-phy";
  507 + samsung,pmu-syscon = <&pmu_system_controller>;
508 508 #phy-cells = <0>;
509 509 };
510 510  
arch/arm/boot/dts/imx25.dtsi
Diff comments   View file @ d0ac5d8
... ... @@ -162,7 +162,7 @@
162 162 #size-cells = <0>;
163 163 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
164 164 reg = <0x43fa4000 0x4000>;
165   - clocks = <&clks 62>, <&clks 62>;
  165 + clocks = <&clks 78>, <&clks 78>;
166 166 clock-names = "ipg", "per";
167 167 interrupts = <14>;
168 168 status = "disabled";
arch/arm/boot/dts/imx51-babbage.dts
Diff comments   View file @ d0ac5d8
... ... @@ -127,26 +127,14 @@
127 127 #address-cells = <1>;
128 128 #size-cells = <0>;
129 129  
130   - reg_usbh1_vbus: regulator@0 {
  130 + reg_hub_reset: regulator@0 {
131 131 compatible = "regulator-fixed";
132 132 pinctrl-names = "default";
133   - pinctrl-0 = <&pinctrl_usbh1reg>;
  133 + pinctrl-0 = <&pinctrl_usbotgreg>;
134 134 reg = <0>;
135   - regulator-name = "usbh1_vbus";
  135 + regulator-name = "hub_reset";
136 136 regulator-min-microvolt = <5000000>;
137 137 regulator-max-microvolt = <5000000>;
138   - gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>;
139   - enable-active-high;
140   - };
141   -
142   - reg_usbotg_vbus: regulator@1 {
143   - compatible = "regulator-fixed";
144   - pinctrl-names = "default";
145   - pinctrl-0 = <&pinctrl_usbotgreg>;
146   - reg = <1>;
147   - regulator-name = "usbotg_vbus";
148   - regulator-min-microvolt = <5000000>;
149   - regulator-max-microvolt = <5000000>;
150 138 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
151 139 enable-active-high;
152 140 };
... ... @@ -176,6 +164,7 @@
176 164 reg = <0>;
177 165 clocks = <&clks IMX5_CLK_DUMMY>;
178 166 clock-names = "main_clk";
  167 + reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
179 168 };
180 169 };
181 170 };
... ... @@ -419,7 +408,7 @@
419 408 &usbh1 {
420 409 pinctrl-names = "default";
421 410 pinctrl-0 = <&pinctrl_usbh1>;
422   - vbus-supply = <&reg_usbh1_vbus>;
  411 + vbus-supply = <&reg_hub_reset>;
423 412 fsl,usbphy = <&usbh1phy>;
424 413 phy_type = "ulpi";
425 414 status = "okay";
... ... @@ -429,7 +418,6 @@
429 418 dr_mode = "otg";
430 419 disable-over-current;
431 420 phy_type = "utmi_wide";
432   - vbus-supply = <&reg_usbotg_vbus>;
433 421 status = "okay";
434 422 };
435 423  
arch/arm/boot/dts/imx6qdl.dtsi
Diff comments   View file @ d0ac5d8
... ... @@ -335,8 +335,8 @@
335 335 vpu: vpu@02040000 {
336 336 compatible = "cnm,coda960";
337 337 reg = <0x02040000 0x3c000>;
338   - interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
339   - <0 12 IRQ_TYPE_LEVEL_HIGH>;
  338 + interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
  339 + <0 3 IRQ_TYPE_LEVEL_HIGH>;
340 340 interrupt-names = "bit", "jpeg";
341 341 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
342 342 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>,
arch/arm/boot/dts/ls1021a.dtsi
Diff comments   View file @ d0ac5d8
... ... @@ -142,6 +142,7 @@
142 142 scfg: scfg@1570000 {
143 143 compatible = "fsl,ls1021a-scfg", "syscon";
144 144 reg = <0x0 0x1570000 0x0 0x10000>;
  145 + big-endian;
145 146 };
146 147  
147 148 clockgen: clocking@1ee1000 {
arch/arm/boot/dts/omap3-n900.dts
Diff comments   View file @ d0ac5d8
... ... @@ -700,11 +700,9 @@
700 700 };
701 701 };
702 702  
  703 + /* Ethernet is on some early development boards and qemu */
703 704 ethernet@gpmc {
704 705 compatible = "smsc,lan91c94";
705   -
706   - status = "disabled";
707   -
708 706 interrupt-parent = <&gpio2>;
709 707 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */
710 708 reg = <1 0x300 0xf>; /* 16 byte IO range at offset 0x300 */
arch/arm/boot/dts/rk3288-evb.dtsi
Diff comments   View file @ d0ac5d8
... ... @@ -155,6 +155,15 @@
155 155 };
156 156  
157 157 &pinctrl {
  158 + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
  159 + drive-strength = <8>;
  160 + };
  161 +
  162 + pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
  163 + bias-pull-up;
  164 + drive-strength = <8>;
  165 + };
  166 +
158 167 backlight {
159 168 bl_en: bl-en {
160 169 rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
... ... @@ -170,6 +179,27 @@
170 179 pmic {
171 180 pmic_int: pmic-int {
172 181 rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
  182 + };
  183 + };
  184 +
  185 + sdmmc {
  186 + /*
  187 + * Default drive strength isn't enough to achieve even
  188 + * high-speed mode on EVB board so bump up to 8ma.
  189 + */
  190 + sdmmc_bus4: sdmmc-bus4 {
  191 + rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
  192 + <6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
  193 + <6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
  194 + <6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
  195 + };
  196 +
  197 + sdmmc_clk: sdmmc-clk {
  198 + rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
  199 + };
  200 +
  201 + sdmmc_cmd: sdmmc-cmd {
  202 + rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
173 203 };
174 204 };
175 205  
arch/arm/boot/dts/sama5d3xmb.dtsi
Diff comments   View file @ d0ac5d8
... ... @@ -176,7 +176,7 @@
176 176 "Headphone Jack", "HPOUTR",
177 177 "IN2L", "Line In Jack",
178 178 "IN2R", "Line In Jack",
179   - "MICBIAS", "IN1L",
  179 + "Mic", "MICBIAS",
180 180 "IN1L", "Mic";
181 181  
182 182 atmel,ssc-controller = <&ssc0>;
arch/arm/boot/dts/sama5d4.dtsi
Diff comments   View file @ d0ac5d8
... ... @@ -1008,7 +1008,7 @@
1008 1008  
1009 1009 pit: timer@fc068630 {
1010 1010 compatible = "atmel,at91sam9260-pit";
1011   - reg = <0xfc068630 0xf>;
  1011 + reg = <0xfc068630 0x10>;
1012 1012 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1013 1013 clocks = <&h32ck>;
1014 1014 };
arch/arm/boot/dts/ste-nomadik-nhk15.dts
Diff comments   View file @ d0ac5d8
... ... @@ -25,11 +25,11 @@
25 25 stmpe2401_1 {
26 26 stmpe2401_1_nhk_mode: stmpe2401_1_nhk {
27 27 nhk_cfg1 {
28   - ste,pins = "GPIO76_B20"; // IRQ line
  28 + pins = "GPIO76_B20"; // IRQ line
29 29 ste,input = <0>;
30 30 };
31 31 nhk_cfg2 {
32   - ste,pins = "GPIO77_B8"; // reset line
  32 + pins = "GPIO77_B8"; // reset line
33 33 ste,output = <1>;
34 34 };
35 35 };
36 36  
... ... @@ -37,11 +37,11 @@
37 37 stmpe2401_2 {
38 38 stmpe2401_2_nhk_mode: stmpe2401_2_nhk {
39 39 nhk_cfg1 {
40   - ste,pins = "GPIO78_A8"; // IRQ line
  40 + pins = "GPIO78_A8"; // IRQ line
41 41 ste,input = <0>;
42 42 };
43 43 nhk_cfg2 {
44   - ste,pins = "GPIO79_C9"; // reset line
  44 + pins = "GPIO79_C9"; // reset line
45 45 ste,output = <1>;
46 46 };
47 47 };
arch/arm/configs/exynos_defconfig
Diff comments   View file @ d0ac5d8
... ... @@ -84,7 +84,8 @@
84 84 CONFIG_POWER_SUPPLY=y
85 85 CONFIG_BATTERY_SBS=y
86 86 CONFIG_CHARGER_TPS65090=y
87   -# CONFIG_HWMON is not set
  87 +CONFIG_HWMON=y
  88 +CONFIG_SENSORS_LM90=y
88 89 CONFIG_THERMAL=y
89 90 CONFIG_EXYNOS_THERMAL=y
90 91 CONFIG_EXYNOS_THERMAL_CORE=y
91 92  
... ... @@ -109,11 +110,26 @@
109 110 CONFIG_REGULATOR_S2MPS11=y
110 111 CONFIG_REGULATOR_S5M8767=y
111 112 CONFIG_REGULATOR_TPS65090=y
  113 +CONFIG_DRM=y
  114 +CONFIG_DRM_BRIDGE=y
  115 +CONFIG_DRM_PTN3460=y
  116 +CONFIG_DRM_PS8622=y
  117 +CONFIG_DRM_EXYNOS=y
  118 +CONFIG_DRM_EXYNOS_FIMD=y
  119 +CONFIG_DRM_EXYNOS_DP=y
  120 +CONFIG_DRM_PANEL=y
  121 +CONFIG_DRM_PANEL_SIMPLE=y
112 122 CONFIG_FB=y
113 123 CONFIG_FB_MODE_HELPERS=y
114 124 CONFIG_FB_SIMPLE=y
115 125 CONFIG_EXYNOS_VIDEO=y
116 126 CONFIG_EXYNOS_MIPI_DSI=y
  127 +CONFIG_BACKLIGHT_LCD_SUPPORT=y
  128 +CONFIG_LCD_CLASS_DEVICE=y
  129 +CONFIG_LCD_PLATFORM=y
  130 +CONFIG_BACKLIGHT_CLASS_DEVICE=y
  131 +CONFIG_BACKLIGHT_GENERIC=y
  132 +CONFIG_BACKLIGHT_PWM=y
117 133 CONFIG_FRAMEBUFFER_CONSOLE=y
118 134 CONFIG_FONTS=y
119 135 CONFIG_FONT_7x14=y
arch/arm/configs/omap2plus_defconfig
Diff comments   View file @ d0ac5d8
... ... @@ -68,7 +68,7 @@
68 68 CONFIG_CPU_FREQ_GOV_POWERSAVE=y
69 69 CONFIG_CPU_FREQ_GOV_USERSPACE=y
70 70 CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
71   -CONFIG_GENERIC_CPUFREQ_CPU0=y
  71 +CONFIG_CPUFREQ_DT=y
72 72 # CONFIG_ARM_OMAP2PLUS_CPUFREQ is not set
73 73 CONFIG_CPU_IDLE=y
74 74 CONFIG_BINFMT_MISC=y
arch/arm/mach-at91/board-dt-sama5.c
Diff comments   View file @ d0ac5d8
... ... @@ -17,6 +17,7 @@
17 17 #include <linux/of_platform.h>
18 18 #include <linux/phy.h>
19 19 #include <linux/clk-provider.h>
  20 +#include <linux/phy.h>
20 21  
21 22 #include <asm/setup.h>
22 23 #include <asm/irq.h>
23 24  
... ... @@ -26,8 +27,25 @@
26 27  
27 28 #include "generic.h"
28 29  
  30 +static int ksz8081_phy_fixup(struct phy_device *phy)
  31 +{
  32 + int value;
  33 +
  34 + value = phy_read(phy, 0x16);
  35 + value &= ~0x20;
  36 + phy_write(phy, 0x16, value);
  37 +
  38 + return 0;
  39 +}
  40 +
29 41 static void __init sama5_dt_device_init(void)
30 42 {
  43 + if (of_machine_is_compatible("atmel,sama5d4ek") &&
  44 + IS_ENABLED(CONFIG_PHYLIB)) {
  45 + phy_register_fixup_for_id("fc028000.etherne:00",
  46 + ksz8081_phy_fixup);
  47 + }
  48 +
31 49 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
32 50 }
33 51  
arch/arm/mach-imx/clk-imx6q.c
Diff comments   View file @ d0ac5d8
... ... @@ -144,7 +144,7 @@
144 144 post_div_table[1].div = 1;
145 145 post_div_table[2].div = 1;
146 146 video_div_table[1].div = 1;
147   - video_div_table[2].div = 1;
  147 + video_div_table[3].div = 1;
148 148 }
149 149  
150 150 clk[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
arch/arm/mach-imx/clk-imx6sx.c
Diff comments   View file @ d0ac5d8
... ... @@ -558,6 +558,9 @@
558 558 clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
559 559 clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
560 560  
  561 + clk_set_parent(clks[IMX6SX_CLK_QSPI1_SEL], clks[IMX6SX_CLK_PLL2_BUS]);
  562 + clk_set_parent(clks[IMX6SX_CLK_QSPI2_SEL], clks[IMX6SX_CLK_PLL2_BUS]);
  563 +
561 564 /* Set initial power mode */
562 565 imx6q_set_lpm(WAIT_CLOCKED);
563 566 }
arch/arm/mach-omap2/board-generic.c
Diff comments   View file @ d0ac5d8
... ... @@ -77,6 +77,24 @@
77 77 #endif
78 78  
79 79 #ifdef CONFIG_ARCH_OMAP3
  80 +/* Some boards need board name for legacy userspace in /proc/cpuinfo */
  81 +static const char *const n900_boards_compat[] __initconst = {
  82 + "nokia,omap3-n900",
  83 + NULL,
  84 +};
  85 +
  86 +DT_MACHINE_START(OMAP3_N900_DT, "Nokia RX-51 board")
  87 + .reserve = omap_reserve,
  88 + .map_io = omap3_map_io,
  89 + .init_early = omap3430_init_early,
  90 + .init_machine = omap_generic_init,
  91 + .init_late = omap3_init_late,
  92 + .init_time = omap3_sync32k_timer_init,
  93 + .dt_compat = n900_boards_compat,
  94 + .restart = omap3xxx_restart,
  95 +MACHINE_END
  96 +
  97 +/* Generic omap3 boards, most boards can use these */
80 98 static const char *const omap3_boards_compat[] __initconst = {
81 99 "ti,omap3430",
82 100 "ti,omap3",
arch/arm/mach-omap2/common.h
Diff comments   View file @ d0ac5d8
... ... @@ -249,6 +249,7 @@
249 249 extern struct smp_operations omap4_smp_ops;
250 250  
251 251 extern void omap5_secondary_startup(void);
  252 +extern void omap5_secondary_hyp_startup(void);
252 253 #endif
253 254  
254 255 #if defined(CONFIG_SMP) && defined(CONFIG_PM)
arch/arm/mach-omap2/control.h
Diff comments   View file @ d0ac5d8
... ... @@ -286,6 +286,10 @@
286 286 #define OMAP5XXX_CONTROL_STATUS 0x134
287 287 #define OMAP5_DEVICETYPE_MASK (0x7 << 6)
288 288  
  289 +/* DRA7XX CONTROL CORE BOOTSTRAP */
  290 +#define DRA7_CTRL_CORE_BOOTSTRAP 0x6c4
  291 +#define DRA7_SPEEDSELECT_MASK (0x3 << 8)
  292 +
289 293 /*
290 294 * REVISIT: This list of registers is not comprehensive - there are more
291 295 * that should be added.
arch/arm/mach-omap2/omap-headsmp.S
Diff comments   View file @ d0ac5d8
... ... @@ -22,6 +22,7 @@
22 22  
23 23 /* Physical address needed since MMU not enabled yet on secondary core */
24 24 #define AUX_CORE_BOOT0_PA 0x48281800
  25 +#define API_HYP_ENTRY 0x102
25 26  
26 27 /*
27 28 * OMAP5 specific entry point for secondary CPU to jump from ROM
... ... @@ -40,6 +41,26 @@
40 41 bne wait
41 42 b secondary_startup
42 43 ENDPROC(omap5_secondary_startup)
  44 +/*
  45 + * Same as omap5_secondary_startup except we call into the ROM to
  46 + * enable HYP mode first. This is called instead of
  47 + * omap5_secondary_startup if the primary CPU was put into HYP mode by
  48 + * the boot loader.
  49 + */
  50 +ENTRY(omap5_secondary_hyp_startup)
  51 +wait_2: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
  52 + ldr r0, [r2]
  53 + mov r0, r0, lsr #5
  54 + mrc p15, 0, r4, c0, c0, 5
  55 + and r4, r4, #0x0f
  56 + cmp r0, r4
  57 + bne wait_2
  58 + ldr r12, =API_HYP_ENTRY
  59 + adr r0, hyp_boot
  60 + smc #0
  61 +hyp_boot:
  62 + b secondary_startup
  63 +ENDPROC(omap5_secondary_hyp_startup)
43 64 /*
44 65 * OMAP4 specific entry point for secondary CPU to jump from ROM
45 66 * code. This routine also provides a holding flag into which
arch/arm/mach-omap2/omap-smp.c
Diff comments   View file @ d0ac5d8
... ... @@ -22,6 +22,7 @@
22 22 #include <linux/irqchip/arm-gic.h>
23 23  
24 24 #include <asm/smp_scu.h>
  25 +#include <asm/virt.h>
25 26  
26 27 #include "omap-secure.h"
27 28 #include "omap-wakeupgen.h"
... ... @@ -227,8 +228,16 @@
227 228 if (omap_secure_apis_support())
228 229 omap_auxcoreboot_addr(virt_to_phys(startup_addr));
229 230 else
230   - writel_relaxed(virt_to_phys(omap5_secondary_startup),
231   - base + OMAP_AUX_CORE_BOOT_1);
  231 + /*
  232 + * If the boot CPU is in HYP mode then start secondary
  233 + * CPU in HYP mode as well.
  234 + */
  235 + if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE)
  236 + writel_relaxed(virt_to_phys(omap5_secondary_hyp_startup),
  237 + base + OMAP_AUX_CORE_BOOT_1);
  238 + else
  239 + writel_relaxed(virt_to_phys(omap5_secondary_startup),
  240 + base + OMAP_AUX_CORE_BOOT_1);
232 241  
233 242 }
234 243  
arch/arm/mach-omap2/timer.c
Diff comments   View file @ d0ac5d8
... ... @@ -54,6 +54,7 @@
54 54  
55 55 #include "soc.h"
56 56 #include "common.h"
  57 +#include "control.h"
57 58 #include "powerdomain.h"
58 59 #include "omap-secure.h"
59 60  
... ... @@ -496,7 +497,8 @@
496 497 void __iomem *base;
497 498 static struct clk *sys_clk;
498 499 unsigned long rate;
499   - unsigned int reg, num, den;
  500 + unsigned int reg;
  501 + unsigned long long num, den;
500 502  
501 503 base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
502 504 if (!base) {
503 505  
504 506  
... ... @@ -511,13 +513,42 @@
511 513 }
512 514  
513 515 rate = clk_get_rate(sys_clk);
  516 +
  517 + if (soc_is_dra7xx()) {
  518 + /*
  519 + * Errata i856 says the 32.768KHz crystal does not start at
  520 + * power on, so the CPU falls back to an emulated 32KHz clock
  521 + * based on sysclk / 610 instead. This causes the master counter
  522 + * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2
  523 + * (OR sysclk * 75 / 244)
  524 + *
  525 + * This affects at least the DRA7/AM572x 1.0, 1.1 revisions.
  526 + * Of course any board built without a populated 32.768KHz
  527 + * crystal would also need this fix even if the CPU is fixed
  528 + * later.
  529 + *
  530 + * Either case can be detected by using the two speedselect bits
  531 + * If they are not 0, then the 32.768KHz clock driving the
  532 + * coarse counter that corrects the fine counter every time it
  533 + * ticks is actually rate/610 rather than 32.768KHz and we
  534 + * should compensate to avoid the 570ppm (at 20MHz, much worse
  535 + * at other rates) too fast system time.
  536 + */
  537 + reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);
  538 + if (reg & DRA7_SPEEDSELECT_MASK) {
  539 + num = 75;
  540 + den = 244;
  541 + goto sysclk1_based;
  542 + }
  543 + }
  544 +
514 545 /* Numerator/denumerator values refer TRM Realtime Counter section */
515 546 switch (rate) {
516   - case 1200000:
  547 + case 12000000:
517 548 num = 64;
518 549 den = 125;
519 550 break;
520   - case 1300000:
  551 + case 13000000:
521 552 num = 768;
522 553 den = 1625;
523 554 break;
524 555  
... ... @@ -529,11 +560,11 @@
529 560 num = 192;
530 561 den = 625;
531 562 break;
532   - case 2600000:
  563 + case 26000000:
533 564 num = 384;
534 565 den = 1625;
535 566 break;
536   - case 2700000:
  567 + case 27000000:
537 568 num = 256;
538 569 den = 1125;
539 570 break;
... ... @@ -545,6 +576,7 @@
545 576 break;
546 577 }
547 578  
  579 +sysclk1_based:
548 580 /* Program numerator and denumerator registers */
549 581 reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
550 582 NUMERATOR_DENUMERATOR_MASK;
... ... @@ -556,7 +588,7 @@
556 588 reg |= den;
557 589 writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
558 590  
559   - arch_timer_freq = (rate / den) * num;
  591 + arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den);
560 592 set_cntfreq();
561 593  
562 594 iounmap(base);
arch/arm/mach-rockchip/rockchip.c
Diff comments   View file @ d0ac5d8
... ... @@ -19,11 +19,37 @@
19 19 #include <linux/init.h>
20 20 #include <linux/of_platform.h>
21 21 #include <linux/irqchip.h>
  22 +#include <linux/clk-provider.h>
  23 +#include <linux/clocksource.h>
  24 +#include <linux/mfd/syscon.h>
  25 +#include <linux/regmap.h>
22 26 #include <asm/mach/arch.h>
23 27 #include <asm/mach/map.h>
24 28 #include <asm/hardware/cache-l2x0.h>
25 29 #include "core.h"
26 30  
  31 +#define RK3288_GRF_SOC_CON0 0x244
  32 +
  33 +static void __init rockchip_timer_init(void)
  34 +{
  35 + if (of_machine_is_compatible("rockchip,rk3288")) {
  36 + struct regmap *grf;
  37 +
  38 + /*
  39 + * Disable auto jtag/sdmmc switching that causes issues
  40 + * with the mmc controllers making them unreliable
  41 + */
  42 + grf = syscon_regmap_lookup_by_compatible("rockchip,rk3288-grf");
  43 + if (!IS_ERR(grf))
  44 + regmap_write(grf, RK3288_GRF_SOC_CON0, 0x10000000);
  45 + else
  46 + pr_err("rockchip: could not get grf syscon\n");
  47 + }
  48 +
  49 + of_clk_init(NULL);
  50 + clocksource_of_init();
  51 +}
  52 +
27 53 static void __init rockchip_dt_init(void)
28 54 {
29 55 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
... ... @@ -42,6 +68,7 @@
42 68 DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)")
43 69 .l2c_aux_val = 0,
44 70 .l2c_aux_mask = ~0,
  71 + .init_time = rockchip_timer_init,
45 72 .dt_compat = rockchip_board_dt_compat,
46 73 .init_machine = rockchip_dt_init,
47 74 MACHINE_END
arch/arm/mach-shmobile/setup-r8a7740.c
Diff comments   View file @ d0ac5d8
... ... @@ -800,7 +800,14 @@
800 800 void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
801 801 void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
802 802  
  803 +#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
  804 + void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000);
  805 + void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000);
  806 +
  807 + gic_init(0, 29, gic_dist_base, gic_cpu_base);
  808 +#else
803 809 irqchip_init();
  810 +#endif
804 811  
805 812 /* route signals to GIC */
806 813 iowrite32(0x0, pfc_inta_ctrl);
arch/arm/mach-shmobile/setup-sh73a0.c
Diff comments   View file @ d0ac5d8
... ... @@ -595,6 +595,7 @@
595 595  
596 596 static struct renesas_intc_irqpin_config irqpin0_platform_data = {
597 597 .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
  598 + .control_parent = true,
598 599 };
599 600  
600 601 static struct resource irqpin0_resources[] = {
... ... @@ -656,6 +657,7 @@
656 657  
657 658 static struct renesas_intc_irqpin_config irqpin2_platform_data = {
658 659 .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
  660 + .control_parent = true,
659 661 };
660 662  
661 663 static struct resource irqpin2_resources[] = {
... ... @@ -686,6 +688,7 @@
686 688  
687 689 static struct renesas_intc_irqpin_config irqpin3_platform_data = {
688 690 .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
  691 + .control_parent = true,
689 692 };
690 693  
691 694 static struct resource irqpin3_resources[] = {
drivers/bus/arm-cci.c
Diff comments   View file @ d0ac5d8
... ... @@ -1312,6 +1312,9 @@
1312 1312 if (!np)
1313 1313 return -ENODEV;
1314 1314  
  1315 + if (!of_device_is_available(np))
  1316 + return -ENODEV;
  1317 +
1315 1318 cci_config = of_match_node(arm_cci_matches, np)->data;
1316 1319 if (!cci_config)
1317 1320 return -ENODEV;
drivers/reset/reset-sunxi.c
Diff comments   View file @ d0ac5d8
... ... @@ -102,6 +102,8 @@
102 102 goto err_alloc;
103 103 }
104 104  
  105 + spin_lock_init(&data->lock);
  106 +
105 107 data->rcdev.owner = THIS_MODULE;
106 108 data->rcdev.nr_resets = size * 32;
107 109 data->rcdev.ops = &sunxi_reset_ops;
... ... @@ -156,6 +158,8 @@
156 158 data->membase = devm_ioremap_resource(&pdev->dev, res);
157 159 if (IS_ERR(data->membase))
158 160 return PTR_ERR(data->membase);
  161 +
  162 + spin_lock_init(&data->lock);
159 163  
160 164 data->rcdev.owner = THIS_MODULE;
161 165 data->rcdev.nr_resets = resource_size(res) * 32;