Commit d2212b4dce596fee83e5c523400bf084f4cc816c
Committed by
Linus Torvalds
Linus Torvalds
1 parent
4b97280675
Exists in
master
and in
20 other branches
lockref: allow relaxed cmpxchg64 variant for lockless updates
The 64-bit cmpxchg operation on the lockref is ordered by virtue of hazarding between the cmpxchg operation and the reference count manipulation. On weakly ordered memory architectures (such as ARM), it can be of great benefit to omit the barrier instructions where they are not needed. This patch moves the lockless lockref code over to a cmpxchg64_relaxed operation, which doesn't provide barrier semantics. If the operation isn't defined, we simply #define it as the usual 64-bit cmpxchg macro. Cc: Waiman Long <Waiman.Long@hp.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Showing 1 changed file with 11 additions and 2 deletions Side-by-side Diff
lib/lockref.c
| ... | ... | @@ -4,6 +4,14 @@ |
| 4 | 4 | #ifdef CONFIG_CMPXCHG_LOCKREF |
| 5 | 5 | |
| 6 | 6 | /* |
| 7 | + * Allow weakly-ordered memory architectures to provide barrier-less | |
| 8 | + * cmpxchg semantics for lockref updates. | |
| 9 | + */ | |
| 10 | +#ifndef cmpxchg64_relaxed | |
| 11 | +# define cmpxchg64_relaxed cmpxchg64 | |
| 12 | +#endif | |
| 13 | + | |
| 14 | +/* | |
| 7 | 15 | * Note that the "cmpxchg()" reloads the "old" value for the |
| 8 | 16 | * failure case. |
| 9 | 17 | */ |
| ... | ... | @@ -14,8 +22,9 @@ |
| 14 | 22 | while (likely(arch_spin_value_unlocked(old.lock.rlock.raw_lock))) { \ |
| 15 | 23 | struct lockref new = old, prev = old; \ |
| 16 | 24 | CODE \ |
| 17 | - old.lock_count = cmpxchg64(&lockref->lock_count, \ | |
| 18 | - old.lock_count, new.lock_count); \ | |
| 25 | + old.lock_count = cmpxchg64_relaxed(&lockref->lock_count, \ | |
| 26 | + old.lock_count, \ | |
| 27 | + new.lock_count); \ | |
| 19 | 28 | if (likely(old.lock_count == prev.lock_count)) { \ |
| 20 | 29 | SUCCESS; \ |
| 21 | 30 | } \ |