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Commit d5b481842040c799a4e5cec6089d8853d8f540f9

Authored by Jean-Christophe PLAGNIOL-VILLARD
Committed by Greg Kroah-Hartman
1 parent a916db4b25

pinctrl: at91: allow to have disabled gpio bank 

commit a0b957f306fa4d0a39f4ffe5e5e25e856e6be46e upstream.

Today we expect that all the bank are enabled, and count the number of banks
used by the pinctrl based on it instead of using the last bank id enabled.

So switch to it, set the chained IRQ at runtime based on enabled banks
and wait only the number of enabled gpio controllers at probe time.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

Showing 1 changed file with 55 additions and 53 deletions Side-by-side Diff

drivers/pinctrl/pinctrl-at91.c
Diff comments   View file @ d5b4818
... ... @@ -179,7 +179,7 @@
179 179 struct device *dev;
180 180 struct pinctrl_dev *pctl;
181 181  
182   - int nbanks;
  182 + int nactive_banks;
183 183  
184 184 uint32_t *mux_mask;
185 185 int nmux;
186 186  
187 187  
... ... @@ -655,12 +655,18 @@
655 655 int mux;
656 656  
657 657 /* check if it's a valid config */
658   - if (pin->bank >= info->nbanks) {
  658 + if (pin->bank >= gpio_banks) {
659 659 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
660   - name, index, pin->bank, info->nbanks);
  660 + name, index, pin->bank, gpio_banks);
661 661 return -EINVAL;
662 662 }
663 663  
  664 + if (!gpio_chips[pin->bank]) {
  665 + dev_err(info->dev, "%s: pin conf %d bank_id %d not enabled\n",
  666 + name, index, pin->bank);
  667 + return -ENXIO;
  668 + }
  669 +
664 670 if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
665 671 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
666 672 name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
... ... @@ -983,7 +989,8 @@
983 989  
984 990 for_each_child_of_node(np, child) {
985 991 if (of_device_is_compatible(child, gpio_compat)) {
986   - info->nbanks++;
  992 + if (of_device_is_available(child))
  993 + info->nactive_banks++;
987 994 } else {
988 995 info->nfunctions++;
989 996 info->ngroups += of_get_child_count(child);
990 997  
... ... @@ -1005,11 +1012,11 @@
1005 1012 }
1006 1013  
1007 1014 size /= sizeof(*list);
1008   - if (!size || size % info->nbanks) {
1009   - dev_err(info->dev, "wrong mux mask array should be by %d\n", info->nbanks);
  1015 + if (!size || size % gpio_banks) {
  1016 + dev_err(info->dev, "wrong mux mask array should be by %d\n", gpio_banks);
1010 1017 return -EINVAL;
1011 1018 }
1012   - info->nmux = size / info->nbanks;
  1019 + info->nmux = size / gpio_banks;
1013 1020  
1014 1021 info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL);
1015 1022 if (!info->mux_mask) {
... ... @@ -1133,7 +1140,7 @@
1133 1140 of_match_device(at91_pinctrl_of_match, &pdev->dev)->data;
1134 1141 at91_pinctrl_child_count(info, np);
1135 1142  
1136   - if (info->nbanks < 1) {
  1143 + if (gpio_banks < 1) {
1137 1144 dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n");
1138 1145 return -EINVAL;
1139 1146 }
... ... @@ -1146,7 +1153,7 @@
1146 1153  
1147 1154 dev_dbg(&pdev->dev, "mux-mask\n");
1148 1155 tmp = info->mux_mask;
1149   - for (i = 0; i < info->nbanks; i++) {
  1156 + for (i = 0; i < gpio_banks; i++) {
1150 1157 for (j = 0; j < info->nmux; j++, tmp++) {
1151 1158 dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
1152 1159 }
... ... @@ -1164,7 +1171,7 @@
1164 1171 if (!info->groups)
1165 1172 return -ENOMEM;
1166 1173  
1167   - dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks);
  1174 + dev_dbg(&pdev->dev, "nbanks = %d\n", gpio_banks);
1168 1175 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1169 1176 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1170 1177  
... ... @@ -1187,7 +1194,7 @@
1187 1194 {
1188 1195 struct at91_pinctrl *info;
1189 1196 struct pinctrl_pin_desc *pdesc;
1190   - int ret, i, j, k;
  1197 + int ret, i, j, k, ngpio_chips_enabled = 0;
1191 1198  
1192 1199 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1193 1200 if (!info)
1194 1201  
1195 1202  
... ... @@ -1202,23 +1209,27 @@
1202 1209 * to obtain references to the struct gpio_chip * for them, and we
1203 1210 * need this to proceed.
1204 1211 */
1205   - for (i = 0; i < info->nbanks; i++) {
1206   - if (!gpio_chips[i]) {
1207   - dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
1208   - devm_kfree(&pdev->dev, info);
1209   - return -EPROBE_DEFER;
1210   - }
  1212 + for (i = 0; i < gpio_banks; i++)
  1213 + if (gpio_chips[i])
  1214 + ngpio_chips_enabled++;
  1215 +
  1216 + if (ngpio_chips_enabled < info->nactive_banks) {
  1217 + dev_warn(&pdev->dev,
  1218 + "All GPIO chips are not registered yet (%d/%d)\n",
  1219 + ngpio_chips_enabled, info->nactive_banks);
  1220 + devm_kfree(&pdev->dev, info);
  1221 + return -EPROBE_DEFER;
1211 1222 }
1212 1223  
1213 1224 at91_pinctrl_desc.name = dev_name(&pdev->dev);
1214   - at91_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK;
  1225 + at91_pinctrl_desc.npins = gpio_banks * MAX_NB_GPIO_PER_BANK;
1215 1226 at91_pinctrl_desc.pins = pdesc =
1216 1227 devm_kzalloc(&pdev->dev, sizeof(*pdesc) * at91_pinctrl_desc.npins, GFP_KERNEL);
1217 1228  
1218 1229 if (!at91_pinctrl_desc.pins)
1219 1230 return -ENOMEM;
1220 1231  
1221   - for (i = 0 , k = 0; i < info->nbanks; i++) {
  1232 + for (i = 0, k = 0; i < gpio_banks; i++) {
1222 1233 for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
1223 1234 pdesc->number = k;
1224 1235 pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j);
... ... @@ -1236,8 +1247,9 @@
1236 1247 }
1237 1248  
1238 1249 /* We will handle a range of GPIO pins */
1239   - for (i = 0; i < info->nbanks; i++)
1240   - pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
  1250 + for (i = 0; i < gpio_banks; i++)
  1251 + if (gpio_chips[i])
  1252 + pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
1241 1253  
1242 1254 dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");
1243 1255  
1244 1256  
... ... @@ -1614,9 +1626,10 @@
1614 1626 static int at91_gpio_of_irq_setup(struct platform_device *pdev,
1615 1627 struct at91_gpio_chip *at91_gpio)
1616 1628 {
  1629 + struct gpio_chip *gpiochip_prev = NULL;
1617 1630 struct at91_gpio_chip *prev = NULL;
1618 1631 struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq);
1619   - int ret;
  1632 + int ret, i;
1620 1633  
1621 1634 at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
1622 1635  
1623 1636  
1624 1637  
1625 1638  
1626 1639  
... ... @@ -1642,24 +1655,33 @@
1642 1655 return ret;
1643 1656 }
1644 1657  
1645   - /* Setup chained handler */
1646   - if (at91_gpio->pioc_idx)
1647   - prev = gpio_chips[at91_gpio->pioc_idx - 1];
1648   -
1649 1658 /* The top level handler handles one bank of GPIOs, except
1650 1659 * on some SoC it can handle up to three...
1651 1660 * We only set up the handler for the first of the list.
1652 1661 */
1653   - if (prev && prev->next == at91_gpio)
  1662 + gpiochip_prev = irq_get_handler_data(at91_gpio->pioc_virq);
  1663 + if (!gpiochip_prev) {
  1664 + /* Then register the chain on the parent IRQ */
  1665 + gpiochip_set_chained_irqchip(&at91_gpio->chip,
  1666 + &gpio_irqchip,
  1667 + at91_gpio->pioc_virq,
  1668 + gpio_irq_handler);
1654 1669 return 0;
  1670 + }
1655 1671  
1656   - /* Then register the chain on the parent IRQ */
1657   - gpiochip_set_chained_irqchip(&at91_gpio->chip,
1658   - &gpio_irqchip,
1659   - at91_gpio->pioc_virq,
1660   - gpio_irq_handler);
  1672 + prev = container_of(gpiochip_prev, struct at91_gpio_chip, chip);
1661 1673  
1662   - return 0;
  1674 + /* we can only have 2 banks before */
  1675 + for (i = 0; i < 2; i++) {
  1676 + if (prev->next) {
  1677 + prev = prev->next;
  1678 + } else {
  1679 + prev->next = at91_gpio;
  1680 + return 0;
  1681 + }
  1682 + }
  1683 +
  1684 + return -EINVAL;
1663 1685 }
1664 1686  
1665 1687 /* This structure is replicated for each GPIO block allocated at probe time */
... ... @@ -1676,24 +1698,6 @@
1676 1698 .ngpio = MAX_NB_GPIO_PER_BANK,
1677 1699 };
1678 1700  
1679   -static void at91_gpio_probe_fixup(void)
1680   -{
1681   - unsigned i;
1682   - struct at91_gpio_chip *at91_gpio, *last = NULL;
1683   -
1684   - for (i = 0; i < gpio_banks; i++) {
1685   - at91_gpio = gpio_chips[i];
1686   -
1687   - /*
1688   - * GPIO controller are grouped on some SoC:
1689   - * PIOC, PIOD and PIOE can share the same IRQ line
1690   - */
1691   - if (last && last->pioc_virq == at91_gpio->pioc_virq)
1692   - last->next = at91_gpio;
1693   - last = at91_gpio;
1694   - }
1695   -}
1696   -
1697 1701 static struct of_device_id at91_gpio_of_match[] = {
1698 1702 { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
1699 1703 { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
... ... @@ -1805,8 +1809,6 @@
1805 1809  
1806 1810 gpio_chips[alias_idx] = at91_chip;
1807 1811 gpio_banks = max(gpio_banks, alias_idx + 1);
1808   -
1809   - at91_gpio_probe_fixup();
1810 1812  
1811 1813 ret = at91_gpio_of_irq_setup(pdev, at91_chip);
1812 1814 if (ret)