Eric Lee / smarc-ti-linux-kernel

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Commit dad3df2044b78ba68a92bf78e38a408bab80ff61

Authored by Harvey Harrison
Committed by Herbert Xu
1 parent 664134d291
Exists in master and in 20 other branches dlt-processor-sdk-linux-03.00.00.04, newt-ti-linux-3.12.y, processor-sdk-linux-01.00.00, processor-sdk-linux-02.00.01, smarc-ti-linux-3.12.10, smarc-ti-linux-3.12.y, smarc-ti-linux-3.14.y, smarc-ti-linux-3.15.y, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04, ti-linux-3.12.y, ti-linux-3.14.y, ti-linux-3.15.y, ti-lsk-linux-4.1.y

crypto: remove uses of __constant_{endian} helpers 

Base versions handle constant folding just fine.

Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Showing 2 changed files with 45 additions and 45 deletions Side-by-side Diff

... ... @@ -73,7 +73,7 @@
73 73 * /afs/transarc.com/public/afsps/afs.rel31b.export-src/rxkad/sboxes.h
74 74 */
75 75 #undef Z
76   -#define Z(x) __constant_cpu_to_be32(x << 3)
  76 +#define Z(x) cpu_to_be32(x << 3)
77 77 static const __be32 sbox0[256] = {
78 78 Z(0xea), Z(0x7f), Z(0xb2), Z(0x64), Z(0x9d), Z(0xb0), Z(0xd9), Z(0x11),
79 79 Z(0xcd), Z(0x86), Z(0x86), Z(0x91), Z(0x0a), Z(0xb2), Z(0x93), Z(0x06),
... ... @@ -110,7 +110,7 @@
110 110 };
111 111  
112 112 #undef Z
113   -#define Z(x) __constant_cpu_to_be32((x << 27) | (x >> 5))
  113 +#define Z(x) cpu_to_be32((x << 27) | (x >> 5))
114 114 static const __be32 sbox1[256] = {
115 115 Z(0x77), Z(0x14), Z(0xa6), Z(0xfe), Z(0xb2), Z(0x5e), Z(0x8c), Z(0x3e),
116 116 Z(0x67), Z(0x6c), Z(0xa1), Z(0x0d), Z(0xc2), Z(0xa2), Z(0xc1), Z(0x85),
... ... @@ -147,7 +147,7 @@
147 147 };
148 148  
149 149 #undef Z
150   -#define Z(x) __constant_cpu_to_be32(x << 11)
  150 +#define Z(x) cpu_to_be32(x << 11)
151 151 static const __be32 sbox2[256] = {
152 152 Z(0xf0), Z(0x37), Z(0x24), Z(0x53), Z(0x2a), Z(0x03), Z(0x83), Z(0x86),
153 153 Z(0xd1), Z(0xec), Z(0x50), Z(0xf0), Z(0x42), Z(0x78), Z(0x2f), Z(0x6d),
... ... @@ -184,7 +184,7 @@
184 184 };
185 185  
186 186 #undef Z
187   -#define Z(x) __constant_cpu_to_be32(x << 19)
  187 +#define Z(x) cpu_to_be32(x << 19)
188 188 static const __be32 sbox3[256] = {
189 189 Z(0xa9), Z(0x2a), Z(0x48), Z(0x51), Z(0x84), Z(0x7e), Z(0x49), Z(0xe2),
190 190 Z(0xb5), Z(0xb7), Z(0x42), Z(0x33), Z(0x7d), Z(0x5d), Z(0xa6), Z(0x12),
drivers/crypto/talitos.h
Diff comments   View file @ dad3df2
... ... @@ -134,34 +134,34 @@
134 134 */
135 135  
136 136 /* written back when done */
137   -#define DESC_HDR_DONE __constant_cpu_to_be32(0xff000000)
138   -#define DESC_HDR_LO_ICCR1_MASK __constant_cpu_to_be32(0x00180000)
139   -#define DESC_HDR_LO_ICCR1_PASS __constant_cpu_to_be32(0x00080000)
140   -#define DESC_HDR_LO_ICCR1_FAIL __constant_cpu_to_be32(0x00100000)
  137 +#define DESC_HDR_DONE cpu_to_be32(0xff000000)
  138 +#define DESC_HDR_LO_ICCR1_MASK cpu_to_be32(0x00180000)
  139 +#define DESC_HDR_LO_ICCR1_PASS cpu_to_be32(0x00080000)
  140 +#define DESC_HDR_LO_ICCR1_FAIL cpu_to_be32(0x00100000)
141 141  
142 142 /* primary execution unit select */
143   -#define DESC_HDR_SEL0_MASK __constant_cpu_to_be32(0xf0000000)
144   -#define DESC_HDR_SEL0_AFEU __constant_cpu_to_be32(0x10000000)
145   -#define DESC_HDR_SEL0_DEU __constant_cpu_to_be32(0x20000000)
146   -#define DESC_HDR_SEL0_MDEUA __constant_cpu_to_be32(0x30000000)
147   -#define DESC_HDR_SEL0_MDEUB __constant_cpu_to_be32(0xb0000000)
148   -#define DESC_HDR_SEL0_RNG __constant_cpu_to_be32(0x40000000)
149   -#define DESC_HDR_SEL0_PKEU __constant_cpu_to_be32(0x50000000)
150   -#define DESC_HDR_SEL0_AESU __constant_cpu_to_be32(0x60000000)
151   -#define DESC_HDR_SEL0_KEU __constant_cpu_to_be32(0x70000000)
152   -#define DESC_HDR_SEL0_CRCU __constant_cpu_to_be32(0x80000000)
  143 +#define DESC_HDR_SEL0_MASK cpu_to_be32(0xf0000000)
  144 +#define DESC_HDR_SEL0_AFEU cpu_to_be32(0x10000000)
  145 +#define DESC_HDR_SEL0_DEU cpu_to_be32(0x20000000)
  146 +#define DESC_HDR_SEL0_MDEUA cpu_to_be32(0x30000000)
  147 +#define DESC_HDR_SEL0_MDEUB cpu_to_be32(0xb0000000)
  148 +#define DESC_HDR_SEL0_RNG cpu_to_be32(0x40000000)
  149 +#define DESC_HDR_SEL0_PKEU cpu_to_be32(0x50000000)
  150 +#define DESC_HDR_SEL0_AESU cpu_to_be32(0x60000000)
  151 +#define DESC_HDR_SEL0_KEU cpu_to_be32(0x70000000)
  152 +#define DESC_HDR_SEL0_CRCU cpu_to_be32(0x80000000)
153 153  
154 154 /* primary execution unit mode (MODE0) and derivatives */
155   -#define DESC_HDR_MODE0_ENCRYPT __constant_cpu_to_be32(0x00100000)
156   -#define DESC_HDR_MODE0_AESU_CBC __constant_cpu_to_be32(0x00200000)
157   -#define DESC_HDR_MODE0_DEU_CBC __constant_cpu_to_be32(0x00400000)
158   -#define DESC_HDR_MODE0_DEU_3DES __constant_cpu_to_be32(0x00200000)
159   -#define DESC_HDR_MODE0_MDEU_INIT __constant_cpu_to_be32(0x01000000)
160   -#define DESC_HDR_MODE0_MDEU_HMAC __constant_cpu_to_be32(0x00800000)
161   -#define DESC_HDR_MODE0_MDEU_PAD __constant_cpu_to_be32(0x00400000)
162   -#define DESC_HDR_MODE0_MDEU_MD5 __constant_cpu_to_be32(0x00200000)
163   -#define DESC_HDR_MODE0_MDEU_SHA256 __constant_cpu_to_be32(0x00100000)
164   -#define DESC_HDR_MODE0_MDEU_SHA1 __constant_cpu_to_be32(0x00000000)
  155 +#define DESC_HDR_MODE0_ENCRYPT cpu_to_be32(0x00100000)
  156 +#define DESC_HDR_MODE0_AESU_CBC cpu_to_be32(0x00200000)
  157 +#define DESC_HDR_MODE0_DEU_CBC cpu_to_be32(0x00400000)
  158 +#define DESC_HDR_MODE0_DEU_3DES cpu_to_be32(0x00200000)
  159 +#define DESC_HDR_MODE0_MDEU_INIT cpu_to_be32(0x01000000)
  160 +#define DESC_HDR_MODE0_MDEU_HMAC cpu_to_be32(0x00800000)
  161 +#define DESC_HDR_MODE0_MDEU_PAD cpu_to_be32(0x00400000)
  162 +#define DESC_HDR_MODE0_MDEU_MD5 cpu_to_be32(0x00200000)
  163 +#define DESC_HDR_MODE0_MDEU_SHA256 cpu_to_be32(0x00100000)
  164 +#define DESC_HDR_MODE0_MDEU_SHA1 cpu_to_be32(0x00000000)
165 165 #define DESC_HDR_MODE0_MDEU_MD5_HMAC (DESC_HDR_MODE0_MDEU_MD5 | \
166 166 DESC_HDR_MODE0_MDEU_HMAC)
167 167 #define DESC_HDR_MODE0_MDEU_SHA256_HMAC (DESC_HDR_MODE0_MDEU_SHA256 | \
168 168  
... ... @@ -170,19 +170,19 @@
170 170 DESC_HDR_MODE0_MDEU_HMAC)
171 171  
172 172 /* secondary execution unit select (SEL1) */
173   -#define DESC_HDR_SEL1_MASK __constant_cpu_to_be32(0x000f0000)
174   -#define DESC_HDR_SEL1_MDEUA __constant_cpu_to_be32(0x00030000)
175   -#define DESC_HDR_SEL1_MDEUB __constant_cpu_to_be32(0x000b0000)
176   -#define DESC_HDR_SEL1_CRCU __constant_cpu_to_be32(0x00080000)
  173 +#define DESC_HDR_SEL1_MASK cpu_to_be32(0x000f0000)
  174 +#define DESC_HDR_SEL1_MDEUA cpu_to_be32(0x00030000)
  175 +#define DESC_HDR_SEL1_MDEUB cpu_to_be32(0x000b0000)
  176 +#define DESC_HDR_SEL1_CRCU cpu_to_be32(0x00080000)
177 177  
178 178 /* secondary execution unit mode (MODE1) and derivatives */
179   -#define DESC_HDR_MODE1_MDEU_CICV __constant_cpu_to_be32(0x00004000)
180   -#define DESC_HDR_MODE1_MDEU_INIT __constant_cpu_to_be32(0x00001000)
181   -#define DESC_HDR_MODE1_MDEU_HMAC __constant_cpu_to_be32(0x00000800)
182   -#define DESC_HDR_MODE1_MDEU_PAD __constant_cpu_to_be32(0x00000400)
183   -#define DESC_HDR_MODE1_MDEU_MD5 __constant_cpu_to_be32(0x00000200)
184   -#define DESC_HDR_MODE1_MDEU_SHA256 __constant_cpu_to_be32(0x00000100)
185   -#define DESC_HDR_MODE1_MDEU_SHA1 __constant_cpu_to_be32(0x00000000)
  179 +#define DESC_HDR_MODE1_MDEU_CICV cpu_to_be32(0x00004000)
  180 +#define DESC_HDR_MODE1_MDEU_INIT cpu_to_be32(0x00001000)
  181 +#define DESC_HDR_MODE1_MDEU_HMAC cpu_to_be32(0x00000800)
  182 +#define DESC_HDR_MODE1_MDEU_PAD cpu_to_be32(0x00000400)
  183 +#define DESC_HDR_MODE1_MDEU_MD5 cpu_to_be32(0x00000200)
  184 +#define DESC_HDR_MODE1_MDEU_SHA256 cpu_to_be32(0x00000100)
  185 +#define DESC_HDR_MODE1_MDEU_SHA1 cpu_to_be32(0x00000000)
186 186 #define DESC_HDR_MODE1_MDEU_MD5_HMAC (DESC_HDR_MODE1_MDEU_MD5 | \
187 187 DESC_HDR_MODE1_MDEU_HMAC)
188 188 #define DESC_HDR_MODE1_MDEU_SHA256_HMAC (DESC_HDR_MODE1_MDEU_SHA256 | \
189 189  
190 190  
... ... @@ -191,16 +191,16 @@
191 191 DESC_HDR_MODE1_MDEU_HMAC)
192 192  
193 193 /* direction of overall data flow (DIR) */
194   -#define DESC_HDR_DIR_INBOUND __constant_cpu_to_be32(0x00000002)
  194 +#define DESC_HDR_DIR_INBOUND cpu_to_be32(0x00000002)
195 195  
196 196 /* request done notification (DN) */
197   -#define DESC_HDR_DONE_NOTIFY __constant_cpu_to_be32(0x00000001)
  197 +#define DESC_HDR_DONE_NOTIFY cpu_to_be32(0x00000001)
198 198  
199 199 /* descriptor types */
200   -#define DESC_HDR_TYPE_AESU_CTR_NONSNOOP __constant_cpu_to_be32(0 << 3)
201   -#define DESC_HDR_TYPE_IPSEC_ESP __constant_cpu_to_be32(1 << 3)
202   -#define DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU __constant_cpu_to_be32(2 << 3)
203   -#define DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU __constant_cpu_to_be32(4 << 3)
  200 +#define DESC_HDR_TYPE_AESU_CTR_NONSNOOP cpu_to_be32(0 << 3)
  201 +#define DESC_HDR_TYPE_IPSEC_ESP cpu_to_be32(1 << 3)
  202 +#define DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU cpu_to_be32(2 << 3)
  203 +#define DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU cpu_to_be32(4 << 3)
204 204  
205 205 /* link table extent field bits */
206 206 #define DESC_PTR_LNKTBL_JUMP 0x80