isci: Added support for C0 to SCU Driver

C0 silicon updates the pci revision id and requires new AFE parameters for phy signal integrity. Support for previous silicon revisions is deprecated (it's also broken for the theoretical case of multiple controllers at different silicon revisions, all the more reason to get it removed as soon as possible) Signed-off-by: Adam Gruchala <adam.gruchala@intel.com> [fixed up deprecated silicon support] Signed-off-by: Dan Williams <dan.j.williams@intel.com>

isci: Added support for C0 to SCU Driver
C0 silicon updates the pci revision id and requires new AFE parameters for phy signal integrity. Support for previous silicon revisions is deprecated (it's also broken for the theoretical case of multiple controllers at different silicon revisions, all the more reason to get it removed as soon as possible) Signed-off-by: Adam Gruchala <adam.gruchala@intel.com> [fixed up deprecated silicon support] Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Adam Gruchala · Dan Williams
1 parent 12ef65444d
Showing 6 changed files with 88 additions and 39 deletions Side-by-side Diff
drivers/scsi/isci/firmware/create_fw.h
drivers/scsi/isci/host.c
drivers/scsi/isci/host.h
drivers/scsi/isci/init.c
drivers/scsi/isci/probe_roms.c
firmware/isci/isci_firmware.bin.ihex
@@ -65,10 +65,10 @@
 static const int enable_ssc;
  
 /* AFE_TX_AMP_CONTROL */
-static const unsigned int afe_tx_amp_control0 = 0x000e7c03;
-static const unsigned int afe_tx_amp_control1 = 0x000e7c03;
-static const unsigned int afe_tx_amp_control2 = 0x000e7c03;
-static const unsigned int afe_tx_amp_control3 = 0x000e7c03;
+static const unsigned int afe_tx_amp_control0 = 0x000bdd08;
+static const unsigned int afe_tx_amp_control1 = 0x000ffc00;
+static const unsigned int afe_tx_amp_control2 = 0x000b7c09;
+static const unsigned int afe_tx_amp_control3 = 0x000afc6e;
  
 static const char blob_name[] = "isci_firmware.bin";
 static const char sig[] = "ISCUOEMB";
@@ -2070,13 +2070,13 @@
 		writel(0x00005500, &scic->scu_registers->afe.afe_bias_control);
 	else if (is_a2())
 		writel(0x00005A00, &scic->scu_registers->afe.afe_bias_control);
-	else if (is_b0())
+	else if (is_b0() || is_c0())
 		writel(0x00005F00, &scic->scu_registers->afe.afe_bias_control);
  
 	udelay(AFE_REGISTER_WRITE_DELAY);
  
 	/* Enable PLL */
-	if (is_b0())
+	if (is_b0() || is_c0())
 		writel(0x80040A08, &scic->scu_registers->afe.afe_pll_control0);
 	else
 		writel(0x80040908, &scic->scu_registers->afe.afe_pll_control0);
@@ -2102,6 +2102,16 @@
 			 /* Configure transmitter SSC parameters */
 			writel(0x00030000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_ssc_control);
 			udelay(AFE_REGISTER_WRITE_DELAY);
+		} else if (is_c0()) {
+			 /* Configure transmitter SSC parameters */
+			writel(0x0003000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_ssc_control);
+			udelay(AFE_REGISTER_WRITE_DELAY);
+
+			/*
+			 * All defaults, except the Receive Word Alignament/Comma Detect
+			 * Enable....(0xe800) */
+			writel(0x00004500, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control0);
+			udelay(AFE_REGISTER_WRITE_DELAY);
 		} else {
 			/*
 			 * All defaults, except the Receive Word Alignament/Comma Detect
  
  
@@ -2120,15 +2130,23 @@
 			writel(0x000003D4, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
 		else if (is_a2())
 			writel(0x000003F0, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
-		else {
+		else if (is_b0()) {
 			 /* Power down TX and RX (PWRDNTX and PWRDNRX) */
-			writel(0x000003d7, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
+			writel(0x000003D7, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
 			udelay(AFE_REGISTER_WRITE_DELAY);
  
 			/*
 			 * Power up TX and RX out from power down (PWRDNTX and PWRDNRX)
 			 * & increase TX int & ext bias 20%....(0xe85c) */
-			writel(0x000003d4, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
+			writel(0x000003D4, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
+		} else {
+			writel(0x000001E7, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
+			udelay(AFE_REGISTER_WRITE_DELAY);
+
+			/*
+			 * Power up TX and RX out from power down (PWRDNTX and PWRDNRX)
+			 * & increase TX int & ext bias 20%....(0xe85c) */
+			writel(0x000001E4, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
 		}
 		udelay(AFE_REGISTER_WRITE_DELAY);
  
  
  
@@ -2149,12 +2167,22 @@
 			writel(0x3F09983F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
 		else if (is_a2())
 			writel(0x3F11103F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
-		else {
+		else if (is_b0()) {
 			writel(0x3F11103F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
 			udelay(AFE_REGISTER_WRITE_DELAY);
 			/* Enable TX equalization (0xe824) */
 			writel(0x00040000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_control);
+		} else {
+			writel(0x0140DF0F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control1);
+			udelay(AFE_REGISTER_WRITE_DELAY);
+
+			writel(0x3F6F103F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
+			udelay(AFE_REGISTER_WRITE_DELAY);
+
+			/* Enable TX equalization (0xe824) */
+			writel(0x00040000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_control);
 		}
+
 		udelay(AFE_REGISTER_WRITE_DELAY);
  
 		writel(oem_phy->afe_tx_amp_control0,
@@ -675,6 +675,7 @@
 	ISCI_SI_REVA0,
 	ISCI_SI_REVA2,
 	ISCI_SI_REVB0,
+	ISCI_SI_REVC0
 };
  
 extern int isci_si_rev;
@@ -691,7 +692,12 @@
  
 static inline bool is_b0(void)
 {
-	return isci_si_rev > ISCI_SI_REVA2;
+	return isci_si_rev == ISCI_SI_REVB0;
+}
+
+static inline bool is_c0(void)
+{
+	return isci_si_rev > ISCI_SI_REVB0;
 }
  
 void scic_sds_controller_post_request(struct scic_sds_controller *scic,
@@ -437,27 +437,27 @@
  
 static void check_si_rev(struct pci_dev *pdev)
 {
-	if (num_controllers(pdev) > 1)
+	switch (pdev->revision) {
+	case 0:
+	case 1:
+		/* if the id is ambiguous don't update isci_si_rev */
+		break;
+	case 3:
+		isci_si_rev = ISCI_SI_REVA2;
+		break;
+	case 4:
 		isci_si_rev = ISCI_SI_REVB0;
-	else {
-		switch (pdev->revision) {
-		case 0:
-		case 1:
-			/* if the id is ambiguous don't update isci_si_rev */
-			break;
-		case 3:
-			isci_si_rev = ISCI_SI_REVA2;
-			break;
-		default:
-		case 4:
-			isci_si_rev = ISCI_SI_REVB0;
-			break;
-		}
+		break;
+	default:
+	case 5:
+		isci_si_rev = ISCI_SI_REVC0;
+		break;
 	}
  
 	dev_info(&pdev->dev, "driver configured for %s silicon (rev: %d)\n",
 		 isci_si_rev == ISCI_SI_REVA0 ? "A0" :
-		 isci_si_rev == ISCI_SI_REVA2 ? "A2" : "B0", pdev->revision);
+		 isci_si_rev == ISCI_SI_REVA2 ? "A2" :
+		 isci_si_rev == ISCI_SI_REVB0 ? "B0" : "C0", pdev->revision);
  
 }
  
@@ -136,6 +136,7 @@
 struct isci_orom *isci_request_firmware(struct pci_dev *pdev, const struct firmware *fw)
 {
 	struct isci_orom *orom = NULL, *data;
+	int i, j;
  
 	if (request_firmware(&fw, ISCI_FW_NAME, &pdev->dev) != 0)
 		return NULL;
@@ -155,6 +156,20 @@
  
 	memcpy(orom, fw->data, fw->size);
  
+	/*
+	 * deprecated: override default amp_control for pre-preproduction
+	 * silicon revisions
+	 */
+	if (isci_si_rev <= ISCI_SI_REVB0)
+		goto out;
+
+	for (i = 0; i < ARRAY_SIZE(orom->ctrl); i++)
+		for (j = 0; j < ARRAY_SIZE(orom->ctrl[i].phys); j++) {
+			orom->ctrl[i].phys[j].afe_tx_amp_control0 = 0xe7c03;
+			orom->ctrl[i].phys[j].afe_tx_amp_control1 = 0xe7c03;
+			orom->ctrl[i].phys[j].afe_tx_amp_control2 = 0xe7c03;
+			orom->ctrl[i].phys[j].afe_tx_amp_control3 = 0xe7c03;
+		}
  out:
 	release_firmware(fw);
  
 :10000000495343554F454D42E80018100002000087
 :1000100000000000000000000101000000000000DE
-:10002000FFFFCF5F01000000037C0E00037C0E0089
-:10003000037C0E00037C0E00FFFFCF5F0100000079
-:10004000037C0E00037C0E00037C0E00037C0E007C
-:10005000FFFFCF5F01000000037C0E00037C0E0059
-:10006000037C0E00037C0E00FFFFCF5F0100000049
-:10007000037C0E00037C0E00037C0E00037C0E004C
+:10002000FFFFCF5F0100000008DD0B0000FC0F00A8
+:10003000097C0B006EFC0A00FFFFCF5F010000008F
+:1000400008DD0B0000FC0F00097C0B006EFC0A00B1
+:10005000FFFFCF5F0100000008DD0B0000FC0F0078
+:10006000097C0B006EFC0A00FFFFCF5F010000005F
+:1000700008DD0B0000FC0F00097C0B006EFC0A0081
 :100080000101000000000000FFFFCF5F0200000040
-:10009000037C0E00037C0E00037C0E00037C0E002C
-:1000A000FFFFCF5F02000000037C0E00037C0E0008
-:1000B000037C0E00037C0E00FFFFCF5F02000000F8
-:1000C000037C0E00037C0E00037C0E00037C0E00FC
-:1000D000FFFFCF5F02000000037C0E00037C0E00D8
-:0800E000037C0E00037C0E00FE
+:1000900008DD0B0000FC0F00097C0B006EFC0A0061
+:1000A000FFFFCF5F0200000008DD0B0000FC0F0027
+:1000B000097C0B006EFC0A00FFFFCF5F020000000E
+:1000C00008DD0B0000FC0F00097C0B006EFC0A0031
+:1000D000FFFFCF5F0200000008DD0B0000FC0F00F7
+:0800E000097C0B006EFC0A0014
 :00000001FF
...	...	@@ -65,10 +65,10 @@
65	65	static const int enable_ssc;
66	66
67	67	/* AFE_TX_AMP_CONTROL */
68		-static const unsigned int afe_tx_amp_control0 = 0x000e7c03;
69		-static const unsigned int afe_tx_amp_control1 = 0x000e7c03;
70		-static const unsigned int afe_tx_amp_control2 = 0x000e7c03;
71		-static const unsigned int afe_tx_amp_control3 = 0x000e7c03;
	68	+static const unsigned int afe_tx_amp_control0 = 0x000bdd08;
	69	+static const unsigned int afe_tx_amp_control1 = 0x000ffc00;
	70	+static const unsigned int afe_tx_amp_control2 = 0x000b7c09;
	71	+static const unsigned int afe_tx_amp_control3 = 0x000afc6e;
72	72
73	73	static const char blob_name[] = "isci_firmware.bin";
74	74	static const char sig[] = "ISCUOEMB";
...	...	@@ -2070,13 +2070,13 @@
2070	2070	writel(0x00005500, &scic->scu_registers->afe.afe_bias_control);
2071	2071	else if (is_a2())
2072	2072	writel(0x00005A00, &scic->scu_registers->afe.afe_bias_control);
2073		- else if (is_b0())
	2073	+ else if (is_b0() \|\| is_c0())
2074	2074	writel(0x00005F00, &scic->scu_registers->afe.afe_bias_control);
2075	2075
2076	2076	udelay(AFE_REGISTER_WRITE_DELAY);
2077	2077
2078	2078	/* Enable PLL */
2079		- if (is_b0())
	2079	+ if (is_b0() \|\| is_c0())
2080	2080	writel(0x80040A08, &scic->scu_registers->afe.afe_pll_control0);
2081	2081	else
2082	2082	writel(0x80040908, &scic->scu_registers->afe.afe_pll_control0);
...	...	@@ -2102,6 +2102,16 @@
2102	2102	/* Configure transmitter SSC parameters */
2103	2103	writel(0x00030000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_ssc_control);
2104	2104	udelay(AFE_REGISTER_WRITE_DELAY);
	2105	+ } else if (is_c0()) {
	2106	+ /* Configure transmitter SSC parameters */
	2107	+ writel(0x0003000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_ssc_control);
	2108	+ udelay(AFE_REGISTER_WRITE_DELAY);
	2109	+
	2110	+ /*
	2111	+ * All defaults, except the Receive Word Alignament/Comma Detect
	2112	+ * Enable....(0xe800) */
	2113	+ writel(0x00004500, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control0);
	2114	+ udelay(AFE_REGISTER_WRITE_DELAY);
2105	2115	} else {
2106	2116	/*
2107	2117	* All defaults, except the Receive Word Alignament/Comma Detect
2108	2118
2109	2119
...	...	@@ -2120,15 +2130,23 @@
2120	2130	writel(0x000003D4, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
2121	2131	else if (is_a2())
2122	2132	writel(0x000003F0, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
2123		- else {
	2133	+ else if (is_b0()) {
2124	2134	/* Power down TX and RX (PWRDNTX and PWRDNRX) */
2125		- writel(0x000003d7, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
	2135	+ writel(0x000003D7, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
2126	2136	udelay(AFE_REGISTER_WRITE_DELAY);
2127	2137
2128	2138	/*
2129	2139	* Power up TX and RX out from power down (PWRDNTX and PWRDNRX)
2130	2140	* & increase TX int & ext bias 20%....(0xe85c) */
2131		- writel(0x000003d4, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
	2141	+ writel(0x000003D4, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
	2142	+ } else {
	2143	+ writel(0x000001E7, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
	2144	+ udelay(AFE_REGISTER_WRITE_DELAY);
	2145	+
	2146	+ /*
	2147	+ * Power up TX and RX out from power down (PWRDNTX and PWRDNRX)
	2148	+ * & increase TX int & ext bias 20%....(0xe85c) */
	2149	+ writel(0x000001E4, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
2132	2150	}
2133	2151	udelay(AFE_REGISTER_WRITE_DELAY);
2134	2152
2135	2153
2136	2154
...	...	@@ -2149,12 +2167,22 @@
2149	2167	writel(0x3F09983F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
2150	2168	else if (is_a2())
2151	2169	writel(0x3F11103F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
2152		- else {
	2170	+ else if (is_b0()) {
2153	2171	writel(0x3F11103F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
2154	2172	udelay(AFE_REGISTER_WRITE_DELAY);
2155	2173	/* Enable TX equalization (0xe824) */
2156	2174	writel(0x00040000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_control);
	2175	+ } else {
	2176	+ writel(0x0140DF0F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control1);
	2177	+ udelay(AFE_REGISTER_WRITE_DELAY);
	2178	+
	2179	+ writel(0x3F6F103F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
	2180	+ udelay(AFE_REGISTER_WRITE_DELAY);
	2181	+
	2182	+ /* Enable TX equalization (0xe824) */
	2183	+ writel(0x00040000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_control);
2157	2184	}
	2185	+
2158	2186	udelay(AFE_REGISTER_WRITE_DELAY);
2159	2187
2160	2188	writel(oem_phy->afe_tx_amp_control0,
...	...	@@ -675,6 +675,7 @@
675	675	ISCI_SI_REVA0,
676	676	ISCI_SI_REVA2,
677	677	ISCI_SI_REVB0,
	678	+ ISCI_SI_REVC0
678	679	};
679	680
680	681	extern int isci_si_rev;
...	...	@@ -691,7 +692,12 @@
691	692
692	693	static inline bool is_b0(void)
693	694	{
694		- return isci_si_rev > ISCI_SI_REVA2;
	695	+ return isci_si_rev == ISCI_SI_REVB0;
	696	+}
	697	+
	698	+static inline bool is_c0(void)
	699	+{
	700	+ return isci_si_rev > ISCI_SI_REVB0;
695	701	}
696	702
697	703	void scic_sds_controller_post_request(struct scic_sds_controller *scic,
...	...	@@ -437,27 +437,27 @@
437	437
438	438	static void check_si_rev(struct pci_dev *pdev)
439	439	{
440		- if (num_controllers(pdev) > 1)
	440	+ switch (pdev->revision) {
	441	+ case 0:
	442	+ case 1:
	443	+ /* if the id is ambiguous don't update isci_si_rev */
	444	+ break;
	445	+ case 3:
	446	+ isci_si_rev = ISCI_SI_REVA2;
	447	+ break;
	448	+ case 4:
441	449	isci_si_rev = ISCI_SI_REVB0;
442		- else {
443		- switch (pdev->revision) {
444		- case 0:
445		- case 1:
446		- /* if the id is ambiguous don't update isci_si_rev */
447		- break;
448		- case 3:
449		- isci_si_rev = ISCI_SI_REVA2;
450		- break;
451		- default:
452		- case 4:
453		- isci_si_rev = ISCI_SI_REVB0;
454		- break;
455		- }
	450	+ break;
	451	+ default:
	452	+ case 5:
	453	+ isci_si_rev = ISCI_SI_REVC0;
	454	+ break;
456	455	}
457	456
458	457	dev_info(&pdev->dev, "driver configured for %s silicon (rev: %d)\n",
459	458	isci_si_rev == ISCI_SI_REVA0 ? "A0" :
460		- isci_si_rev == ISCI_SI_REVA2 ? "A2" : "B0", pdev->revision);
	459	+ isci_si_rev == ISCI_SI_REVA2 ? "A2" :
	460	+ isci_si_rev == ISCI_SI_REVB0 ? "B0" : "C0", pdev->revision);
461	461
462	462	}
463	463
...	...	@@ -136,6 +136,7 @@
136	136	struct isci_orom isci_request_firmware(struct pci_dev pdev, const struct firmware *fw)
137	137	{
138	138	struct isci_orom orom = NULL, data;
	139	+ int i, j;
139	140
140	141	if (request_firmware(&fw, ISCI_FW_NAME, &pdev->dev) != 0)
141	142	return NULL;
...	...	@@ -155,6 +156,20 @@
155	156
156	157	memcpy(orom, fw->data, fw->size);
157	158
	159	+ /*
	160	+ * deprecated: override default amp_control for pre-preproduction
	161	+ * silicon revisions
	162	+ */
	163	+ if (isci_si_rev <= ISCI_SI_REVB0)
	164	+ goto out;
	165	+
	166	+ for (i = 0; i < ARRAY_SIZE(orom->ctrl); i++)
	167	+ for (j = 0; j < ARRAY_SIZE(orom->ctrl[i].phys); j++) {
	168	+ orom->ctrl[i].phys[j].afe_tx_amp_control0 = 0xe7c03;
	169	+ orom->ctrl[i].phys[j].afe_tx_amp_control1 = 0xe7c03;
	170	+ orom->ctrl[i].phys[j].afe_tx_amp_control2 = 0xe7c03;
	171	+ orom->ctrl[i].phys[j].afe_tx_amp_control3 = 0xe7c03;
	172	+ }
158	173	out:
159	174	release_firmware(fw);
160	175
1	1	:10000000495343554F454D42E80018100002000087
2	2	:1000100000000000000000000101000000000000DE
3		-:10002000FFFFCF5F01000000037C0E00037C0E0089
4		-:10003000037C0E00037C0E00FFFFCF5F0100000079
5		-:10004000037C0E00037C0E00037C0E00037C0E007C
6		-:10005000FFFFCF5F01000000037C0E00037C0E0059
7		-:10006000037C0E00037C0E00FFFFCF5F0100000049
8		-:10007000037C0E00037C0E00037C0E00037C0E004C
	3	+:10002000FFFFCF5F0100000008DD0B0000FC0F00A8
	4	+:10003000097C0B006EFC0A00FFFFCF5F010000008F
	5	+:1000400008DD0B0000FC0F00097C0B006EFC0A00B1
	6	+:10005000FFFFCF5F0100000008DD0B0000FC0F0078
	7	+:10006000097C0B006EFC0A00FFFFCF5F010000005F
	8	+:1000700008DD0B0000FC0F00097C0B006EFC0A0081
9	9	:100080000101000000000000FFFFCF5F0200000040
10		-:10009000037C0E00037C0E00037C0E00037C0E002C
11		-:1000A000FFFFCF5F02000000037C0E00037C0E0008
12		-:1000B000037C0E00037C0E00FFFFCF5F02000000F8
13		-:1000C000037C0E00037C0E00037C0E00037C0E00FC
14		-:1000D000FFFFCF5F02000000037C0E00037C0E00D8
15		-:0800E000037C0E00037C0E00FE
	10	+:1000900008DD0B0000FC0F00097C0B006EFC0A0061
	11	+:1000A000FFFFCF5F0200000008DD0B0000FC0F0027
	12	+:1000B000097C0B006EFC0A00FFFFCF5F020000000E
	13	+:1000C00008DD0B0000FC0F00097C0B006EFC0A0031
	14	+:1000D000FFFFCF5F0200000008DD0B0000FC0F00F7
	15	+:0800E000097C0B006EFC0A0014
16	16	:00000001FF