Eric Lee / smarc-ti-linux-kernel

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Commit dbf3b7ddbaaf65c7da9b99a686b25fd06fd75073

Authored by Linus Torvalds
2 parents 9d82f5eb33 1b6af71a8f
Exists in ti-lsk-linux-4.1.y and in 10 other branches dlt-processor-sdk-linux-03.00.00.04, processor-sdk-linux-02.00.01, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus 

Pull MIPS fixes from Ralf Baechle:
 "The pending MIPS fixes for 3.19.  All across the field and nothing
  particularly severe or dramatic"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (23 commits)
  IRQCHIP: mips-gic: Avoid rerouting timer IRQs for smp-cmp
  MIPS: Fix syscall_get_nr for the syscall exit tracing.
  MIPS: elf2ecoff: Ignore PT_MIPS_ABIFLAGS program headers.
  MIPS: elf2ecoff: Rewrite main processing loop to switch.
  MIPS: fork: Fix MSA/FPU/DSP context duplication race
  MIPS: Fix C0_Pagegrain[IEC] support.
  MIPS: traps: Fix inline asm ctc1 missing .set hardfloat
  MIPS: mipsregs.h: Add write_32bit_cp1_register()
  MIPS: Fix kernel lockup or crash after CPU offline/online
  MIPS: OCTEON: fix kernel crash when offlining a CPU
  MIPS: ARC: Fix build error.
  MIPS: IRQ: Fix disable_irq on CPU IRQs
  MIPS: smp-mt,smp-cmp: Enable all HW IRQs on secondary CPUs
  MIPS: Fix restart of indirect syscalls
  MIPS: ELF: fix loading o32 binaries on 64-bit kernels
  MIPS: mips-cm: Fix sparse warnings
  MIPS: Kconfig: Fix recursive dependency.
  MIPS: Compat: Fix build error if CONFIG_MIPS32_COMPAT but no compat ABI.
  MIPS: JZ4740: Fixup #include's (sparse)
  MIPS: Wire up execveat(2).
  ...

Showing 26 changed files Side-by-side Diff

... ... @@ -2656,27 +2656,21 @@
2656 2656 bool
2657 2657  
2658 2658 config MIPS32_COMPAT
2659   - bool "Kernel support for Linux/MIPS 32-bit binary compatibility"
2660   - depends on 64BIT
2661   - help
2662   - Select this option if you want Linux/MIPS 32-bit binary
2663   - compatibility. Since all software available for Linux/MIPS is
2664   - currently 32-bit you should say Y here.
  2659 + bool
2665 2660  
2666 2661 config COMPAT
2667 2662 bool
2668   - depends on MIPS32_COMPAT
2669   - select ARCH_WANT_OLD_COMPAT_IPC
2670   - default y
2671 2663  
2672 2664 config SYSVIPC_COMPAT
2673 2665 bool
2674   - depends on COMPAT && SYSVIPC
2675   - default y
2676 2666  
2677 2667 config MIPS32_O32
2678 2668 bool "Kernel support for o32 binaries"
2679   - depends on MIPS32_COMPAT
  2669 + depends on 64BIT
  2670 + select ARCH_WANT_OLD_COMPAT_IPC
  2671 + select COMPAT
  2672 + select MIPS32_COMPAT
  2673 + select SYSVIPC_COMPAT if SYSVIPC
2680 2674 help
2681 2675 Select this option if you want to run o32 binaries. These are pure
2682 2676 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
... ... @@ -2686,7 +2680,10 @@
2686 2680  
2687 2681 config MIPS32_N32
2688 2682 bool "Kernel support for n32 binaries"
2689   - depends on MIPS32_COMPAT
  2683 + depends on 64BIT
  2684 + select COMPAT
  2685 + select MIPS32_COMPAT
  2686 + select SYSVIPC_COMPAT if SYSVIPC
2690 2687 help
2691 2688 Select this option if you want to run n32 binaries. These are
2692 2689 64-bit binaries using 32-bit quantities for addressing and certain
arch/mips/boot/elf2ecoff.c
Diff comments   View file @ dbf3b7d
... ... @@ -49,7 +49,8 @@
49 49 /*
50 50 * Some extra ELF definitions
51 51 */
52   -#define PT_MIPS_REGINFO 0x70000000 /* Register usage information */
  52 +#define PT_MIPS_REGINFO 0x70000000 /* Register usage information */
  53 +#define PT_MIPS_ABIFLAGS 0x70000003 /* Records ABI related flags */
53 54  
54 55 /* -------------------------------------------------------------------- */
55 56  
56 57  
57 58  
... ... @@ -349,39 +350,46 @@
349 350  
350 351 for (i = 0; i < ex.e_phnum; i++) {
351 352 /* Section types we can ignore... */
352   - if (ph[i].p_type == PT_NULL || ph[i].p_type == PT_NOTE ||
353   - ph[i].p_type == PT_PHDR
354   - || ph[i].p_type == PT_MIPS_REGINFO)
  353 + switch (ph[i].p_type) {
  354 + case PT_NULL:
  355 + case PT_NOTE:
  356 + case PT_PHDR:
  357 + case PT_MIPS_REGINFO:
  358 + case PT_MIPS_ABIFLAGS:
355 359 continue;
356   - /* Section types we can't handle... */
357   - else if (ph[i].p_type != PT_LOAD) {
  360 +
  361 + case PT_LOAD:
  362 + /* Writable (data) segment? */
  363 + if (ph[i].p_flags & PF_W) {
  364 + struct sect ndata, nbss;
  365 +
  366 + ndata.vaddr = ph[i].p_vaddr;
  367 + ndata.len = ph[i].p_filesz;
  368 + nbss.vaddr = ph[i].p_vaddr + ph[i].p_filesz;
  369 + nbss.len = ph[i].p_memsz - ph[i].p_filesz;
  370 +
  371 + combine(&data, &ndata, 0);
  372 + combine(&bss, &nbss, 1);
  373 + } else {
  374 + struct sect ntxt;
  375 +
  376 + ntxt.vaddr = ph[i].p_vaddr;
  377 + ntxt.len = ph[i].p_filesz;
  378 +
  379 + combine(&text, &ntxt, 0);
  380 + }
  381 + /* Remember the lowest segment start address. */
  382 + if (ph[i].p_vaddr < cur_vma)
  383 + cur_vma = ph[i].p_vaddr;
  384 + break;
  385 +
  386 + default:
  387 + /* Section types we can't handle... */
358 388 fprintf(stderr,
359 389 "Program header %d type %d can't be converted.\n",
360 390 ex.e_phnum, ph[i].p_type);
361 391 exit(1);
362 392 }
363   - /* Writable (data) segment? */
364   - if (ph[i].p_flags & PF_W) {
365   - struct sect ndata, nbss;
366   -
367   - ndata.vaddr = ph[i].p_vaddr;
368   - ndata.len = ph[i].p_filesz;
369   - nbss.vaddr = ph[i].p_vaddr + ph[i].p_filesz;
370   - nbss.len = ph[i].p_memsz - ph[i].p_filesz;
371   -
372   - combine(&data, &ndata, 0);
373   - combine(&bss, &nbss, 1);
374   - } else {
375   - struct sect ntxt;
376   -
377   - ntxt.vaddr = ph[i].p_vaddr;
378   - ntxt.len = ph[i].p_filesz;
379   -
380   - combine(&text, &ntxt, 0);
381   - }
382   - /* Remember the lowest segment start address. */
383   - if (ph[i].p_vaddr < cur_vma)
384   - cur_vma = ph[i].p_vaddr;
385 393 }
386 394  
387 395 /* Sections must be in order to be converted... */
arch/mips/cavium-octeon/smp.c
Diff comments   View file @ dbf3b7d
... ... @@ -240,9 +240,7 @@
240 240  
241 241 set_cpu_online(cpu, false);
242 242 cpu_clear(cpu, cpu_callin_map);
243   - local_irq_disable();
244 243 octeon_fixup_irqs();
245   - local_irq_enable();
246 244  
247 245 flush_cache_all();
248 246 local_flush_tlb_all();
arch/mips/configs/malta_defconfig
Diff comments   View file @ dbf3b7d
... ... @@ -132,7 +132,6 @@
132 132 CONFIG_IP_NF_MATCH_TTL=m
133 133 CONFIG_IP_NF_FILTER=m
134 134 CONFIG_IP_NF_TARGET_REJECT=m
135   -CONFIG_IP_NF_TARGET_ULOG=m
136 135 CONFIG_IP_NF_MANGLE=m
137 136 CONFIG_IP_NF_TARGET_CLUSTERIP=m
138 137 CONFIG_IP_NF_TARGET_ECN=m
... ... @@ -175,7 +174,6 @@
175 174 CONFIG_BRIDGE_EBT_REDIRECT=m
176 175 CONFIG_BRIDGE_EBT_SNAT=m
177 176 CONFIG_BRIDGE_EBT_LOG=m
178   -CONFIG_BRIDGE_EBT_ULOG=m
179 177 CONFIG_BRIDGE_EBT_NFLOG=m
180 178 CONFIG_IP_SCTP=m
181 179 CONFIG_BRIDGE=m
... ... @@ -220,8 +218,6 @@
220 218 CONFIG_NET_CLS_IND=y
221 219 CONFIG_CFG80211=m
222 220 CONFIG_MAC80211=m
223   -CONFIG_MAC80211_RC_PID=y
224   -CONFIG_MAC80211_RC_DEFAULT_PID=y
225 221 CONFIG_MAC80211_MESH=y
226 222 CONFIG_RFKILL=m
227 223 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
228 224  
229 225  
... ... @@ -248,19 +244,13 @@
248 244 CONFIG_IDE=y
249 245 CONFIG_BLK_DEV_IDECD=y
250 246 CONFIG_IDE_GENERIC=y
251   -CONFIG_BLK_DEV_GENERIC=y
252   -CONFIG_BLK_DEV_PIIX=y
253   -CONFIG_BLK_DEV_IT8213=m
254   -CONFIG_BLK_DEV_TC86C001=m
255 247 CONFIG_RAID_ATTRS=m
256   -CONFIG_SCSI=m
257   -CONFIG_BLK_DEV_SD=m
  248 +CONFIG_BLK_DEV_SD=y
258 249 CONFIG_CHR_DEV_ST=m
259 250 CONFIG_CHR_DEV_OSST=m
260 251 CONFIG_BLK_DEV_SR=m
261 252 CONFIG_BLK_DEV_SR_VENDOR=y
262 253 CONFIG_CHR_DEV_SG=m
263   -CONFIG_SCSI_MULTI_LUN=y
264 254 CONFIG_SCSI_CONSTANTS=y
265 255 CONFIG_SCSI_LOGGING=y
266 256 CONFIG_SCSI_SCAN_ASYNC=y
... ... @@ -273,6 +263,8 @@
273 263 CONFIG_SCSI_AIC7XXX=m
274 264 CONFIG_AIC7XXX_RESET_DELAY_MS=15000
275 265 # CONFIG_AIC7XXX_DEBUG_ENABLE is not set
  266 +CONFIG_ATA=y
  267 +CONFIG_ATA_PIIX=y
276 268 CONFIG_MD=y
277 269 CONFIG_BLK_DEV_MD=m
278 270 CONFIG_MD_LINEAR=m
... ... @@ -340,6 +332,7 @@
340 332 CONFIG_UIO_CIF=m
341 333 CONFIG_EXT2_FS=y
342 334 CONFIG_EXT3_FS=y
  335 +CONFIG_EXT4_FS=y
343 336 CONFIG_REISERFS_FS=m
344 337 CONFIG_REISERFS_PROC_INFO=y
345 338 CONFIG_REISERFS_FS_XATTR=y
... ... @@ -441,5 +434,4 @@
441 434 CONFIG_CRYPTO_TEA=m
442 435 CONFIG_CRYPTO_TWOFISH=m
443 436 # CONFIG_CRYPTO_ANSI_CPRNG is not set
444   -CONFIG_CRC16=m
arch/mips/include/asm/fpu.h
Diff comments   View file @ dbf3b7d
... ... @@ -64,7 +64,7 @@
64 64 return SIGFPE;
65 65  
66 66 /* set FRE */
67   - write_c0_config5(read_c0_config5() | MIPS_CONF5_FRE);
  67 + set_c0_config5(MIPS_CONF5_FRE);
68 68 goto fr_common;
69 69  
70 70 case FPU_64BIT:
... ... @@ -74,8 +74,10 @@
74 74 #endif
75 75 /* fall through */
76 76 case FPU_32BIT:
77   - /* clear FRE */
78   - write_c0_config5(read_c0_config5() & ~MIPS_CONF5_FRE);
  77 + if (cpu_has_fre) {
  78 + /* clear FRE */
  79 + clear_c0_config5(MIPS_CONF5_FRE);
  80 + }
79 81 fr_common:
80 82 /* set CU1 & change FR appropriately */
81 83 fr = (int)mode & FPU_FR_MASK;
82 84  
83 85  
84 86  
85 87  
... ... @@ -182,25 +184,32 @@
182 184 int ret = 0;
183 185  
184 186 if (cpu_has_fpu) {
  187 + unsigned int config5;
  188 +
185 189 ret = __own_fpu();
186   - if (!ret) {
187   - unsigned int config5 = read_c0_config5();
  190 + if (ret)
  191 + return ret;
188 192  
189   - /*
190   - * Ensure FRE is clear whilst running _init_fpu, since
191   - * single precision FP instructions are used. If FRE
192   - * was set then we'll just end up initialising all 32
193   - * 64b registers.
194   - */
195   - write_c0_config5(config5 & ~MIPS_CONF5_FRE);
196   - enable_fpu_hazard();
197   -
  193 + if (!cpu_has_fre) {
198 194 _init_fpu();
199 195  
200   - /* Restore FRE */
201   - write_c0_config5(config5);
202   - enable_fpu_hazard();
  196 + return 0;
203 197 }
  198 +
  199 + /*
  200 + * Ensure FRE is clear whilst running _init_fpu, since
  201 + * single precision FP instructions are used. If FRE
  202 + * was set then we'll just end up initialising all 32
  203 + * 64b registers.
  204 + */
  205 + config5 = clear_c0_config5(MIPS_CONF5_FRE);
  206 + enable_fpu_hazard();
  207 +
  208 + _init_fpu();
  209 +
  210 + /* Restore FRE */
  211 + write_c0_config5(config5);
  212 + enable_fpu_hazard();
204 213 } else
205 214 fpu_emulator_init_fpu();
206 215  
arch/mips/include/asm/fw/arc/hinv.h
Diff comments   View file @ dbf3b7d
... ... @@ -119,7 +119,7 @@
119 119 #define SGI_ARCS_REV 10 /* rev .10, 3/04/92 */
120 120 #endif
121 121  
122   -typedef struct component {
  122 +typedef struct {
123 123 CONFIGCLASS Class;
124 124 CONFIGTYPE Type;
125 125 IDENTIFIERFLAG Flags;
... ... @@ -140,7 +140,7 @@
140 140 };
141 141  
142 142 /* System ID */
143   -typedef struct systemid {
  143 +typedef struct {
144 144 CHAR VendorId[8];
145 145 CHAR ProductId[8];
146 146 } SYSTEMID;
... ... @@ -166,7 +166,7 @@
166 166 #endif /* _NT_PROM */
167 167 } MEMORYTYPE;
168 168  
169   -typedef struct memorydescriptor {
  169 +typedef struct {
170 170 MEMORYTYPE Type;
171 171 LONG BasePage;
172 172 LONG PageCount;
arch/mips/include/asm/mips-cm.h
Diff comments   View file @ dbf3b7d
... ... @@ -89,9 +89,9 @@
89 89  
90 90 /* Macros to ease the creation of register access functions */
91 91 #define BUILD_CM_R_(name, off) \
92   -static inline u32 *addr_gcr_##name(void) \
  92 +static inline u32 __iomem *addr_gcr_##name(void) \
93 93 { \
94   - return (u32 *)(mips_cm_base + (off)); \
  94 + return (u32 __iomem *)(mips_cm_base + (off)); \
95 95 } \
96 96 \
97 97 static inline u32 read_gcr_##name(void) \
arch/mips/include/asm/mipsregs.h
Diff comments   View file @ dbf3b7d
... ... @@ -1386,12 +1386,27 @@
1386 1386 __res; \
1387 1387 })
1388 1388  
  1389 +#define _write_32bit_cp1_register(dest, val, gas_hardfloat) \
  1390 +do { \
  1391 + __asm__ __volatile__( \
  1392 + " .set push \n" \
  1393 + " .set reorder \n" \
  1394 + " "STR(gas_hardfloat)" \n" \
  1395 + " ctc1 %0,"STR(dest)" \n" \
  1396 + " .set pop \n" \
  1397 + : : "r" (val)); \
  1398 +} while (0)
  1399 +
1389 1400 #ifdef GAS_HAS_SET_HARDFLOAT
1390 1401 #define read_32bit_cp1_register(source) \
1391 1402 _read_32bit_cp1_register(source, .set hardfloat)
  1403 +#define write_32bit_cp1_register(dest, val) \
  1404 + _write_32bit_cp1_register(dest, val, .set hardfloat)
1392 1405 #else
1393 1406 #define read_32bit_cp1_register(source) \
1394 1407 _read_32bit_cp1_register(source, )
  1408 +#define write_32bit_cp1_register(dest, val) \
  1409 + _write_32bit_cp1_register(dest, val, )
1395 1410 #endif
1396 1411  
1397 1412 #ifdef HAVE_AS_DSP
arch/mips/include/asm/syscall.h
Diff comments   View file @ dbf3b7d
... ... @@ -29,13 +29,7 @@
29 29 static inline long syscall_get_nr(struct task_struct *task,
30 30 struct pt_regs *regs)
31 31 {
32   - /* O32 ABI syscall() - Either 64-bit with O32 or 32-bit */
33   - if ((config_enabled(CONFIG_32BIT) ||
34   - test_tsk_thread_flag(task, TIF_32BIT_REGS)) &&
35   - (regs->regs[2] == __NR_syscall))
36   - return regs->regs[4];
37   - else
38   - return regs->regs[2];
  32 + return current_thread_info()->syscall;
39 33 }
40 34  
41 35 static inline unsigned long mips_get_syscall_arg(unsigned long *arg,
arch/mips/include/asm/thread_info.h
Diff comments   View file @ dbf3b7d
... ... @@ -36,6 +36,7 @@
36 36 */
37 37 struct restart_block restart_block;
38 38 struct pt_regs *regs;
  39 + long syscall; /* syscall number */
39 40 };
40 41  
41 42 /*
arch/mips/include/uapi/asm/unistd.h
Diff comments   View file @ dbf3b7d
... ... @@ -376,16 +376,17 @@
376 376 #define __NR_getrandom (__NR_Linux + 353)
377 377 #define __NR_memfd_create (__NR_Linux + 354)
378 378 #define __NR_bpf (__NR_Linux + 355)
  379 +#define __NR_execveat (__NR_Linux + 356)
379 380  
380 381 /*
381 382 * Offset of the last Linux o32 flavoured syscall
382 383 */
383   -#define __NR_Linux_syscalls 355
  384 +#define __NR_Linux_syscalls 356
384 385  
385 386 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
386 387  
387 388 #define __NR_O32_Linux 4000
388   -#define __NR_O32_Linux_syscalls 355
  389 +#define __NR_O32_Linux_syscalls 356
389 390  
390 391 #if _MIPS_SIM == _MIPS_SIM_ABI64
391 392  
392 393  
393 394  
... ... @@ -709,16 +710,17 @@
709 710 #define __NR_getrandom (__NR_Linux + 313)
710 711 #define __NR_memfd_create (__NR_Linux + 314)
711 712 #define __NR_bpf (__NR_Linux + 315)
  713 +#define __NR_execveat (__NR_Linux + 316)
712 714  
713 715 /*
714 716 * Offset of the last Linux 64-bit flavoured syscall
715 717 */
716   -#define __NR_Linux_syscalls 315
  718 +#define __NR_Linux_syscalls 316
717 719  
718 720 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
719 721  
720 722 #define __NR_64_Linux 5000
721   -#define __NR_64_Linux_syscalls 315
  723 +#define __NR_64_Linux_syscalls 316
722 724  
723 725 #if _MIPS_SIM == _MIPS_SIM_NABI32
724 726  
725 727  
726 728  
... ... @@ -1046,16 +1048,17 @@
1046 1048 #define __NR_getrandom (__NR_Linux + 317)
1047 1049 #define __NR_memfd_create (__NR_Linux + 318)
1048 1050 #define __NR_bpf (__NR_Linux + 319)
  1051 +#define __NR_execveat (__NR_Linux + 320)
1049 1052  
1050 1053 /*
1051 1054 * Offset of the last N32 flavoured syscall
1052 1055 */
1053   -#define __NR_Linux_syscalls 319
  1056 +#define __NR_Linux_syscalls 320
1054 1057  
1055 1058 #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
1056 1059  
1057 1060 #define __NR_N32_Linux 6000
1058   -#define __NR_N32_Linux_syscalls 319
  1061 +#define __NR_N32_Linux_syscalls 320
1059 1062  
1060 1063 #endif /* _UAPI_ASM_UNISTD_H */
arch/mips/jz4740/irq.c
Diff comments   View file @ dbf3b7d
... ... @@ -30,6 +30,9 @@
30 30 #include <asm/irq_cpu.h>
31 31  
32 32 #include <asm/mach-jz4740/base.h>
  33 +#include <asm/mach-jz4740/irq.h>
  34 +
  35 +#include "irq.h"
33 36  
34 37 static void __iomem *jz_intc_base;
35 38  
arch/mips/kernel/elf.c
Diff comments   View file @ dbf3b7d
... ... @@ -19,8 +19,8 @@
19 19 int arch_elf_pt_proc(void *_ehdr, void *_phdr, struct file *elf,
20 20 bool is_interp, struct arch_elf_state *state)
21 21 {
22   - struct elfhdr *ehdr = _ehdr;
23   - struct elf_phdr *phdr = _phdr;
  22 + struct elf32_hdr *ehdr = _ehdr;
  23 + struct elf32_phdr *phdr = _phdr;
24 24 struct mips_elf_abiflags_v0 abiflags;
25 25 int ret;
26 26  
... ... @@ -48,7 +48,7 @@
48 48 return 0;
49 49 }
50 50  
51   -static inline unsigned get_fp_abi(struct elfhdr *ehdr, int in_abi)
  51 +static inline unsigned get_fp_abi(struct elf32_hdr *ehdr, int in_abi)
52 52 {
53 53 /* If the ABI requirement is provided, simply return that */
54 54 if (in_abi != -1)
... ... @@ -65,7 +65,7 @@
65 65 int arch_check_elf(void *_ehdr, bool has_interpreter,
66 66 struct arch_elf_state *state)
67 67 {
68   - struct elfhdr *ehdr = _ehdr;
  68 + struct elf32_hdr *ehdr = _ehdr;
69 69 unsigned fp_abi, interp_fp_abi, abi0, abi1;
70 70  
71 71 /* Ignore non-O32 binaries */
arch/mips/kernel/irq_cpu.c
Diff comments   View file @ dbf3b7d
... ... @@ -57,6 +57,8 @@
57 57 .irq_mask_ack = mask_mips_irq,
58 58 .irq_unmask = unmask_mips_irq,
59 59 .irq_eoi = unmask_mips_irq,
  60 + .irq_disable = mask_mips_irq,
  61 + .irq_enable = unmask_mips_irq,
60 62 };
61 63  
62 64 /*
... ... @@ -93,6 +95,8 @@
93 95 .irq_mask_ack = mips_mt_cpu_irq_ack,
94 96 .irq_unmask = unmask_mips_irq,
95 97 .irq_eoi = unmask_mips_irq,
  98 + .irq_disable = mask_mips_irq,
  99 + .irq_enable = unmask_mips_irq,
96 100 };
97 101  
98 102 asmlinkage void __weak plat_irq_dispatch(void)
arch/mips/kernel/process.c
Diff comments   View file @ dbf3b7d
... ... @@ -82,6 +82,30 @@
82 82 {
83 83 }
84 84  
  85 +int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
  86 +{
  87 + /*
  88 + * Save any process state which is live in hardware registers to the
  89 + * parent context prior to duplication. This prevents the new child
  90 + * state becoming stale if the parent is preempted before copy_thread()
  91 + * gets a chance to save the parent's live hardware registers to the
  92 + * child context.
  93 + */
  94 + preempt_disable();
  95 +
  96 + if (is_msa_enabled())
  97 + save_msa(current);
  98 + else if (is_fpu_owner())
  99 + _save_fp(current);
  100 +
  101 + save_dsp(current);
  102 +
  103 + preempt_enable();
  104 +
  105 + *dst = *src;
  106 + return 0;
  107 +}
  108 +
85 109 int copy_thread(unsigned long clone_flags, unsigned long usp,
86 110 unsigned long arg, struct task_struct *p)
87 111 {
... ... @@ -91,18 +115,6 @@
91 115 p->set_child_tid = p->clear_child_tid = NULL;
92 116  
93 117 childksp = (unsigned long)task_stack_page(p) + THREAD_SIZE - 32;
94   -
95   - preempt_disable();
96   -
97   - if (is_msa_enabled())
98   - save_msa(p);
99   - else if (is_fpu_owner())
100   - save_fp(p);
101   -
102   - if (cpu_has_dsp)
103   - save_dsp(p);
104   -
105   - preempt_enable();
106 118  
107 119 /* set up new TSS. */
108 120 childregs = (struct pt_regs *) childksp - 1;
arch/mips/kernel/ptrace.c
Diff comments   View file @ dbf3b7d
... ... @@ -770,6 +770,8 @@
770 770 long ret = 0;
771 771 user_exit();
772 772  
  773 + current_thread_info()->syscall = syscall;
  774 +
773 775 if (secure_computing() == -1)
774 776 return -1;
775 777  
arch/mips/kernel/scall32-o32.S
Diff comments   View file @ dbf3b7d
... ... @@ -181,6 +181,7 @@
181 181 sll t1, t0, 2
182 182 beqz v0, einval
183 183 lw t2, sys_call_table(t1) # syscall routine
  184 + sw a0, PT_R2(sp) # call routine directly on restart
184 185  
185 186 /* Some syscalls like execve get their arguments from struct pt_regs
186 187 and claim zero arguments in the syscall table. Thus we have to
... ... @@ -580,4 +581,5 @@
580 581 PTR sys_getrandom
581 582 PTR sys_memfd_create
582 583 PTR sys_bpf /* 4355 */
  584 + PTR sys_execveat
arch/mips/kernel/scall64-64.S
Diff comments   View file @ dbf3b7d
... ... @@ -435,5 +435,6 @@
435 435 PTR sys_getrandom
436 436 PTR sys_memfd_create
437 437 PTR sys_bpf /* 5315 */
  438 + PTR sys_execveat
438 439 .size sys_call_table,.-sys_call_table
arch/mips/kernel/scall64-n32.S
Diff comments   View file @ dbf3b7d
... ... @@ -428,5 +428,6 @@
428 428 PTR sys_getrandom
429 429 PTR sys_memfd_create
430 430 PTR sys_bpf
  431 + PTR compat_sys_execveat /* 6320 */
431 432 .size sysn32_call_table,.-sysn32_call_table
arch/mips/kernel/scall64-o32.S
Diff comments   View file @ dbf3b7d
... ... @@ -186,6 +186,7 @@
186 186 dsll t1, t0, 3
187 187 beqz v0, einval
188 188 ld t2, sys32_call_table(t1) # syscall routine
  189 + sd a0, PT_R2(sp) # call routine directly on restart
189 190  
190 191 move a0, a1 # shift argument registers
191 192 move a1, a2
... ... @@ -565,5 +566,6 @@
565 566 PTR sys_getrandom
566 567 PTR sys_memfd_create
567 568 PTR sys_bpf /* 4355 */
  569 + PTR compat_sys_execveat
568 570 .size sys32_call_table,.-sys32_call_table
arch/mips/kernel/smp-cmp.c
Diff comments   View file @ dbf3b7d
... ... @@ -44,8 +44,8 @@
44 44 struct cpuinfo_mips *c __maybe_unused = &current_cpu_data;
45 45  
46 46 /* Assume GIC is present */
47   - change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | STATUSF_IP6 |
48   - STATUSF_IP7);
  47 + change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 |
  48 + STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7);
49 49  
50 50 /* Enable per-cpu interrupts: platform specific */
51 51  
arch/mips/kernel/smp-mt.c
Diff comments   View file @ dbf3b7d
... ... @@ -161,7 +161,8 @@
161 161 #ifdef CONFIG_MIPS_GIC
162 162 /* This is Malta specific: IPI,performance and timer interrupts */
163 163 if (gic_present)
164   - change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 |
  164 + change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 |
  165 + STATUSF_IP4 | STATUSF_IP5 |
165 166 STATUSF_IP6 | STATUSF_IP7);
166 167 else
167 168 #endif
arch/mips/kernel/smp.c
Diff comments   View file @ dbf3b7d
... ... @@ -123,10 +123,10 @@
123 123 unsigned int cpu;
124 124  
125 125 cpu_probe();
126   - cpu_report();
127 126 per_cpu_trap_init(false);
128 127 mips_clockevent_init();
129 128 mp_ops->init_secondary();
  129 + cpu_report();
130 130  
131 131 /*
132 132 * XXX parity protection should be folded in here when it's converted
arch/mips/kernel/traps.c
Diff comments   View file @ dbf3b7d
... ... @@ -1231,7 +1231,8 @@
1231 1231  
1232 1232 /* Restore the scalar FP control & status register */
1233 1233 if (!was_fpu_owner)
1234   - asm volatile("ctc1 %0, $31" : : "r"(current->thread.fpu.fcr31));
  1234 + write_32bit_cp1_register(CP1_STATUS,
  1235 + current->thread.fpu.fcr31);
1235 1236 }
1236 1237  
1237 1238 out:
arch/mips/mm/tlb-r4k.c
Diff comments   View file @ dbf3b7d
... ... @@ -489,6 +489,8 @@
489 489 #ifdef CONFIG_64BIT
490 490 pg |= PG_ELPA;
491 491 #endif
  492 + if (cpu_has_rixiex)
  493 + pg |= PG_IEC;
492 494 write_c0_pagegrain(pg);
493 495 }
494 496  
drivers/irqchip/irq-mips-gic.c
Diff comments   View file @ dbf3b7d
... ... @@ -37,6 +37,7 @@
37 37 static int gic_shared_intrs;
38 38 static int gic_vpes;
39 39 static unsigned int gic_cpu_pin;
  40 +static unsigned int timer_cpu_pin;
40 41 static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller;
41 42  
42 43 static void __gic_irq_dispatch(void);
... ... @@ -616,6 +617,8 @@
616 617 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_MAP), val);
617 618 break;
618 619 case GIC_LOCAL_INT_TIMER:
  620 + /* CONFIG_MIPS_CMP workaround (see __gic_init) */
  621 + val = GIC_MAP_TO_PIN_MSK | timer_cpu_pin;
619 622 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP), val);
620 623 break;
621 624 case GIC_LOCAL_INT_PERFCTR:
622 625  
... ... @@ -713,12 +716,36 @@
713 716 if (cpu_has_veic) {
714 717 /* Always use vector 1 in EIC mode */
715 718 gic_cpu_pin = 0;
  719 + timer_cpu_pin = gic_cpu_pin;
716 720 set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET,
717 721 __gic_irq_dispatch);
718 722 } else {
719 723 gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET;
720 724 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec,
721 725 gic_irq_dispatch);
  726 + /*
  727 + * With the CMP implementation of SMP (deprecated), other CPUs
  728 + * are started by the bootloader and put into a timer based
  729 + * waiting poll loop. We must not re-route those CPU's local
  730 + * timer interrupts as the wait instruction will never finish,
  731 + * so just handle whatever CPU interrupt it is routed to by
  732 + * default.
  733 + *
  734 + * This workaround should be removed when CMP support is
  735 + * dropped.
  736 + */
  737 + if (IS_ENABLED(CONFIG_MIPS_CMP) &&
  738 + gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) {
  739 + timer_cpu_pin = gic_read(GIC_REG(VPE_LOCAL,
  740 + GIC_VPE_TIMER_MAP)) &
  741 + GIC_MAP_MSK;
  742 + irq_set_chained_handler(MIPS_CPU_IRQ_BASE +
  743 + GIC_CPU_PIN_OFFSET +
  744 + timer_cpu_pin,
  745 + gic_irq_dispatch);
  746 + } else {
  747 + timer_cpu_pin = gic_cpu_pin;
  748 + }
722 749 }
723 750  
724 751 gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS +