Merge remote-tracking branch 'spi/fix/sh-msiof' into spi-linus

Mark Brown
2 parents 52addcf9d6 3e81b59208
Showing 1 changed file Side-by-side Diff
drivers/spi/spi-sh-msiof.c
@@ -636,48 +636,38 @@
 	dma_cookie_t cookie;
 	int ret;
  
-	if (tx) {
-		ier_bits |= IER_TDREQE | IER_TDMAE;
-		dma_sync_single_for_device(p->master->dma_tx->device->dev,
-					   p->tx_dma_addr, len, DMA_TO_DEVICE);
-		desc_tx = dmaengine_prep_slave_single(p->master->dma_tx,
-					p->tx_dma_addr, len, DMA_TO_DEVICE,
-					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
-		if (!desc_tx)
-			return -EAGAIN;
-	}
-
+	/* First prepare and submit the DMA request(s), as this may fail */
 	if (rx) {
 		ier_bits |= IER_RDREQE | IER_RDMAE;
 		desc_rx = dmaengine_prep_slave_single(p->master->dma_rx,
 					p->rx_dma_addr, len, DMA_FROM_DEVICE,
 					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
-		if (!desc_rx)
-			return -EAGAIN;
-	}
+		if (!desc_rx) {
+			ret = -EAGAIN;
+			goto no_dma_rx;
+		}
  
-	/* 1 stage FIFO watermarks for DMA */
-	sh_msiof_write(p, FCTR, FCTR_TFWM_1 | FCTR_RFWM_1);
-
-	/* setup msiof transfer mode registers (32-bit words) */
-	sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);
-
-	sh_msiof_write(p, IER, ier_bits);
-
-	reinit_completion(&p->done);
-
-	if (rx) {
 		desc_rx->callback = sh_msiof_dma_complete;
 		desc_rx->callback_param = p;
 		cookie = dmaengine_submit(desc_rx);
 		if (dma_submit_error(cookie)) {
 			ret = cookie;
-			goto stop_ier;
+			goto no_dma_rx;
 		}
-		dma_async_issue_pending(p->master->dma_rx);
 	}
  
 	if (tx) {
+		ier_bits |= IER_TDREQE | IER_TDMAE;
+		dma_sync_single_for_device(p->master->dma_tx->device->dev,
+					   p->tx_dma_addr, len, DMA_TO_DEVICE);
+		desc_tx = dmaengine_prep_slave_single(p->master->dma_tx,
+					p->tx_dma_addr, len, DMA_TO_DEVICE,
+					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+		if (!desc_tx) {
+			ret = -EAGAIN;
+			goto no_dma_tx;
+		}
+
 		if (rx) {
 			/* No callback */
 			desc_tx->callback = NULL;
  
  
  
@@ -688,15 +678,30 @@
 		cookie = dmaengine_submit(desc_tx);
 		if (dma_submit_error(cookie)) {
 			ret = cookie;
-			goto stop_rx;
+			goto no_dma_tx;
 		}
-		dma_async_issue_pending(p->master->dma_tx);
 	}
  
+	/* 1 stage FIFO watermarks for DMA */
+	sh_msiof_write(p, FCTR, FCTR_TFWM_1 | FCTR_RFWM_1);
+
+	/* setup msiof transfer mode registers (32-bit words) */
+	sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);
+
+	sh_msiof_write(p, IER, ier_bits);
+
+	reinit_completion(&p->done);
+
+	/* Now start DMA */
+	if (tx)
+		dma_async_issue_pending(p->master->dma_rx);
+	if (rx)
+		dma_async_issue_pending(p->master->dma_tx);
+
 	ret = sh_msiof_spi_start(p, rx);
 	if (ret) {
 		dev_err(&p->pdev->dev, "failed to start hardware\n");
-		goto stop_tx;
+		goto stop_dma;
 	}
  
 	/* wait for tx fifo to be emptied / rx fifo to be filled */
  
  
  
@@ -726,14 +731,14 @@
 stop_reset:
 	sh_msiof_reset_str(p);
 	sh_msiof_spi_stop(p, rx);
-stop_tx:
+stop_dma:
 	if (tx)
 		dmaengine_terminate_all(p->master->dma_tx);
-stop_rx:
+no_dma_tx:
 	if (rx)
 		dmaengine_terminate_all(p->master->dma_rx);
-stop_ier:
 	sh_msiof_write(p, IER, 0);
+no_dma_rx:
 	return ret;
 }
...	...	@@ -636,48 +636,38 @@
636	636	dma_cookie_t cookie;
637	637	int ret;
638	638
639		- if (tx) {
640		- ier_bits \|= IER_TDREQE \| IER_TDMAE;
641		- dma_sync_single_for_device(p->master->dma_tx->device->dev,
642		- p->tx_dma_addr, len, DMA_TO_DEVICE);
643		- desc_tx = dmaengine_prep_slave_single(p->master->dma_tx,
644		- p->tx_dma_addr, len, DMA_TO_DEVICE,
645		- DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
646		- if (!desc_tx)
647		- return -EAGAIN;
648		- }
649		-
	639	+ /* First prepare and submit the DMA request(s), as this may fail */
650	640	if (rx) {
651	641	ier_bits \|= IER_RDREQE \| IER_RDMAE;
652	642	desc_rx = dmaengine_prep_slave_single(p->master->dma_rx,
653	643	p->rx_dma_addr, len, DMA_FROM_DEVICE,
654	644	DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
655		- if (!desc_rx)
656		- return -EAGAIN;
657		- }
	645	+ if (!desc_rx) {
	646	+ ret = -EAGAIN;
	647	+ goto no_dma_rx;
	648	+ }
658	649
659		- /* 1 stage FIFO watermarks for DMA */
660		- sh_msiof_write(p, FCTR, FCTR_TFWM_1 \| FCTR_RFWM_1);
661		-
662		- /* setup msiof transfer mode registers (32-bit words) */
663		- sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);
664		-
665		- sh_msiof_write(p, IER, ier_bits);
666		-
667		- reinit_completion(&p->done);
668		-
669		- if (rx) {
670	650	desc_rx->callback = sh_msiof_dma_complete;
671	651	desc_rx->callback_param = p;
672	652	cookie = dmaengine_submit(desc_rx);
673	653	if (dma_submit_error(cookie)) {
674	654	ret = cookie;
675		- goto stop_ier;
	655	+ goto no_dma_rx;
676	656	}
677		- dma_async_issue_pending(p->master->dma_rx);
678	657	}
679	658
680	659	if (tx) {
	660	+ ier_bits \|= IER_TDREQE \| IER_TDMAE;
	661	+ dma_sync_single_for_device(p->master->dma_tx->device->dev,
	662	+ p->tx_dma_addr, len, DMA_TO_DEVICE);
	663	+ desc_tx = dmaengine_prep_slave_single(p->master->dma_tx,
	664	+ p->tx_dma_addr, len, DMA_TO_DEVICE,
	665	+ DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
	666	+ if (!desc_tx) {
	667	+ ret = -EAGAIN;
	668	+ goto no_dma_tx;
	669	+ }
	670	+
681	671	if (rx) {
682	672	/* No callback */
683	673	desc_tx->callback = NULL;
684	674
685	675
686	676
...	...	@@ -688,15 +678,30 @@
688	678	cookie = dmaengine_submit(desc_tx);
689	679	if (dma_submit_error(cookie)) {
690	680	ret = cookie;
691		- goto stop_rx;
	681	+ goto no_dma_tx;
692	682	}
693		- dma_async_issue_pending(p->master->dma_tx);
694	683	}
695	684
	685	+ /* 1 stage FIFO watermarks for DMA */
	686	+ sh_msiof_write(p, FCTR, FCTR_TFWM_1 \| FCTR_RFWM_1);
	687	+
	688	+ /* setup msiof transfer mode registers (32-bit words) */
	689	+ sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);
	690	+
	691	+ sh_msiof_write(p, IER, ier_bits);
	692	+
	693	+ reinit_completion(&p->done);
	694	+
	695	+ /* Now start DMA */
	696	+ if (tx)
	697	+ dma_async_issue_pending(p->master->dma_rx);
	698	+ if (rx)
	699	+ dma_async_issue_pending(p->master->dma_tx);
	700	+
696	701	ret = sh_msiof_spi_start(p, rx);
697	702	if (ret) {
698	703	dev_err(&p->pdev->dev, "failed to start hardware\n");
699		- goto stop_tx;
	704	+ goto stop_dma;
700	705	}
701	706
702	707	/* wait for tx fifo to be emptied / rx fifo to be filled */
703	708
704	709
705	710
...	...	@@ -726,14 +731,14 @@
726	731	stop_reset:
727	732	sh_msiof_reset_str(p);
728	733	sh_msiof_spi_stop(p, rx);
729		-stop_tx:
	734	+stop_dma:
730	735	if (tx)
731	736	dmaengine_terminate_all(p->master->dma_tx);
732		-stop_rx:
	737	+no_dma_tx:
733	738	if (rx)
734	739	dmaengine_terminate_all(p->master->dma_rx);
735		-stop_ier:
736	740	sh_msiof_write(p, IER, 0);
	741	+no_dma_rx:
737	742	return ret;
738	743	}
739	744