bcma: add serial console support

This adds support for serial console to bcma, when operating on an SoC. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Acked-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>

bcma: add serial console support
This adds support for serial console to bcma, when operating on an SoC. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Acked-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Hauke Mehrtens · John W. Linville
1 parent 21e0534ad7
Showing 5 changed files with 97 additions and 0 deletions Side-by-side Diff
drivers/bcma/bcma_private.h
drivers/bcma/driver_chipcommon.c
drivers/bcma/driver_chipcommon_pmu.c
drivers/bcma/driver_mips.c
include/linux/bcma/bcma_driver_chipcommon.h
@@ -29,6 +29,14 @@
 /* sprom.c */
 int bcma_sprom_get(struct bcma_bus *bus);
  
+/* driver_chipcommon.c */
+#ifdef CONFIG_BCMA_DRIVER_MIPS
+void bcma_chipco_serial_init(struct bcma_drv_cc *cc);
+#endif /* CONFIG_BCMA_DRIVER_MIPS */
+
+/* driver_chipcommon_pmu.c */
+u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
+
 #ifdef CONFIG_BCMA_HOST_PCI
 /* host_pci.c */
 extern int __init bcma_host_pci_init(void);
@@ -106,4 +106,52 @@
 {
 	return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
 }
+
+#ifdef CONFIG_BCMA_DRIVER_MIPS
+void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
+{
+	unsigned int irq;
+	u32 baud_base;
+	u32 i;
+	unsigned int ccrev = cc->core->id.rev;
+	struct bcma_serial_port *ports = cc->serial_ports;
+
+	if (ccrev >= 11 && ccrev != 15) {
+		/* Fixed ALP clock */
+		baud_base = bcma_pmu_alp_clock(cc);
+		if (ccrev >= 21) {
+			/* Turn off UART clock before switching clocksource. */
+			bcma_cc_write32(cc, BCMA_CC_CORECTL,
+				       bcma_cc_read32(cc, BCMA_CC_CORECTL)
+				       & ~BCMA_CC_CORECTL_UARTCLKEN);
+		}
+		/* Set the override bit so we don't divide it */
+		bcma_cc_write32(cc, BCMA_CC_CORECTL,
+			       bcma_cc_read32(cc, BCMA_CC_CORECTL)
+			       | BCMA_CC_CORECTL_UARTCLK0);
+		if (ccrev >= 21) {
+			/* Re-enable the UART clock. */
+			bcma_cc_write32(cc, BCMA_CC_CORECTL,
+				       bcma_cc_read32(cc, BCMA_CC_CORECTL)
+				       | BCMA_CC_CORECTL_UARTCLKEN);
+		}
+	} else {
+		pr_err("serial not supported on this device ccrev: 0x%x\n",
+		       ccrev);
+		return;
+	}
+
+	irq = bcma_core_mips_irq(cc->core);
+
+	/* Determine the registers of the UARTs */
+	cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
+	for (i = 0; i < cc->nr_serial_ports; i++) {
+		ports[i].regs = cc->core->io_addr + BCMA_CC_UART0_DATA +
+				(i * 256);
+		ports[i].irq = irq;
+		ports[i].baud_base = baud_base;
+		ports[i].reg_shift = 0;
+	}
+}
+#endif /* CONFIG_BCMA_DRIVER_MIPS */
@@ -136,4 +136,30 @@
 	bcma_pmu_swreg_init(cc);
 	bcma_pmu_workarounds(cc);
 }
+
+u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
+{
+	struct bcma_bus *bus = cc->core->bus;
+
+	switch (bus->chipinfo.id) {
+	case 0x4716:
+	case 0x4748:
+	case 47162:
+	case 0x4313:
+	case 0x5357:
+	case 0x4749:
+	case 53572:
+		/* always 20Mhz */
+		return 20000 * 1000;
+	case 0x5356:
+	case 0x5300:
+		/* always 25Mhz */
+		return 25000 * 1000;
+	default:
+		pr_warn("No ALP clock specified for %04X device, "
+			"pmu rev. %d, using default %d Hz\n",
+			bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
+	}
+	return BCMA_CC_PMU_ALP_CLOCK;
+}
@@ -238,6 +238,7 @@
 	if (mcore->setup_done)
 		return;
  
+	bcma_chipco_serial_init(&bus->drv_cc);
 	bcma_core_mips_flash_detect(mcore);
 	mcore->setup_done = true;
 }
@@ -241,6 +241,9 @@
 #define BCMA_CC_SPROM			0x0800 /* SPROM beginning */
 #define BCMA_CC_SPROM_PCIE6		0x0830 /* SPROM beginning on PCIe rev >= 6 */
  
+/* ALP clock on pre-PMU chips */
+#define BCMA_CC_PMU_ALP_CLOCK		20000000
+
 /* Data for the PMU, if available.
  * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
  */
@@ -255,6 +258,14 @@
 	u32 window;
 	u32 window_size;
 };
+
+struct bcma_serial_port {
+	void *regs;
+	unsigned long clockspeed;
+	unsigned int irq;
+	unsigned int baud_base;
+	unsigned int reg_shift;
+};
 #endif /* CONFIG_BCMA_DRIVER_MIPS */
  
 struct bcma_drv_cc {
@@ -268,6 +279,9 @@
 	struct bcma_chipcommon_pmu pmu;
 #ifdef CONFIG_BCMA_DRIVER_MIPS
 	struct bcma_pflash pflash;
+
+	int nr_serial_ports;
+	struct bcma_serial_port serial_ports[4];
 #endif /* CONFIG_BCMA_DRIVER_MIPS */
 };
...	...	@@ -29,6 +29,14 @@
29	29	/* sprom.c */
30	30	int bcma_sprom_get(struct bcma_bus *bus);
31	31
	32	+/* driver_chipcommon.c */
	33	+#ifdef CONFIG_BCMA_DRIVER_MIPS
	34	+void bcma_chipco_serial_init(struct bcma_drv_cc *cc);
	35	+#endif /* CONFIG_BCMA_DRIVER_MIPS */
	36	+
	37	+/* driver_chipcommon_pmu.c */
	38	+u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
	39	+
32	40	#ifdef CONFIG_BCMA_HOST_PCI
33	41	/* host_pci.c */
34	42	extern int __init bcma_host_pci_init(void);
...	...	@@ -106,4 +106,52 @@
106	106	{
107	107	return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
108	108	}
	109	+
	110	+#ifdef CONFIG_BCMA_DRIVER_MIPS
	111	+void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
	112	+{
	113	+ unsigned int irq;
	114	+ u32 baud_base;
	115	+ u32 i;
	116	+ unsigned int ccrev = cc->core->id.rev;
	117	+ struct bcma_serial_port *ports = cc->serial_ports;
	118	+
	119	+ if (ccrev >= 11 && ccrev != 15) {
	120	+ /* Fixed ALP clock */
	121	+ baud_base = bcma_pmu_alp_clock(cc);
	122	+ if (ccrev >= 21) {
	123	+ /* Turn off UART clock before switching clocksource. */
	124	+ bcma_cc_write32(cc, BCMA_CC_CORECTL,
	125	+ bcma_cc_read32(cc, BCMA_CC_CORECTL)
	126	+ & ~BCMA_CC_CORECTL_UARTCLKEN);
	127	+ }
	128	+ /* Set the override bit so we don't divide it */
	129	+ bcma_cc_write32(cc, BCMA_CC_CORECTL,
	130	+ bcma_cc_read32(cc, BCMA_CC_CORECTL)
	131	+ \| BCMA_CC_CORECTL_UARTCLK0);
	132	+ if (ccrev >= 21) {
	133	+ /* Re-enable the UART clock. */
	134	+ bcma_cc_write32(cc, BCMA_CC_CORECTL,
	135	+ bcma_cc_read32(cc, BCMA_CC_CORECTL)
	136	+ \| BCMA_CC_CORECTL_UARTCLKEN);
	137	+ }
	138	+ } else {
	139	+ pr_err("serial not supported on this device ccrev: 0x%x\n",
	140	+ ccrev);
	141	+ return;
	142	+ }
	143	+
	144	+ irq = bcma_core_mips_irq(cc->core);
	145	+
	146	+ /* Determine the registers of the UARTs */
	147	+ cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
	148	+ for (i = 0; i < cc->nr_serial_ports; i++) {
	149	+ ports[i].regs = cc->core->io_addr + BCMA_CC_UART0_DATA +
	150	+ (i * 256);
	151	+ ports[i].irq = irq;
	152	+ ports[i].baud_base = baud_base;
	153	+ ports[i].reg_shift = 0;
	154	+ }
	155	+}
	156	+#endif /* CONFIG_BCMA_DRIVER_MIPS */
...	...	@@ -136,4 +136,30 @@
136	136	bcma_pmu_swreg_init(cc);
137	137	bcma_pmu_workarounds(cc);
138	138	}
	139	+
	140	+u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
	141	+{
	142	+ struct bcma_bus *bus = cc->core->bus;
	143	+
	144	+ switch (bus->chipinfo.id) {
	145	+ case 0x4716:
	146	+ case 0x4748:
	147	+ case 47162:
	148	+ case 0x4313:
	149	+ case 0x5357:
	150	+ case 0x4749:
	151	+ case 53572:
	152	+ /* always 20Mhz */
	153	+ return 20000 * 1000;
	154	+ case 0x5356:
	155	+ case 0x5300:
	156	+ /* always 25Mhz */
	157	+ return 25000 * 1000;
	158	+ default:
	159	+ pr_warn("No ALP clock specified for %04X device, "
	160	+ "pmu rev. %d, using default %d Hz\n",
	161	+ bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
	162	+ }
	163	+ return BCMA_CC_PMU_ALP_CLOCK;
	164	+}
...	...	@@ -238,6 +238,7 @@
238	238	if (mcore->setup_done)
239	239	return;
240	240
	241	+ bcma_chipco_serial_init(&bus->drv_cc);
241	242	bcma_core_mips_flash_detect(mcore);
242	243	mcore->setup_done = true;
243	244	}
...	...	@@ -241,6 +241,9 @@
241	241	#define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
242	242	#define BCMA_CC_SPROM_PCIE6 0x0830 /* SPROM beginning on PCIe rev >= 6 */
243	243
	244	+/* ALP clock on pre-PMU chips */
	245	+#define BCMA_CC_PMU_ALP_CLOCK 20000000
	246	+
244	247	/* Data for the PMU, if available.
245	248	* Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
246	249	*/
...	...	@@ -255,6 +258,14 @@
255	258	u32 window;
256	259	u32 window_size;
257	260	};
	261	+
	262	+struct bcma_serial_port {
	263	+ void *regs;
	264	+ unsigned long clockspeed;
	265	+ unsigned int irq;
	266	+ unsigned int baud_base;
	267	+ unsigned int reg_shift;
	268	+};
258	269	#endif /* CONFIG_BCMA_DRIVER_MIPS */
259	270
260	271	struct bcma_drv_cc {
...	...	@@ -268,6 +279,9 @@
268	279	struct bcma_chipcommon_pmu pmu;
269	280	#ifdef CONFIG_BCMA_DRIVER_MIPS
270	281	struct bcma_pflash pflash;
	282	+
	283	+ int nr_serial_ports;
	284	+ struct bcma_serial_port serial_ports[4];
271	285	#endif /* CONFIG_BCMA_DRIVER_MIPS */
272	286	};
273	287