drm/i915/vlv: Make the vlv_dpio_read/vlv_dpio_write more PHY centric

vlv_dpio_read/write should be describe more in PHY centric instead of display controller centric. Create a enum dpio_channel for channel index and enum dpio_phy for PHY index. This should better to gather for upcoming platform. v2: Rebase the code based on drm/i915/vlv: Fix typo in the DPIO register define. v3: Rename vlv_phy to dpio_phy_iosf_port and define additional macro DPIO_PHY, and remove unrelated change. (Ville) Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

drm/i915/vlv: Make the vlv_dpio_read/vlv_dpio_write more PHY centric
vlv_dpio_read/write should be describe more in PHY centric instead of display controller centric. Create a enum dpio_channel for channel index and enum dpio_phy for PHY index. This should better to gather for upcoming platform. v2: Rebase the code based on drm/i915/vlv: Fix typo in the DPIO register define. v3: Rename vlv_phy to dpio_phy_iosf_port and define additional macro DPIO_PHY, and remove unrelated change. (Ville) Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Chon Ming Lee · Daniel Vetter
1 parent 00fe639a56
Showing 7 changed files with 42 additions and 26 deletions Side-by-side Diff
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_display.c
drivers/gpu/drm/i915/intel_dp.c
drivers/gpu/drm/i915/intel_drv.h
drivers/gpu/drm/i915/intel_hdmi.c
drivers/gpu/drm/i915/intel_sideband.c
@@ -88,6 +88,18 @@
 };
 #define port_name(p) ((p) + 'A')
  
+#define I915_NUM_PHYS_VLV 1
+
+enum dpio_channel {
+	DPIO_CH0,
+	DPIO_CH1
+};
+
+enum dpio_phy {
+	DPIO_PHY0,
+	DPIO_PHY1
+};
+
 enum intel_display_power_domain {
 	POWER_DOMAIN_PIPE_A,
 	POWER_DOMAIN_PIPE_B,
@@ -1403,6 +1415,7 @@
 	int num_shared_dpll;
 	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
 	struct intel_ddi_plls ddi_plls;
+	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
  
 	/* Reclocking support */
 	bool render_reclock_avail;
@@ -452,6 +452,9 @@
 #define  DPIO_SFR_BYPASS		(1<<1)
 #define  DPIO_CMNRST			(1<<0)
  
+#define DPIO_PHY(pipe)			((pipe) >> 1)
+#define DPIO_PHY_IOSF_PORT(phy)		(dev_priv->dpio_phy_iosf_port[phy])
+
 /*
  * Per pipe/PLL DPIO regs
  */
@@ -1361,6 +1361,7 @@
 	if (!IS_VALLEYVIEW(dev))
 		return;
  
+	DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 	/*
 	 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
 	 *  6.	De-assert cmn_reset/side_reset. Same as VLV X0.
  
  
  
  
@@ -1494,18 +1495,25 @@
 	POSTING_READ(DPLL(pipe));
 }
  
-void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
+void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
+		struct intel_digital_port *dport)
 {
 	u32 port_mask;
  
-	if (!port)
+	switch (dport->port) {
+	case PORT_B:
 		port_mask = DPLL_PORTB_READY_MASK;
-	else
+		break;
+	case PORT_C:
 		port_mask = DPLL_PORTC_READY_MASK;
+		break;
+	default:
+		BUG();
+	}
  
 	if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
 		WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
-		     'B' + port, I915_READ(DPLL(0)));
+		     'B' + dport->port, I915_READ(DPLL(0)));
 }
  
 /**
@@ -1839,7 +1839,7 @@
 	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
-	int port = vlv_dport_to_channel(dport);
+	enum dpio_channel port = vlv_dport_to_channel(dport);
 	int pipe = intel_crtc->pipe;
 	struct edp_power_seq power_seq;
 	u32 val;
@@ -1866,7 +1866,7 @@
  
 	intel_enable_dp(encoder);
  
-	vlv_wait_port_ready(dev_priv, port);
+	vlv_wait_port_ready(dev_priv, dport);
 }
  
 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
@@ -1876,7 +1876,7 @@
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc =
 		to_intel_crtc(encoder->base.crtc);
-	int port = vlv_dport_to_channel(dport);
+	enum dpio_channel port = vlv_dport_to_channel(dport);
 	int pipe = intel_crtc->pipe;
  
 	/* Program Tx lane resets to default */
@@ -2033,7 +2033,7 @@
 	unsigned long demph_reg_value, preemph_reg_value,
 		uniqtranscale_reg_value;
 	uint8_t train_set = intel_dp->train_set[0];
-	int port = vlv_dport_to_channel(dport);
+	enum dpio_channel port = vlv_dport_to_channel(dport);
 	int pipe = intel_crtc->pipe;
  
 	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
@@ -490,9 +490,9 @@
 {
 	switch (dport->port) {
 	case PORT_B:
-		return 0;
+		return DPIO_CH0;
 	case PORT_C:
-		return 1;
+		return DPIO_CH1;
 	default:
 		BUG();
 	}
@@ -637,7 +637,8 @@
 void intel_wait_for_vblank(struct drm_device *dev, int pipe);
 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
-void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port);
+void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
+			 struct intel_digital_port *dport);
 bool intel_get_load_detect_pipe(struct drm_connector *connector,
 				struct drm_display_mode *mode,
 				struct intel_load_detect_pipe *old);
@@ -1081,7 +1081,7 @@
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc =
 		to_intel_crtc(encoder->base.crtc);
-	int port = vlv_dport_to_channel(dport);
+	enum dpio_channel port = vlv_dport_to_channel(dport);
 	int pipe = intel_crtc->pipe;
 	u32 val;
  
@@ -1116,7 +1116,7 @@
  
 	intel_enable_hdmi(encoder);
  
-	vlv_wait_port_ready(dev_priv, port);
+	vlv_wait_port_ready(dev_priv, dport);
 }
  
 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
@@ -1126,7 +1126,7 @@
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc =
 		to_intel_crtc(encoder->base.crtc);
-	int port = vlv_dport_to_channel(dport);
+	enum dpio_channel port = vlv_dport_to_channel(dport);
 	int pipe = intel_crtc->pipe;
  
 	if (!IS_VALLEYVIEW(dev))
@@ -1159,7 +1159,7 @@
 	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 	struct intel_crtc *intel_crtc =
 		to_intel_crtc(encoder->base.crtc);
-	int port = vlv_dport_to_channel(dport);
+	enum dpio_channel port = vlv_dport_to_channel(dport);
 	int pipe = intel_crtc->pipe;
  
 	/* Reset lanes to avoid HDMI flicker (VLV w/a) */
@@ -176,27 +176,18 @@
 			PUNIT_OPCODE_REG_WRITE, reg, &val);
 }
  
-static u32 vlv_get_phy_port(enum pipe pipe)
-{
-	u32 port = IOSF_PORT_DPIO;
-
-	WARN_ON ((pipe != PIPE_A) && (pipe != PIPE_B));
-
-	return port;
-}
-
 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
 {
 	u32 val = 0;
  
-	vlv_sideband_rw(dev_priv, DPIO_DEVFN, vlv_get_phy_port(pipe),
+	vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
 			DPIO_OPCODE_REG_READ, reg, &val);
 	return val;
 }
  
 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val)
 {
-	vlv_sideband_rw(dev_priv, DPIO_DEVFN, vlv_get_phy_port(pipe),
+	vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
 			DPIO_OPCODE_REG_WRITE, reg, &val);
 }
...	...	@@ -88,6 +88,18 @@
88	88	};
89	89	#define port_name(p) ((p) + 'A')
90	90
	91	+#define I915_NUM_PHYS_VLV 1
	92	+
	93	+enum dpio_channel {
	94	+ DPIO_CH0,
	95	+ DPIO_CH1
	96	+};
	97	+
	98	+enum dpio_phy {
	99	+ DPIO_PHY0,
	100	+ DPIO_PHY1
	101	+};
	102	+
91	103	enum intel_display_power_domain {
92	104	POWER_DOMAIN_PIPE_A,
93	105	POWER_DOMAIN_PIPE_B,
...	...	@@ -1403,6 +1415,7 @@
1403	1415	int num_shared_dpll;
1404	1416	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1405	1417	struct intel_ddi_plls ddi_plls;
	1418	+ int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1406	1419
1407	1420	/* Reclocking support */
1408	1421	bool render_reclock_avail;
...	...	@@ -452,6 +452,9 @@
452	452	#define DPIO_SFR_BYPASS (1<<1)
453	453	#define DPIO_CMNRST (1<<0)
454	454
	455	+#define DPIO_PHY(pipe) ((pipe) >> 1)
	456	+#define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy])
	457	+
455	458	/*
456	459	* Per pipe/PLL DPIO regs
457	460	*/
...	...	@@ -1361,6 +1361,7 @@
1361	1361	if (!IS_VALLEYVIEW(dev))
1362	1362	return;
1363	1363
	1364	+ DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1364	1365	/*
1365	1366	* From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1366	1367	* 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1367	1368
1368	1369
1369	1370
1370	1371
...	...	@@ -1494,18 +1495,25 @@
1494	1495	POSTING_READ(DPLL(pipe));
1495	1496	}
1496	1497
1497		-void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
	1498	+void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
	1499	+ struct intel_digital_port *dport)
1498	1500	{
1499	1501	u32 port_mask;
1500	1502
1501		- if (!port)
	1503	+ switch (dport->port) {
	1504	+ case PORT_B:
1502	1505	port_mask = DPLL_PORTB_READY_MASK;
1503		- else
	1506	+ break;
	1507	+ case PORT_C:
1504	1508	port_mask = DPLL_PORTC_READY_MASK;
	1509	+ break;
	1510	+ default:
	1511	+ BUG();
	1512	+ }
1505	1513
1506	1514	if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1507	1515	WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1508		- 'B' + port, I915_READ(DPLL(0)));
	1516	+ 'B' + dport->port, I915_READ(DPLL(0)));
1509	1517	}
1510	1518
1511	1519	/**
...	...	@@ -1839,7 +1839,7 @@
1839	1839	struct drm_device *dev = encoder->base.dev;
1840	1840	struct drm_i915_private *dev_priv = dev->dev_private;
1841	1841	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1842		- int port = vlv_dport_to_channel(dport);
	1842	+ enum dpio_channel port = vlv_dport_to_channel(dport);
1843	1843	int pipe = intel_crtc->pipe;
1844	1844	struct edp_power_seq power_seq;
1845	1845	u32 val;
...	...	@@ -1866,7 +1866,7 @@
1866	1866
1867	1867	intel_enable_dp(encoder);
1868	1868
1869		- vlv_wait_port_ready(dev_priv, port);
	1869	+ vlv_wait_port_ready(dev_priv, dport);
1870	1870	}
1871	1871
1872	1872	static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
...	...	@@ -1876,7 +1876,7 @@
1876	1876	struct drm_i915_private *dev_priv = dev->dev_private;
1877	1877	struct intel_crtc *intel_crtc =
1878	1878	to_intel_crtc(encoder->base.crtc);
1879		- int port = vlv_dport_to_channel(dport);
	1879	+ enum dpio_channel port = vlv_dport_to_channel(dport);
1880	1880	int pipe = intel_crtc->pipe;
1881	1881
1882	1882	/* Program Tx lane resets to default */
...	...	@@ -2033,7 +2033,7 @@
2033	2033	unsigned long demph_reg_value, preemph_reg_value,
2034	2034	uniqtranscale_reg_value;
2035	2035	uint8_t train_set = intel_dp->train_set[0];
2036		- int port = vlv_dport_to_channel(dport);
	2036	+ enum dpio_channel port = vlv_dport_to_channel(dport);
2037	2037	int pipe = intel_crtc->pipe;
2038	2038
2039	2039	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
...	...	@@ -490,9 +490,9 @@
490	490	{
491	491	switch (dport->port) {
492	492	case PORT_B:
493		- return 0;
	493	+ return DPIO_CH0;
494	494	case PORT_C:
495		- return 1;
	495	+ return DPIO_CH1;
496	496	default:
497	497	BUG();
498	498	}
...	...	@@ -637,7 +637,8 @@
637	637	void intel_wait_for_vblank(struct drm_device *dev, int pipe);
638	638	void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
639	639	int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
640		-void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port);
	640	+void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
	641	+ struct intel_digital_port *dport);
641	642	bool intel_get_load_detect_pipe(struct drm_connector *connector,
642	643	struct drm_display_mode *mode,
643	644	struct intel_load_detect_pipe *old);
...	...	@@ -1081,7 +1081,7 @@
1081	1081	struct drm_i915_private *dev_priv = dev->dev_private;
1082	1082	struct intel_crtc *intel_crtc =
1083	1083	to_intel_crtc(encoder->base.crtc);
1084		- int port = vlv_dport_to_channel(dport);
	1084	+ enum dpio_channel port = vlv_dport_to_channel(dport);
1085	1085	int pipe = intel_crtc->pipe;
1086	1086	u32 val;
1087	1087
...	...	@@ -1116,7 +1116,7 @@
1116	1116
1117	1117	intel_enable_hdmi(encoder);
1118	1118
1119		- vlv_wait_port_ready(dev_priv, port);
	1119	+ vlv_wait_port_ready(dev_priv, dport);
1120	1120	}
1121	1121
1122	1122	static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
...	...	@@ -1126,7 +1126,7 @@
1126	1126	struct drm_i915_private *dev_priv = dev->dev_private;
1127	1127	struct intel_crtc *intel_crtc =
1128	1128	to_intel_crtc(encoder->base.crtc);
1129		- int port = vlv_dport_to_channel(dport);
	1129	+ enum dpio_channel port = vlv_dport_to_channel(dport);
1130	1130	int pipe = intel_crtc->pipe;
1131	1131
1132	1132	if (!IS_VALLEYVIEW(dev))
...	...	@@ -1159,7 +1159,7 @@
1159	1159	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1160	1160	struct intel_crtc *intel_crtc =
1161	1161	to_intel_crtc(encoder->base.crtc);
1162		- int port = vlv_dport_to_channel(dport);
	1162	+ enum dpio_channel port = vlv_dport_to_channel(dport);
1163	1163	int pipe = intel_crtc->pipe;
1164	1164
1165	1165	/* Reset lanes to avoid HDMI flicker (VLV w/a) */
...	...	@@ -176,27 +176,18 @@
176	176	PUNIT_OPCODE_REG_WRITE, reg, &val);
177	177	}
178	178
179		-static u32 vlv_get_phy_port(enum pipe pipe)
180		-{
181		- u32 port = IOSF_PORT_DPIO;
182		-
183		- WARN_ON ((pipe != PIPE_A) && (pipe != PIPE_B));
184		-
185		- return port;
186		-}
187		-
188	179	u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
189	180	{
190	181	u32 val = 0;
191	182
192		- vlv_sideband_rw(dev_priv, DPIO_DEVFN, vlv_get_phy_port(pipe),
	183	+ vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
193	184	DPIO_OPCODE_REG_READ, reg, &val);
194	185	return val;
195	186	}
196	187
197	188	void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val)
198	189	{
199		- vlv_sideband_rw(dev_priv, DPIO_DEVFN, vlv_get_phy_port(pipe),
	190	+ vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
200	191	DPIO_OPCODE_REG_WRITE, reg, &val);
201	192	}
202	193