Eric Lee / smarc-ti-linux-kernel | Embedian Git Server

Commit e83ce4a51757cf63970a76090662f636112231a7

Authored by Takashi Iwai 2014-12-30 23:17:13 +0800

Exists in ti-lsk-linux-4.1.y and in 10 other branches

Merge tag 'asoc-fix-v3.19-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/…

…broonie/sound into for-linus

ASoC: Fixes for v3.19

A few fixes for v3.19, a few driver specifics and one core fix which
fixes a boot crash on OMAP if deferred probing kicks in due to
attempting to modify static data.

Showing 9 changed files Inline Diff

sound/soc/codecs/rt5677.c
sound/soc/dwc/designware_i2s.c
sound/soc/intel/Kconfig
sound/soc/intel/bytcr_dpcm_rt5640.c
sound/soc/intel/sst-firmware.c
sound/soc/intel/sst/sst_acpi.c
sound/soc/rockchip/rockchip_i2s.c
sound/soc/rockchip/rockchip_i2s.h
sound/soc/soc-core.c

sound/soc/codecs/rt5677.c

Diff comments View file @ e83ce4a

 /*
  * rt5677.c  --  RT5677 ALSA SoC audio codec driver
  *
  * Copyright 2013 Realtek Semiconductor Corp.
  * Author: Oder Chiou <oder_chiou@realtek.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 #include <linux/fs.h>
 #include <linux/module.h>
 #include <linux/moduleparam.h>
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/pm.h>
 #include <linux/of_gpio.h>
 #include <linux/regmap.h>
 #include <linux/i2c.h>
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
 #include <linux/firmware.h>
 #include <linux/gpio.h>
 #include <sound/core.h>
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
 #include <sound/soc-dapm.h>
 #include <sound/initval.h>
 #include <sound/tlv.h>
 #include "rl6231.h"
 #include "rt5677.h"
 #include "rt5677-spi.h"
 #define RT5677_DEVICE_ID 0x6327
 #define RT5677_PR_RANGE_BASE (0xff + 1)
 #define RT5677_PR_SPACING 0x100
 #define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
 static const struct regmap_range_cfg rt5677_ranges[] = {
 	{
 		.name = "PR",
 		.range_min = RT5677_PR_BASE,
 		.range_max = RT5677_PR_BASE + 0xfd,
 		.selector_reg = RT5677_PRIV_INDEX,
 		.selector_mask = 0xff,
 		.selector_shift = 0x0,
 		.window_start = RT5677_PRIV_DATA,
 		.window_len = 0x1,
 	},
 };
 static const struct reg_default init_list[] = {
 	{RT5677_ASRC_12,	0x0018},
 	{RT5677_PR_BASE + 0x3d,	0x364d},
 	{RT5677_PR_BASE + 0x17,	0x4fc0},
 	{RT5677_PR_BASE + 0x13,	0x0312},
 	{RT5677_PR_BASE + 0x1e,	0x0000},
 	{RT5677_PR_BASE + 0x12,	0x0eaa},
 	{RT5677_PR_BASE + 0x14,	0x018a},
 };
 #define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
 static const struct reg_default rt5677_reg[] = {
 	{RT5677_RESET			, 0x0000},
 	{RT5677_LOUT1			, 0xa800},
 	{RT5677_IN1			, 0x0000},
 	{RT5677_MICBIAS			, 0x0000},
 	{RT5677_SLIMBUS_PARAM		, 0x0000},
 	{RT5677_SLIMBUS_RX		, 0x0000},
 	{RT5677_SLIMBUS_CTRL		, 0x0000},
 	{RT5677_SIDETONE_CTRL		, 0x000b},
 	{RT5677_ANA_DAC1_2_3_SRC	, 0x0000},
 	{RT5677_IF_DSP_DAC3_4_MIXER	, 0x1111},
 	{RT5677_DAC4_DIG_VOL		, 0xafaf},
 	{RT5677_DAC3_DIG_VOL		, 0xafaf},
 	{RT5677_DAC1_DIG_VOL		, 0xafaf},
 	{RT5677_DAC2_DIG_VOL		, 0xafaf},
 	{RT5677_IF_DSP_DAC2_MIXER	, 0x0011},
 	{RT5677_STO1_ADC_DIG_VOL	, 0x2f2f},
 	{RT5677_MONO_ADC_DIG_VOL	, 0x2f2f},
 	{RT5677_STO1_2_ADC_BST		, 0x0000},
 	{RT5677_STO2_ADC_DIG_VOL	, 0x2f2f},
 	{RT5677_ADC_BST_CTRL2		, 0x0000},
 	{RT5677_STO3_4_ADC_BST		, 0x0000},
 	{RT5677_STO3_ADC_DIG_VOL	, 0x2f2f},
 	{RT5677_STO4_ADC_DIG_VOL	, 0x2f2f},
 	{RT5677_STO4_ADC_MIXER		, 0xd4c0},
 	{RT5677_STO3_ADC_MIXER		, 0xd4c0},
 	{RT5677_STO2_ADC_MIXER		, 0xd4c0},
 	{RT5677_STO1_ADC_MIXER		, 0xd4c0},
 	{RT5677_MONO_ADC_MIXER		, 0xd4d1},
 	{RT5677_ADC_IF_DSP_DAC1_MIXER	, 0x8080},
 	{RT5677_STO1_DAC_MIXER		, 0xaaaa},
 	{RT5677_MONO_DAC_MIXER		, 0xaaaa},
 	{RT5677_DD1_MIXER		, 0xaaaa},
 	{RT5677_DD2_MIXER		, 0xaaaa},
 	{RT5677_IF3_DATA		, 0x0000},
 	{RT5677_IF4_DATA		, 0x0000},
 	{RT5677_PDM_OUT_CTRL		, 0x8888},
 	{RT5677_PDM_DATA_CTRL1		, 0x0000},
 	{RT5677_PDM_DATA_CTRL2		, 0x0000},
 	{RT5677_PDM1_DATA_CTRL2		, 0x0000},
 	{RT5677_PDM1_DATA_CTRL3		, 0x0000},
 	{RT5677_PDM1_DATA_CTRL4		, 0x0000},
 	{RT5677_PDM2_DATA_CTRL2		, 0x0000},
 	{RT5677_PDM2_DATA_CTRL3		, 0x0000},
 	{RT5677_PDM2_DATA_CTRL4		, 0x0000},
 	{RT5677_TDM1_CTRL1		, 0x0300},
 	{RT5677_TDM1_CTRL2		, 0x0000},
 	{RT5677_TDM1_CTRL3		, 0x4000},
 	{RT5677_TDM1_CTRL4		, 0x0123},
 	{RT5677_TDM1_CTRL5		, 0x4567},
 	{RT5677_TDM2_CTRL1		, 0x0300},
 	{RT5677_TDM2_CTRL2		, 0x0000},
 	{RT5677_TDM2_CTRL3		, 0x4000},
 	{RT5677_TDM2_CTRL4		, 0x0123},
 	{RT5677_TDM2_CTRL5		, 0x4567},
 	{RT5677_I2C_MASTER_CTRL1	, 0x0001},
 	{RT5677_I2C_MASTER_CTRL2	, 0x0000},
 	{RT5677_I2C_MASTER_CTRL3	, 0x0000},
 	{RT5677_I2C_MASTER_CTRL4	, 0x0000},
 	{RT5677_I2C_MASTER_CTRL5	, 0x0000},
 	{RT5677_I2C_MASTER_CTRL6	, 0x0000},
 	{RT5677_I2C_MASTER_CTRL7	, 0x0000},
 	{RT5677_I2C_MASTER_CTRL8	, 0x0000},
 	{RT5677_DMIC_CTRL1		, 0x1505},
 	{RT5677_DMIC_CTRL2		, 0x0055},
 	{RT5677_HAP_GENE_CTRL1		, 0x0111},
 	{RT5677_HAP_GENE_CTRL2		, 0x0064},
 	{RT5677_HAP_GENE_CTRL3		, 0xef0e},
 	{RT5677_HAP_GENE_CTRL4		, 0xf0f0},
 	{RT5677_HAP_GENE_CTRL5		, 0xef0e},
 	{RT5677_HAP_GENE_CTRL6		, 0xf0f0},
 	{RT5677_HAP_GENE_CTRL7		, 0xef0e},
 	{RT5677_HAP_GENE_CTRL8		, 0xf0f0},
 	{RT5677_HAP_GENE_CTRL9		, 0xf000},
 	{RT5677_HAP_GENE_CTRL10		, 0x0000},
 	{RT5677_PWR_DIG1		, 0x0000},
 	{RT5677_PWR_DIG2		, 0x0000},
 	{RT5677_PWR_ANLG1		, 0x0055},
 	{RT5677_PWR_ANLG2		, 0x0000},
 	{RT5677_PWR_DSP1		, 0x0001},
 	{RT5677_PWR_DSP_ST		, 0x0000},
 	{RT5677_PWR_DSP2		, 0x0000},
 	{RT5677_ADC_DAC_HPF_CTRL1	, 0x0e00},
 	{RT5677_PRIV_INDEX		, 0x0000},
 	{RT5677_PRIV_DATA		, 0x0000},
 	{RT5677_I2S4_SDP		, 0x8000},
 	{RT5677_I2S1_SDP		, 0x8000},
 	{RT5677_I2S2_SDP		, 0x8000},
 	{RT5677_I2S3_SDP		, 0x8000},
 	{RT5677_CLK_TREE_CTRL1		, 0x1111},
 	{RT5677_CLK_TREE_CTRL2		, 0x1111},
 	{RT5677_CLK_TREE_CTRL3		, 0x0000},
 	{RT5677_PLL1_CTRL1		, 0x0000},
 	{RT5677_PLL1_CTRL2		, 0x0000},
 	{RT5677_PLL2_CTRL1		, 0x0c60},
 	{RT5677_PLL2_CTRL2		, 0x2000},
 	{RT5677_GLB_CLK1		, 0x0000},
 	{RT5677_GLB_CLK2		, 0x0000},
 	{RT5677_ASRC_1			, 0x0000},
 	{RT5677_ASRC_2			, 0x0000},
 	{RT5677_ASRC_3			, 0x0000},
 	{RT5677_ASRC_4			, 0x0000},
 	{RT5677_ASRC_5			, 0x0000},
 	{RT5677_ASRC_6			, 0x0000},
 	{RT5677_ASRC_7			, 0x0000},
 	{RT5677_ASRC_8			, 0x0000},
 	{RT5677_ASRC_9			, 0x0000},
 	{RT5677_ASRC_10			, 0x0000},
 	{RT5677_ASRC_11			, 0x0000},
 	{RT5677_ASRC_12			, 0x0018},
 	{RT5677_ASRC_13			, 0x0000},
 	{RT5677_ASRC_14			, 0x0000},
 	{RT5677_ASRC_15			, 0x0000},
 	{RT5677_ASRC_16			, 0x0000},
 	{RT5677_ASRC_17			, 0x0000},
 	{RT5677_ASRC_18			, 0x0000},
 	{RT5677_ASRC_19			, 0x0000},
 	{RT5677_ASRC_20			, 0x0000},
 	{RT5677_ASRC_21			, 0x000c},
 	{RT5677_ASRC_22			, 0x0000},
 	{RT5677_ASRC_23			, 0x0000},
 	{RT5677_VAD_CTRL1		, 0x2184},
 	{RT5677_VAD_CTRL2		, 0x010a},
 	{RT5677_VAD_CTRL3		, 0x0aea},
 	{RT5677_VAD_CTRL4		, 0x000c},
 	{RT5677_VAD_CTRL5		, 0x0000},
 	{RT5677_DSP_INB_CTRL1		, 0x0000},
 	{RT5677_DSP_INB_CTRL2		, 0x0000},
 	{RT5677_DSP_IN_OUTB_CTRL	, 0x0000},
 	{RT5677_DSP_OUTB0_1_DIG_VOL	, 0x2f2f},
 	{RT5677_DSP_OUTB2_3_DIG_VOL	, 0x2f2f},
 	{RT5677_DSP_OUTB4_5_DIG_VOL	, 0x2f2f},
 	{RT5677_DSP_OUTB6_7_DIG_VOL	, 0x2f2f},
 	{RT5677_ADC_EQ_CTRL1		, 0x6000},
 	{RT5677_ADC_EQ_CTRL2		, 0x0000},
 	{RT5677_EQ_CTRL1		, 0xc000},
 	{RT5677_EQ_CTRL2		, 0x0000},
 	{RT5677_EQ_CTRL3		, 0x0000},
 	{RT5677_SOFT_VOL_ZERO_CROSS1	, 0x0009},
 	{RT5677_JD_CTRL1		, 0x0000},
 	{RT5677_JD_CTRL2		, 0x0000},
 	{RT5677_JD_CTRL3		, 0x0000},
 	{RT5677_IRQ_CTRL1		, 0x0000},
 	{RT5677_IRQ_CTRL2		, 0x0000},
 	{RT5677_GPIO_ST			, 0x0000},
 	{RT5677_GPIO_CTRL1		, 0x0000},
 	{RT5677_GPIO_CTRL2		, 0x0000},
 	{RT5677_GPIO_CTRL3		, 0x0000},
 	{RT5677_STO1_ADC_HI_FILTER1	, 0xb320},
 	{RT5677_STO1_ADC_HI_FILTER2	, 0x0000},
 	{RT5677_MONO_ADC_HI_FILTER1	, 0xb300},
 	{RT5677_MONO_ADC_HI_FILTER2	, 0x0000},
 	{RT5677_STO2_ADC_HI_FILTER1	, 0xb300},
 	{RT5677_STO2_ADC_HI_FILTER2	, 0x0000},
 	{RT5677_STO3_ADC_HI_FILTER1	, 0xb300},
 	{RT5677_STO3_ADC_HI_FILTER2	, 0x0000},
 	{RT5677_STO4_ADC_HI_FILTER1	, 0xb300},
 	{RT5677_STO4_ADC_HI_FILTER2	, 0x0000},
 	{RT5677_MB_DRC_CTRL1		, 0x0f20},
 	{RT5677_DRC1_CTRL1		, 0x001f},
 	{RT5677_DRC1_CTRL2		, 0x020c},
 	{RT5677_DRC1_CTRL3		, 0x1f00},
 	{RT5677_DRC1_CTRL4		, 0x0000},
 	{RT5677_DRC1_CTRL5		, 0x0000},
 	{RT5677_DRC1_CTRL6		, 0x0029},
 	{RT5677_DRC2_CTRL1		, 0x001f},
 	{RT5677_DRC2_CTRL2		, 0x020c},
 	{RT5677_DRC2_CTRL3		, 0x1f00},
 	{RT5677_DRC2_CTRL4		, 0x0000},
 	{RT5677_DRC2_CTRL5		, 0x0000},
 	{RT5677_DRC2_CTRL6		, 0x0029},
 	{RT5677_DRC1_HL_CTRL1		, 0x8000},
 	{RT5677_DRC1_HL_CTRL2		, 0x0200},
 	{RT5677_DRC2_HL_CTRL1		, 0x8000},
 	{RT5677_DRC2_HL_CTRL2		, 0x0200},
 	{RT5677_DSP_INB1_SRC_CTRL1	, 0x5800},
 	{RT5677_DSP_INB1_SRC_CTRL2	, 0x0000},
 	{RT5677_DSP_INB1_SRC_CTRL3	, 0x0000},
 	{RT5677_DSP_INB1_SRC_CTRL4	, 0x0800},
 	{RT5677_DSP_INB2_SRC_CTRL1	, 0x5800},
 	{RT5677_DSP_INB2_SRC_CTRL2	, 0x0000},
 	{RT5677_DSP_INB2_SRC_CTRL3	, 0x0000},
 	{RT5677_DSP_INB2_SRC_CTRL4	, 0x0800},
 	{RT5677_DSP_INB3_SRC_CTRL1	, 0x5800},
 	{RT5677_DSP_INB3_SRC_CTRL2	, 0x0000},
 	{RT5677_DSP_INB3_SRC_CTRL3	, 0x0000},
 	{RT5677_DSP_INB3_SRC_CTRL4	, 0x0800},
 	{RT5677_DSP_OUTB1_SRC_CTRL1	, 0x5800},
 	{RT5677_DSP_OUTB1_SRC_CTRL2	, 0x0000},
 	{RT5677_DSP_OUTB1_SRC_CTRL3	, 0x0000},
 	{RT5677_DSP_OUTB1_SRC_CTRL4	, 0x0800},
 	{RT5677_DSP_OUTB2_SRC_CTRL1	, 0x5800},
 	{RT5677_DSP_OUTB2_SRC_CTRL2	, 0x0000},
 	{RT5677_DSP_OUTB2_SRC_CTRL3	, 0x0000},
 	{RT5677_DSP_OUTB2_SRC_CTRL4	, 0x0800},
 	{RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
 	{RT5677_DSP_OUTB_45_MIXER_CTRL	, 0xfefe},
 	{RT5677_DSP_OUTB_67_MIXER_CTRL	, 0xfefe},
 	{RT5677_DIG_MISC		, 0x0000},
 	{RT5677_GEN_CTRL1		, 0x0000},
 	{RT5677_GEN_CTRL2		, 0x0000},
 	{RT5677_VENDOR_ID		, 0x0000},
 	{RT5677_VENDOR_ID1		, 0x10ec},
 	{RT5677_VENDOR_ID2		, 0x6327},
 };
 static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
 {
 	int i;
 	for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
 		if (reg >= rt5677_ranges[i].range_min &&
 			reg <= rt5677_ranges[i].range_max) {
 			return true;
 		}
 	}
 	switch (reg) {
 	case RT5677_RESET:
 	case RT5677_SLIMBUS_PARAM:
 	case RT5677_PDM_DATA_CTRL1:
 	case RT5677_PDM_DATA_CTRL2:
 	case RT5677_PDM1_DATA_CTRL4:
 	case RT5677_PDM2_DATA_CTRL4:
 	case RT5677_I2C_MASTER_CTRL1:
 	case RT5677_I2C_MASTER_CTRL7:
 	case RT5677_I2C_MASTER_CTRL8:
 	case RT5677_HAP_GENE_CTRL2:
 	case RT5677_PWR_DSP_ST:
 	case RT5677_PRIV_DATA:
 	case RT5677_PLL1_CTRL2:
 	case RT5677_PLL2_CTRL2:
 	case RT5677_ASRC_22:
 	case RT5677_ASRC_23:
 	case RT5677_VAD_CTRL5:
 	case RT5677_ADC_EQ_CTRL1:
 	case RT5677_EQ_CTRL1:
 	case RT5677_IRQ_CTRL1:
 	case RT5677_IRQ_CTRL2:
 	case RT5677_GPIO_ST:
 	case RT5677_DSP_INB1_SRC_CTRL4:
 	case RT5677_DSP_INB2_SRC_CTRL4:
 	case RT5677_DSP_INB3_SRC_CTRL4:
 	case RT5677_DSP_OUTB1_SRC_CTRL4:
 	case RT5677_DSP_OUTB2_SRC_CTRL4:
 	case RT5677_VENDOR_ID:
 	case RT5677_VENDOR_ID1:
 	case RT5677_VENDOR_ID2:
 		return true;
 	default:
 		return false;
 	}
 }
 static bool rt5677_readable_register(struct device *dev, unsigned int reg)
 {
 	int i;
 	for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
 		if (reg >= rt5677_ranges[i].range_min &&
 			reg <= rt5677_ranges[i].range_max) {
 			return true;
 		}
 	}
 	switch (reg) {
 	case RT5677_RESET:
 	case RT5677_LOUT1:
 	case RT5677_IN1:
 	case RT5677_MICBIAS:
 	case RT5677_SLIMBUS_PARAM:
 	case RT5677_SLIMBUS_RX:
 	case RT5677_SLIMBUS_CTRL:
 	case RT5677_SIDETONE_CTRL:
 	case RT5677_ANA_DAC1_2_3_SRC:
 	case RT5677_IF_DSP_DAC3_4_MIXER:
 	case RT5677_DAC4_DIG_VOL:
 	case RT5677_DAC3_DIG_VOL:
 	case RT5677_DAC1_DIG_VOL:
 	case RT5677_DAC2_DIG_VOL:
 	case RT5677_IF_DSP_DAC2_MIXER:
 	case RT5677_STO1_ADC_DIG_VOL:
 	case RT5677_MONO_ADC_DIG_VOL:
 	case RT5677_STO1_2_ADC_BST:
 	case RT5677_STO2_ADC_DIG_VOL:
 	case RT5677_ADC_BST_CTRL2:
 	case RT5677_STO3_4_ADC_BST:
 	case RT5677_STO3_ADC_DIG_VOL:
 	case RT5677_STO4_ADC_DIG_VOL:
 	case RT5677_STO4_ADC_MIXER:
 	case RT5677_STO3_ADC_MIXER:
 	case RT5677_STO2_ADC_MIXER:
 	case RT5677_STO1_ADC_MIXER:
 	case RT5677_MONO_ADC_MIXER:
 	case RT5677_ADC_IF_DSP_DAC1_MIXER:
 	case RT5677_STO1_DAC_MIXER:
 	case RT5677_MONO_DAC_MIXER:
 	case RT5677_DD1_MIXER:
 	case RT5677_DD2_MIXER:
 	case RT5677_IF3_DATA:
 	case RT5677_IF4_DATA:
 	case RT5677_PDM_OUT_CTRL:
 	case RT5677_PDM_DATA_CTRL1:
 	case RT5677_PDM_DATA_CTRL2:
 	case RT5677_PDM1_DATA_CTRL2:
 	case RT5677_PDM1_DATA_CTRL3:
 	case RT5677_PDM1_DATA_CTRL4:
 	case RT5677_PDM2_DATA_CTRL2:
 	case RT5677_PDM2_DATA_CTRL3:
 	case RT5677_PDM2_DATA_CTRL4:
 	case RT5677_TDM1_CTRL1:
 	case RT5677_TDM1_CTRL2:
 	case RT5677_TDM1_CTRL3:
 	case RT5677_TDM1_CTRL4:
 	case RT5677_TDM1_CTRL5:
 	case RT5677_TDM2_CTRL1:
 	case RT5677_TDM2_CTRL2:
 	case RT5677_TDM2_CTRL3:
 	case RT5677_TDM2_CTRL4:
 	case RT5677_TDM2_CTRL5:
 	case RT5677_I2C_MASTER_CTRL1:
 	case RT5677_I2C_MASTER_CTRL2:
 	case RT5677_I2C_MASTER_CTRL3:
 	case RT5677_I2C_MASTER_CTRL4:
 	case RT5677_I2C_MASTER_CTRL5:
 	case RT5677_I2C_MASTER_CTRL6:
 	case RT5677_I2C_MASTER_CTRL7:
 	case RT5677_I2C_MASTER_CTRL8:
 	case RT5677_DMIC_CTRL1:
 	case RT5677_DMIC_CTRL2:
 	case RT5677_HAP_GENE_CTRL1:
 	case RT5677_HAP_GENE_CTRL2:
 	case RT5677_HAP_GENE_CTRL3:
 	case RT5677_HAP_GENE_CTRL4:
 	case RT5677_HAP_GENE_CTRL5:
 	case RT5677_HAP_GENE_CTRL6:
 	case RT5677_HAP_GENE_CTRL7:
 	case RT5677_HAP_GENE_CTRL8:
 	case RT5677_HAP_GENE_CTRL9:
 	case RT5677_HAP_GENE_CTRL10:
 	case RT5677_PWR_DIG1:
 	case RT5677_PWR_DIG2:
 	case RT5677_PWR_ANLG1:
 	case RT5677_PWR_ANLG2:
 	case RT5677_PWR_DSP1:
 	case RT5677_PWR_DSP_ST:
 	case RT5677_PWR_DSP2:
 	case RT5677_ADC_DAC_HPF_CTRL1:
 	case RT5677_PRIV_INDEX:
 	case RT5677_PRIV_DATA:
 	case RT5677_I2S4_SDP:
 	case RT5677_I2S1_SDP:
 	case RT5677_I2S2_SDP:
 	case RT5677_I2S3_SDP:
 	case RT5677_CLK_TREE_CTRL1:
 	case RT5677_CLK_TREE_CTRL2:
 	case RT5677_CLK_TREE_CTRL3:
 	case RT5677_PLL1_CTRL1:
 	case RT5677_PLL1_CTRL2:
 	case RT5677_PLL2_CTRL1:
 	case RT5677_PLL2_CTRL2:
 	case RT5677_GLB_CLK1:
 	case RT5677_GLB_CLK2:
 	case RT5677_ASRC_1:
 	case RT5677_ASRC_2:
 	case RT5677_ASRC_3:
 	case RT5677_ASRC_4:
 	case RT5677_ASRC_5:
 	case RT5677_ASRC_6:
 	case RT5677_ASRC_7:
 	case RT5677_ASRC_8:
 	case RT5677_ASRC_9:
 	case RT5677_ASRC_10:
 	case RT5677_ASRC_11:
 	case RT5677_ASRC_12:
 	case RT5677_ASRC_13:
 	case RT5677_ASRC_14:
 	case RT5677_ASRC_15:
 	case RT5677_ASRC_16:
 	case RT5677_ASRC_17:
 	case RT5677_ASRC_18:
 	case RT5677_ASRC_19:
 	case RT5677_ASRC_20:
 	case RT5677_ASRC_21:
 	case RT5677_ASRC_22:
 	case RT5677_ASRC_23:
 	case RT5677_VAD_CTRL1:
 	case RT5677_VAD_CTRL2:
 	case RT5677_VAD_CTRL3:
 	case RT5677_VAD_CTRL4:
 	case RT5677_VAD_CTRL5:
 	case RT5677_DSP_INB_CTRL1:
 	case RT5677_DSP_INB_CTRL2:
 	case RT5677_DSP_IN_OUTB_CTRL:
 	case RT5677_DSP_OUTB0_1_DIG_VOL:
 	case RT5677_DSP_OUTB2_3_DIG_VOL:
 	case RT5677_DSP_OUTB4_5_DIG_VOL:
 	case RT5677_DSP_OUTB6_7_DIG_VOL:
 	case RT5677_ADC_EQ_CTRL1:
 	case RT5677_ADC_EQ_CTRL2:
 	case RT5677_EQ_CTRL1:
 	case RT5677_EQ_CTRL2:
 	case RT5677_EQ_CTRL3:
 	case RT5677_SOFT_VOL_ZERO_CROSS1:
 	case RT5677_JD_CTRL1:
 	case RT5677_JD_CTRL2:
 	case RT5677_JD_CTRL3:
 	case RT5677_IRQ_CTRL1:
 	case RT5677_IRQ_CTRL2:
 	case RT5677_GPIO_ST:
 	case RT5677_GPIO_CTRL1:
 	case RT5677_GPIO_CTRL2:
 	case RT5677_GPIO_CTRL3:
 	case RT5677_STO1_ADC_HI_FILTER1:
 	case RT5677_STO1_ADC_HI_FILTER2:
 	case RT5677_MONO_ADC_HI_FILTER1:
 	case RT5677_MONO_ADC_HI_FILTER2:
 	case RT5677_STO2_ADC_HI_FILTER1:
 	case RT5677_STO2_ADC_HI_FILTER2:
 	case RT5677_STO3_ADC_HI_FILTER1:
 	case RT5677_STO3_ADC_HI_FILTER2:
 	case RT5677_STO4_ADC_HI_FILTER1:
 	case RT5677_STO4_ADC_HI_FILTER2:
 	case RT5677_MB_DRC_CTRL1:
 	case RT5677_DRC1_CTRL1:
 	case RT5677_DRC1_CTRL2:
 	case RT5677_DRC1_CTRL3:
 	case RT5677_DRC1_CTRL4:
 	case RT5677_DRC1_CTRL5:
 	case RT5677_DRC1_CTRL6:
 	case RT5677_DRC2_CTRL1:
 	case RT5677_DRC2_CTRL2:
 	case RT5677_DRC2_CTRL3:
 	case RT5677_DRC2_CTRL4:
 	case RT5677_DRC2_CTRL5:
 	case RT5677_DRC2_CTRL6:
 	case RT5677_DRC1_HL_CTRL1:
 	case RT5677_DRC1_HL_CTRL2:
 	case RT5677_DRC2_HL_CTRL1:
 	case RT5677_DRC2_HL_CTRL2:
 	case RT5677_DSP_INB1_SRC_CTRL1:
 	case RT5677_DSP_INB1_SRC_CTRL2:
 	case RT5677_DSP_INB1_SRC_CTRL3:
 	case RT5677_DSP_INB1_SRC_CTRL4:
 	case RT5677_DSP_INB2_SRC_CTRL1:
 	case RT5677_DSP_INB2_SRC_CTRL2:
 	case RT5677_DSP_INB2_SRC_CTRL3:
 	case RT5677_DSP_INB2_SRC_CTRL4:
 	case RT5677_DSP_INB3_SRC_CTRL1:
 	case RT5677_DSP_INB3_SRC_CTRL2:
 	case RT5677_DSP_INB3_SRC_CTRL3:
 	case RT5677_DSP_INB3_SRC_CTRL4:
 	case RT5677_DSP_OUTB1_SRC_CTRL1:
 	case RT5677_DSP_OUTB1_SRC_CTRL2:
 	case RT5677_DSP_OUTB1_SRC_CTRL3:
 	case RT5677_DSP_OUTB1_SRC_CTRL4:
 	case RT5677_DSP_OUTB2_SRC_CTRL1:
 	case RT5677_DSP_OUTB2_SRC_CTRL2:
 	case RT5677_DSP_OUTB2_SRC_CTRL3:
 	case RT5677_DSP_OUTB2_SRC_CTRL4:
 	case RT5677_DSP_OUTB_0123_MIXER_CTRL:
 	case RT5677_DSP_OUTB_45_MIXER_CTRL:
 	case RT5677_DSP_OUTB_67_MIXER_CTRL:
 	case RT5677_DIG_MISC:
 	case RT5677_GEN_CTRL1:
 	case RT5677_GEN_CTRL2:
 	case RT5677_VENDOR_ID:
 	case RT5677_VENDOR_ID1:
 	case RT5677_VENDOR_ID2:
 		return true;
 	default:
 		return false;
 	}
 }
 /**
  * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
  * @rt5677: Private Data.
  * @addr: Address index.
  * @value: Address data.
  *
  *
  * Returns 0 for success or negative error code.
  */
 static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677,
 		unsigned int addr, unsigned int value, unsigned int opcode)
 {
 	struct snd_soc_codec *codec = rt5677->codec;
 	int ret;
 	mutex_lock(&rt5677->dsp_cmd_lock);
 	ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
 		addr >> 16);
 	if (ret < 0) {
 		dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
 		goto err;
 	}
 	ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
 		addr & 0xffff);
 	if (ret < 0) {
 		dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
 		goto err;
 	}
 	ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
 		value >> 16);
 	if (ret < 0) {
 		dev_err(codec->dev, "Failed to set data msb value: %d\n", ret);
 		goto err;
 	}
 	ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
 		value & 0xffff);
 	if (ret < 0) {
 		dev_err(codec->dev, "Failed to set data lsb value: %d\n", ret);
 		goto err;
 	}
 	ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
 		opcode);
 	if (ret < 0) {
 		dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
 		goto err;
 	}
 err:
 	mutex_unlock(&rt5677->dsp_cmd_lock);
 	return ret;
 }
 /**
  * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
  * rt5677: Private Data.
  * @addr: Address index.
  * @value: Address data.
  *
  *
  * Returns 0 for success or negative error code.
  */
 static int rt5677_dsp_mode_i2c_read_addr(
 	struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value)
 {
 	struct snd_soc_codec *codec = rt5677->codec;
 	int ret;
 	unsigned int msb, lsb;
 	mutex_lock(&rt5677->dsp_cmd_lock);
 	ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
 		addr >> 16);
 	if (ret < 0) {
 		dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
 		goto err;
 	}
 	ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
 		addr & 0xffff);
 	if (ret < 0) {
 		dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
 		goto err;
 	}
 	ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
 		0x0002);
 	if (ret < 0) {
 		dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
 		goto err;
 	}
 	regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
 	regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
 	*value = (msb << 16) | lsb;
 err:
 	mutex_unlock(&rt5677->dsp_cmd_lock);
 	return ret;
 }
 /**
  * rt5677_dsp_mode_i2c_write - Write register on DSP mode.
  * rt5677: Private Data.
  * @reg: Register index.
  * @value: Register data.
  *
  *
  * Returns 0 for success or negative error code.
  */
 static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677,
 		unsigned int reg, unsigned int value)
 {
 	return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2,
 		value, 0x0001);
 }
 /**
  * rt5677_dsp_mode_i2c_read - Read register on DSP mode.
  * @codec: SoC audio codec device.
  * @reg: Register index.
  * @value: Register data.
  *
  *
  * Returns 0 for success or negative error code.
  */
 static int rt5677_dsp_mode_i2c_read(
 	struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value)
 {
 	int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2,
 		value);
 	*value &= 0xffff;
 	return ret;
 }
 static void rt5677_set_dsp_mode(struct snd_soc_codec *codec, bool on)
 {
 	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
 	if (on) {
 		regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x2);
 		rt5677->is_dsp_mode = true;
 	} else {
 		regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x0);
 		rt5677->is_dsp_mode = false;
 	}
 }
 static int rt5677_set_dsp_vad(struct snd_soc_codec *codec, bool on)
 {
 	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
 	static bool activity;
 	int ret;
 	if (on && !activity) {
 		activity = true;
 		regcache_cache_only(rt5677->regmap, false);
 		regcache_cache_bypass(rt5677->regmap, true);
 		regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1);
 		regmap_update_bits(rt5677->regmap,
 			RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00);
 		regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
 			RT5677_LDO1_SEL_MASK, 0x0);
 		regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
 			RT5677_PWR_LDO1, RT5677_PWR_LDO1);
 		regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
 			RT5677_MCLK_SRC_MASK, RT5677_MCLK2_SRC);
 		regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
 			RT5677_PLL2_PR_SRC_MASK | RT5677_DSP_CLK_SRC_MASK,
 			RT5677_PLL2_PR_SRC_MCLK2 | RT5677_DSP_CLK_SRC_BYPASS);
 		regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff);
 		regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd);
 		rt5677_set_dsp_mode(codec, true);
 		ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1,
 			codec->dev);
 		if (ret == 0) {
 			rt5677_spi_burst_write(0x50000000, rt5677->fw1);
 			release_firmware(rt5677->fw1);
 		}
 		ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2,
 			codec->dev);
 		if (ret == 0) {
 			rt5677_spi_burst_write(0x60000000, rt5677->fw2);
 			release_firmware(rt5677->fw2);
 		}
 		regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0);
 		regcache_cache_bypass(rt5677->regmap, false);
 		regcache_cache_only(rt5677->regmap, true);
 	} else if (!on && activity) {
 		activity = false;
 		regcache_cache_only(rt5677->regmap, false);
 		regcache_cache_bypass(rt5677->regmap, true);
 		regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1);
 		rt5677_set_dsp_mode(codec, false);
 		regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001);
 		regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
 		regcache_cache_bypass(rt5677->regmap, false);
 		regcache_mark_dirty(rt5677->regmap);
 		regcache_sync(rt5677->regmap);
 	}
 	return 0;
 }
 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
 static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
 static unsigned int bst_tlv[] = {
 	TLV_DB_RANGE_HEAD(7),
 	0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
 	1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
 	2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
 	3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
 	6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
 	7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
 	8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
 };
 static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
 		struct snd_ctl_elem_value *ucontrol)
 {
-	struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
-	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
+	struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
 	ucontrol->value.integer.value[0] = rt5677->dsp_vad_en;
 	return 0;
 }
 static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
 		struct snd_ctl_elem_value *ucontrol)
 {
-	struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
-	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
+	struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
+	struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
 	rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0];
 	if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
 		rt5677_set_dsp_vad(codec, rt5677->dsp_vad_en);
 	return 0;
 }
 static const struct snd_kcontrol_new rt5677_snd_controls[] = {
 	/* OUTPUT Control */
 	SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
 		RT5677_LOUT1_L_MUTE_SFT, 1, 1),
 	SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
 		RT5677_LOUT2_L_MUTE_SFT, 1, 1),
 	SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
 		RT5677_LOUT3_L_MUTE_SFT, 1, 1),
 	/* DAC Digital Volume */
 	SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
 		RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
 	SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
 		RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
 	SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
 		RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
 	SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
 		RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
 	/* IN1/IN2 Control */
 	SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
 	SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
 	/* ADC Digital Volume Control */
 	SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
 		RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
 	SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
 		RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
 	SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
 		RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
 	SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
 		RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
 	SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
 		RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
 	SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
 		RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
 		adc_vol_tlv),
 	SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
 		RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
 		adc_vol_tlv),
 	SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
 		RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
 		adc_vol_tlv),
 	SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
 		RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
 		adc_vol_tlv),
 	SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
 		RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0,
 		adc_vol_tlv),
 	/* Sidetone Control */
 	SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL,
 		RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv),
 	/* ADC Boost Volume Control */
 	SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
 		RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
 		adc_bst_tlv),
 	SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
 		RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
 		adc_bst_tlv),
 	SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
 		RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
 		adc_bst_tlv),
 	SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
 		RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
 		adc_bst_tlv),
 	SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
 		RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
 		adc_bst_tlv),
 	SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0,
 		rt5677_dsp_vad_get, rt5677_dsp_vad_put),
 };
 /**
  * set_dmic_clk - Set parameter of dmic.
  *
  * @w: DAPM widget.
  * @kcontrol: The kcontrol of this widget.
  * @event: Event id.
  *
  * Choose dmic clock between 1MHz and 3MHz.
  * It is better for clock to approximate 3MHz.
  */
 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
 	struct snd_kcontrol *kcontrol, int event)
 {
 	struct snd_soc_codec *codec = w->codec;
 	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
 	int idx = rl6231_calc_dmic_clk(rt5677->sysclk);
 	if (idx < 0)
 		dev_err(codec->dev, "Failed to set DMIC clock\n");
 	else
 		regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
 			RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
 	return idx;
 }
 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
 			 struct snd_soc_dapm_widget *sink)
 {
 	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(source->codec);
 	unsigned int val;
 	regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
 	val &= RT5677_SCLK_SRC_MASK;
 	if (val == RT5677_SCLK_SRC_PLL1)
 		return 1;
 	else
 		return 0;
 }
 /* Digital Mixer */
 static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
 	SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
 			RT5677_M_STO1_ADC_L1_SFT, 1, 1),
 	SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
 			RT5677_M_STO1_ADC_L2_SFT, 1, 1),
 };
 static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
 	SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
 			RT5677_M_STO1_ADC_R1_SFT, 1, 1),
 	SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
 			RT5677_M_STO1_ADC_R2_SFT, 1, 1),
 };
 static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
 	SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
 			RT5677_M_STO2_ADC_L1_SFT, 1, 1),
 	SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
 			RT5677_M_STO2_ADC_L2_SFT, 1, 1),
 };
 static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
 	SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
 			RT5677_M_STO2_ADC_R1_SFT, 1, 1),
 	SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
 			RT5677_M_STO2_ADC_R2_SFT, 1, 1),
 };
 static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
 	SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
 			RT5677_M_STO3_ADC_L1_SFT, 1, 1),
 	SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
 			RT5677_M_STO3_ADC_L2_SFT, 1, 1),
 };
 static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
 	SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
 			RT5677_M_STO3_ADC_R1_SFT, 1, 1),
 	SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
 			RT5677_M_STO3_ADC_R2_SFT, 1, 1),
 };
 static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
 	SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
 			RT5677_M_STO4_ADC_L1_SFT, 1, 1),
 	SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
 			RT5677_M_STO4_ADC_L2_SFT, 1, 1),
 };
 static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
 	SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
 			RT5677_M_STO4_ADC_R1_SFT, 1, 1),
 	SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
 			RT5677_M_STO4_ADC_R2_SFT, 1, 1),
 };
 static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
 	SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
 			RT5677_M_MONO_ADC_L1_SFT, 1, 1),
 	SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
 			RT5677_M_MONO_ADC_L2_SFT, 1, 1),
 };
 static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
 	SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
 			RT5677_M_MONO_ADC_R1_SFT, 1, 1),
 	SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
 			RT5677_M_MONO_ADC_R2_SFT, 1, 1),
 };
 static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
 	SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
 			RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
 	SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
 			RT5677_M_DAC1_L_SFT, 1, 1),
 };
 static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
 	SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
 			RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
 	SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
 			RT5677_M_DAC1_R_SFT, 1, 1),
 };
 static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
 	SOC_DAPM_SINGLE("ST L Switch", RT5677_STO1_DAC_MIXER,
 			RT5677_M_ST_DAC1_L_SFT, 1, 1),
 	SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
 			RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
 	SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
 			RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
 	SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
 			RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
 };
 static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
 	SOC_DAPM_SINGLE("ST R Switch", RT5677_STO1_DAC_MIXER,
 			RT5677_M_ST_DAC1_R_SFT, 1, 1),
 	SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
 			RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
 	SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
 			RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
 	SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
 			RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
 };
 static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
 	SOC_DAPM_SINGLE("ST L Switch", RT5677_MONO_DAC_MIXER,
 			RT5677_M_ST_DAC2_L_SFT, 1, 1),
 	SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
 			RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
 	SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
 			RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
 	SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
 			RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
 };
 static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
 	SOC_DAPM_SINGLE("ST R Switch", RT5677_MONO_DAC_MIXER,
 			RT5677_M_ST_DAC2_R_SFT, 1, 1),
 	SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
 			RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
 	SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
 			RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
 	SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
 			RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
 };
 static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
 	SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
 			RT5677_M_STO_L_DD1_L_SFT, 1, 1),
 	SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
 			RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
 	SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
 			RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
 	SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
 			RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
 };
 static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
 	SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
 			RT5677_M_STO_R_DD1_R_SFT, 1, 1),
 	SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
 			RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
 	SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
 			RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
 	SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
 			RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
 };
 static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
 	SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
 			RT5677_M_STO_L_DD2_L_SFT, 1, 1),
 	SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
 			RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
 	SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
 			RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
 	SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
 			RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
 };
 static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
 	SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
 			RT5677_M_STO_R_DD2_R_SFT, 1, 1),
 	SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
 			RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
 	SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
 			RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
 	SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
 			RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
 };
 static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
 	SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
 			RT5677_DSP_IB_01_H_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
 			RT5677_DSP_IB_23_H_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
 			RT5677_DSP_IB_45_H_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
 			RT5677_DSP_IB_6_H_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
 			RT5677_DSP_IB_7_H_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
 			RT5677_DSP_IB_8_H_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
 			RT5677_DSP_IB_9_H_SFT, 1, 1),
 };
 static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
 	SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
 			RT5677_DSP_IB_01_L_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
 			RT5677_DSP_IB_23_L_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
 			RT5677_DSP_IB_45_L_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
 			RT5677_DSP_IB_6_L_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
 			RT5677_DSP_IB_7_L_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
 			RT5677_DSP_IB_8_L_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
 			RT5677_DSP_IB_9_L_SFT, 1, 1),
 };
 static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
 	SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
 			RT5677_DSP_IB_01_H_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
 			RT5677_DSP_IB_23_H_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
 			RT5677_DSP_IB_45_H_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
 			RT5677_DSP_IB_6_H_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
 			RT5677_DSP_IB_7_H_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
 			RT5677_DSP_IB_8_H_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
 			RT5677_DSP_IB_9_H_SFT, 1, 1),
 };
 static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
 	SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
 			RT5677_DSP_IB_01_L_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
 			RT5677_DSP_IB_23_L_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
 			RT5677_DSP_IB_45_L_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
 			RT5677_DSP_IB_6_L_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
 			RT5677_DSP_IB_7_L_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
 			RT5677_DSP_IB_8_L_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
 			RT5677_DSP_IB_9_L_SFT, 1, 1),
 };
 static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
 	SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
 			RT5677_DSP_IB_01_H_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
 			RT5677_DSP_IB_23_H_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
 			RT5677_DSP_IB_45_H_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
 			RT5677_DSP_IB_6_H_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
 			RT5677_DSP_IB_7_H_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
 			RT5677_DSP_IB_8_H_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
 			RT5677_DSP_IB_9_H_SFT, 1, 1),
 };
 static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
 	SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
 			RT5677_DSP_IB_01_L_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
 			RT5677_DSP_IB_23_L_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
 			RT5677_DSP_IB_45_L_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
 			RT5677_DSP_IB_6_L_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
 			RT5677_DSP_IB_7_L_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
 			RT5677_DSP_IB_8_L_SFT, 1, 1),
 	SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
 			RT5677_DSP_IB_9_L_SFT, 1, 1),
 };
 /* Mux */
 /* DAC1 L/R Source */ /* MX-29 [10:8] */
 static const char * const rt5677_dac1_src[] = {
 	"IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
 	"OB 01"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
 	RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
 static const struct snd_kcontrol_new rt5677_dac1_mux =
 	SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
 /* ADDA1 L/R Source */ /* MX-29 [1:0] */
 static const char * const rt5677_adda1_src[] = {
 	"STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
 	RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
 static const struct snd_kcontrol_new rt5677_adda1_mux =
 	SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
 /*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
 static const char * const rt5677_dac2l_src[] = {
 	"IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
 	"OB 2",
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
 	RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
 static const struct snd_kcontrol_new rt5677_dac2_l_mux =
 	SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
 static const char * const rt5677_dac2r_src[] = {
 	"IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
 	"OB 3", "Haptic Generator", "VAD ADC"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
 	RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
 static const struct snd_kcontrol_new rt5677_dac2_r_mux =
 	SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
 /*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
 static const char * const rt5677_dac3l_src[] = {
 	"IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
 	"SLB DAC 4", "OB 4"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
 	RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
 static const struct snd_kcontrol_new rt5677_dac3_l_mux =
 	SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
 static const char * const rt5677_dac3r_src[] = {
 	"IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
 	"SLB DAC 5", "OB 5"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
 	RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
 static const struct snd_kcontrol_new rt5677_dac3_r_mux =
 	SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
 /*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
 static const char * const rt5677_dac4l_src[] = {
 	"IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
 	"SLB DAC 6", "OB 6"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
 	RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
 static const struct snd_kcontrol_new rt5677_dac4_l_mux =
 	SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
 static const char * const rt5677_dac4r_src[] = {
 	"IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
 	"SLB DAC 7", "OB 7"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
 	RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
 static const struct snd_kcontrol_new rt5677_dac4_r_mux =
 	SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
 /* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
 static const char * const rt5677_iob_bypass_src[] = {
 	"Bypass", "Pass SRC"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
 	RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
 static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
 	SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
 	RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
 static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
 	SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
 	RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
 static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
 	SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
 	RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
 static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
 	SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
 	RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
 static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
 	SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
 /* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
 static const char * const rt5677_stereo_adc2_src[] = {
 	"DD MIX1", "DMIC", "Stereo DAC MIX"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
 	RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
 static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
 	SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
 	RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
 static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
 	SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
 	RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
 static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
 	SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
 /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
 static const char * const rt5677_dmic_src[] = {
 	"DMIC1", "DMIC2", "DMIC3", "DMIC4"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
 	RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
 static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
 	SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
 	RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
 static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
 	SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
 	RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
 static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
 	SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
 	RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
 static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
 	SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
 	RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
 static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
 	SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
 	RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
 static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
 	SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
 /* Stereo2 ADC Source */ /* MX-26 [0] */
 static const char * const rt5677_stereo2_adc_lr_src[] = {
 	"L", "LR"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
 	RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
 static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
 	SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
 /* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
 static const char * const rt5677_stereo_adc1_src[] = {
 	"DD MIX1", "ADC1/2", "Stereo DAC MIX"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
 	RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
 static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
 	SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
 	RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
 static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
 	SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
 	RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
 static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
 	SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
 /* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
 static const char * const rt5677_mono_adc2_l_src[] = {
 	"DD MIX1L", "DMIC", "MONO DAC MIXL"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
 	RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
 static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
 	SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
 /* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
 static const char * const rt5677_mono_adc1_l_src[] = {
 	"DD MIX1L", "ADC1", "MONO DAC MIXL"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
 	RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
 static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
 	SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
 /* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
 static const char * const rt5677_mono_adc2_r_src[] = {
 	"DD MIX1R", "DMIC", "MONO DAC MIXR"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
 	RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
 static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
 	SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
 /* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
 static const char * const rt5677_mono_adc1_r_src[] = {
 	"DD MIX1R", "ADC2", "MONO DAC MIXR"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
 	RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
 static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
 	SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
 /* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
 static const char * const rt5677_stereo4_adc2_src[] = {
 	"DD MIX1", "DMIC", "DD MIX2"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
 	RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
 static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
 	SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
 /* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
 static const char * const rt5677_stereo4_adc1_src[] = {
 	"DD MIX1", "ADC1/2", "DD MIX2"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
 	RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
 static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
 	SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
 /* InBound0/1 Source */ /* MX-A3 [14:12] */
 static const char * const rt5677_inbound01_src[] = {
 	"IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
 	"VAD ADC/DAC1 FS"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
 	RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
 static const struct snd_kcontrol_new rt5677_ib01_src_mux =
 	SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
 /* InBound2/3 Source */ /* MX-A3 [10:8] */
 static const char * const rt5677_inbound23_src[] = {
 	"IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
 	"DAC1 FS", "IF4 DAC"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
 	RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
 static const struct snd_kcontrol_new rt5677_ib23_src_mux =
 	SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
 /* InBound4/5 Source */ /* MX-A3 [6:4] */
 static const char * const rt5677_inbound45_src[] = {
 	"IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
 	"IF3 DAC"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
 	RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
 static const struct snd_kcontrol_new rt5677_ib45_src_mux =
 	SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
 /* InBound6 Source */ /* MX-A3 [2:0] */
 static const char * const rt5677_inbound6_src[] = {
 	"IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
 	"IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
 	RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
 static const struct snd_kcontrol_new rt5677_ib6_src_mux =
 	SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
 /* InBound7 Source */ /* MX-A4 [14:12] */
 static const char * const rt5677_inbound7_src[] = {
 	"IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
 	"IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
 	RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
 static const struct snd_kcontrol_new rt5677_ib7_src_mux =
 	SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
 /* InBound8 Source */ /* MX-A4 [10:8] */
 static const char * const rt5677_inbound8_src[] = {
 	"STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
 	"MONO ADC MIX L", "DACL1 FS"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
 	RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
 static const struct snd_kcontrol_new rt5677_ib8_src_mux =
 	SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
 /* InBound9 Source */ /* MX-A4 [6:4] */
 static const char * const rt5677_inbound9_src[] = {
 	"STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
 	"MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
 	RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
 static const struct snd_kcontrol_new rt5677_ib9_src_mux =
 	SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
 /* VAD Source */ /* MX-9F [6:4] */
 static const char * const rt5677_vad_src[] = {
 	"STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
 	"STO3 ADC MIX L"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_vad_enum, RT5677_VAD_CTRL4,
 	RT5677_VAD_SRC_SFT, rt5677_vad_src);
 static const struct snd_kcontrol_new rt5677_vad_src_mux =
 	SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
 /* Sidetone Source */ /* MX-13 [11:9] */
 static const char * const rt5677_sidetone_src[] = {
 	"DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
 	RT5677_ST_SEL_SFT, rt5677_sidetone_src);
 static const struct snd_kcontrol_new rt5677_sidetone_mux =
 	SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
 /* DAC1/2 Source */ /* MX-15 [1:0] */
 static const char * const rt5677_dac12_src[] = {
 	"STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
 	RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
 static const struct snd_kcontrol_new rt5677_dac12_mux =
 	SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
 /* DAC3 Source */ /* MX-15 [5:4] */
 static const char * const rt5677_dac3_src[] = {
 	"MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
 	RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
 static const struct snd_kcontrol_new rt5677_dac3_mux =
 	SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
 /* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
 static const char * const rt5677_pdm_src[] = {
 	"STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
 	RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
 static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
 	SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
 	RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
 static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
 	SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
 	RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
 static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
 	SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
 	RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
 static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
 	SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
 /* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */
 static const char * const rt5677_if12_adc1_src[] = {
 	"STO1 ADC MIX", "OB01", "VAD ADC"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
 	RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
 static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
 	SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
 	RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
 static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
 	SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
 	RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
 static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
 	SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
 /* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
 static const char * const rt5677_if12_adc2_src[] = {
 	"STO2 ADC MIX", "OB23"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
 	RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
 static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
 	SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
 	RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
 static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
 	SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
 	RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
 static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
 	SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
 /* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
 static const char * const rt5677_if12_adc3_src[] = {
 	"STO3 ADC MIX", "MONO ADC MIX", "OB45"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
 	RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
 static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
 	SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
 	RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
 static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
 	SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
 	RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
 static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
 	SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
 /* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
 static const char * const rt5677_if12_adc4_src[] = {
 	"STO4 ADC MIX", "OB67", "OB01"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
 	RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
 static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
 	SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
 	RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
 static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
 	SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
 	RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
 static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
 	SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
 /* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */
 static const char * const rt5677_if34_adc_src[] = {
 	"STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
 	"MONO ADC MIX", "OB01", "OB23", "VAD ADC"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if3_adc_enum, RT5677_IF3_DATA,
 	RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
 static const struct snd_kcontrol_new rt5677_if3_adc_mux =
 	SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if4_adc_enum, RT5677_IF4_DATA,
 	RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
 static const struct snd_kcontrol_new rt5677_if4_adc_mux =
 	SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
 /* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */
 static const char * const rt5677_if12_adc_swap_src[] = {
 	"L/R", "R/L", "L/L", "R/R"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1,
 	RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src);
 static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux =
 	SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1,
 	RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
 static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux =
 	SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1,
 	RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
 static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux =
 	SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1,
 	RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
 static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux =
 	SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1,
 	RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
 static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux =
 	SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1,
 	RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
 static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux =
 	SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1,
 	RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
 static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux =
 	SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1,
 	RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
 static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux =
 	SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum);
 /* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */
 static const char * const rt5677_if1_adc_tdm_swap_src[] = {
 	"1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
 	"3/1/2/4", "3/4/1/2"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2,
 	RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src);
 static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux =
 	SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum);
 /* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */
 static const char * const rt5677_if2_adc_tdm_swap_src[] = {
 	"1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
 	"2/3/1/4", "3/4/1/2"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2,
 	RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src);
 static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux =
 	SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum);
 /* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0]
 					MX-3F[14:12][10:8][6:4][2:0]
 					MX-43[14:12][10:8][6:4][2:0]
 					MX-44[14:12][10:8][6:4][2:0] */
 static const char * const rt5677_if12_dac_tdm_sel_src[] = {
 	"Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
 };
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4,
 	RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
 static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux =
 	SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4,
 	RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
 static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux =
 	SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4,
 	RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
 static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux =
 	SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4,
 	RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
 static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux =
 	SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5,
 	RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
 static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux =
 	SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5,
 	RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
 static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux =
 	SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5,
 	RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
 static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux =
 	SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5,
 	RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
 static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux =
 	SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4,
 	RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
 static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux =
 	SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4,
 	RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
 static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux =
 	SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4,
 	RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
 static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux =
 	SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4,
 	RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
 static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux =
 	SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5,
 	RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
 static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux =
 	SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5,
 	RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
 static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux =
 	SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5,
 	RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
 static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux =
 	SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum);
 static SOC_ENUM_SINGLE_DECL(
 	rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5,
 	RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
 static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux =
 	SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum);
 static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
 	struct snd_kcontrol *kcontrol, int event)
 {
 	struct snd_soc_codec *codec = w->codec;
 	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
 	switch (event) {
 	case SND_SOC_DAPM_POST_PMU:
 		regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
 			RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
 		break;
 	case SND_SOC_DAPM_PRE_PMD:
 		regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
 			RT5677_PWR_BST1_P, 0);
 		break;
 	default:
 		return 0;
 	}
 	return 0;
 }
 static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
 	struct snd_kcontrol *kcontrol, int event)
 {
 	struct snd_soc_codec *codec = w->codec;
 	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
 	switch (event) {
 	case SND_SOC_DAPM_POST_PMU:
 		regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
 			RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
 		break;
 	case SND_SOC_DAPM_PRE_PMD:
 		regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
 			RT5677_PWR_BST2_P, 0);
 		break;
 	default:
 		return 0;
 	}
 	return 0;
 }
 static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
 	struct snd_kcontrol *kcontrol, int event)
 {
 	struct snd_soc_codec *codec = w->codec;
 	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
 	switch (event) {
 	case SND_SOC_DAPM_POST_PMU:
 		regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
 		regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
 		break;
 	default:
 		return 0;
 	}
 	return 0;
 }
 static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
 	struct snd_kcontrol *kcontrol, int event)
 {
 	struct snd_soc_codec *codec = w->codec;
 	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
 	switch (event) {
 	case SND_SOC_DAPM_POST_PMU:
 		regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
 		regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
 		break;
 	default:
 		return 0;
 	}
 	return 0;
 }
 static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
 	struct snd_kcontrol *kcontrol, int event)
 {
 	struct snd_soc_codec *codec = w->codec;
 	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
 	switch (event) {
 	case SND_SOC_DAPM_POST_PMU:
 		regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
 			RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
 			RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
 			RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
 		break;
 	case SND_SOC_DAPM_PRE_PMD:
 		regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
 			RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
 			RT5677_PWR_CLK_MB, 0);
 		break;
 	default:
 		return 0;
 	}
 	return 0;
 }
 static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w,
 	struct snd_kcontrol *kcontrol, int event)
 {
 	struct snd_soc_codec *codec = w->codec;
 	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
 	unsigned int value;
 	switch (event) {
 	case SND_SOC_DAPM_PRE_PMU:
 		regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value);
 		if (value & RT5677_IF1_ADC_CTRL_MASK)
 			regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1,
 				RT5677_IF1_ADC_MODE_MASK,
 				RT5677_IF1_ADC_MODE_TDM);
 		break;
 	default:
 		return 0;
 	}
 	return 0;
 }
 static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w,
 	struct snd_kcontrol *kcontrol, int event)
 {
 	struct snd_soc_codec *codec = w->codec;
 	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
 	unsigned int value;
 	switch (event) {
 	case SND_SOC_DAPM_PRE_PMU:
 		regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value);
 		if (value & RT5677_IF2_ADC_CTRL_MASK)
 			regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1,
 				RT5677_IF2_ADC_MODE_MASK,
 				RT5677_IF2_ADC_MODE_TDM);
 		break;
 	default:
 		return 0;
 	}
 	return 0;
 }
 static int rt5677_vref_event(struct snd_soc_dapm_widget *w,
 	struct snd_kcontrol *kcontrol, int event)
 {
 	struct snd_soc_codec *codec = w->codec;
 	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
 	switch (event) {
 	case SND_SOC_DAPM_POST_PMU:
 		if (codec->dapm.bias_level != SND_SOC_BIAS_ON &&
 			!rt5677->is_vref_slow) {
 			mdelay(20);
 			regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
 				RT5677_PWR_FV1 | RT5677_PWR_FV2,
 				RT5677_PWR_FV1 | RT5677_PWR_FV2);
 			rt5677->is_vref_slow = true;
 		}
 		break;
 	default:
 		return 0;
 	}
 	return 0;
 }
 static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
 	SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
 		0, rt5677_set_pll1_event, SND_SOC_DAPM_POST_PMU),
 	SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
 		0, rt5677_set_pll2_event, SND_SOC_DAPM_POST_PMU),
 	/* Input Side */
 	/* micbias */
 	SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
 		0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
 		SND_SOC_DAPM_POST_PMU),
 	/* Input Lines */
 	SND_SOC_DAPM_INPUT("DMIC L1"),
 	SND_SOC_DAPM_INPUT("DMIC R1"),
 	SND_SOC_DAPM_INPUT("DMIC L2"),
 	SND_SOC_DAPM_INPUT("DMIC R2"),
 	SND_SOC_DAPM_INPUT("DMIC L3"),
 	SND_SOC_DAPM_INPUT("DMIC R3"),
 	SND_SOC_DAPM_INPUT("DMIC L4"),
 	SND_SOC_DAPM_INPUT("DMIC R4"),
 	SND_SOC_DAPM_INPUT("IN1P"),
 	SND_SOC_DAPM_INPUT("IN1N"),
 	SND_SOC_DAPM_INPUT("IN2P"),
 	SND_SOC_DAPM_INPUT("IN2N"),
 	SND_SOC_DAPM_INPUT("Haptic Generator"),
 	SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1,
 		RT5677_DMIC_1_EN_SFT, 0, NULL, 0),
 	SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1,
 		RT5677_DMIC_2_EN_SFT, 0, NULL, 0),
 	SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1,
 		RT5677_DMIC_3_EN_SFT, 0, NULL, 0),
 	SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2,
 		RT5677_DMIC_4_EN_SFT, 0, NULL, 0),
 	SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
 		set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
 	/* Boost */
 	SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
 		RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
 		SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
 	SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
 		RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
 		SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
 	/* ADCs */
 	SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
 		0, 0),
 	SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
 		0, 0),
 	SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
 		RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
 	SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
 		RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
 	SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
 		RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
 	SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
 		RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
 	/* ADC Mux */
 	SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
 				&rt5677_sto1_dmic_mux),
 	SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
 				&rt5677_sto1_adc1_mux),
 	SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
 				&rt5677_sto1_adc2_mux),
 	SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
 				&rt5677_sto2_dmic_mux),
 	SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
 				&rt5677_sto2_adc1_mux),
 	SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
 				&rt5677_sto2_adc2_mux),
 	SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
 				&rt5677_sto2_adc_lr_mux),
 	SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
 				&rt5677_sto3_dmic_mux),
 	SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
 				&rt5677_sto3_adc1_mux),
 	SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
 				&rt5677_sto3_adc2_mux),
 	SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
 				&rt5677_sto4_dmic_mux),
 	SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
 				&rt5677_sto4_adc1_mux),
 	SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
 				&rt5677_sto4_adc2_mux),
 	SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
 				&rt5677_mono_dmic_l_mux),
 	SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
 				&rt5677_mono_dmic_r_mux),
 	SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
 				&rt5677_mono_adc2_l_mux),
 	SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
 				&rt5677_mono_adc1_l_mux),
 	SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
 				&rt5677_mono_adc1_r_mux),
 	SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
 				&rt5677_mono_adc2_r_mux),
 	/* ADC Mixer */
 	SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
 		RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
 	SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
 		RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
 	SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
 		RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
 	SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
 		RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
 	SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
 		rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
 	SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
 		rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
 	SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
 		rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
 	SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
 		rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
 	SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
 		rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
 	SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
 		rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
 	SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
 		rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
 	SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
 		rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
 	SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
 		RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
 	SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
 		rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
 	SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
 		RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
 	SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
 		rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
 	/* ADC PGA */
 	SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
 	/* DSP */
 	SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_ib9_src_mux),
 	SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_ib8_src_mux),
 	SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_ib7_src_mux),
 	SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_ib6_src_mux),
 	SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_ib45_src_mux),
 	SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_ib23_src_mux),
 	SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_ib01_src_mux),
 	SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_ib45_bypass_src_mux),
 	SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_ib23_bypass_src_mux),
 	SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_ib01_bypass_src_mux),
 	SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_ob23_bypass_src_mux),
 	SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_ob01_bypass_src_mux),
 	SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
 	/* Digital Interface */
 	SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
 		RT5677_PWR_I2S1_BIT, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
 		RT5677_PWR_I2S2_BIT, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
 		RT5677_PWR_I2S3_BIT, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
 		RT5677_PWR_I2S4_BIT, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
 		RT5677_PWR_SLB_BIT, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
 	/* Digital Interface Select */
 	SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if1_adc1_mux),
 	SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if1_adc2_mux),
 	SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if1_adc3_mux),
 	SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if1_adc4_mux),
 	SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if1_adc1_swap_mux),
 	SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if1_adc2_swap_mux),
 	SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if1_adc3_swap_mux),
 	SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if1_adc4_swap_mux),
 	SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event,
 			SND_SOC_DAPM_PRE_PMU),
 	SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if2_adc1_mux),
 	SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if2_adc2_mux),
 	SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if2_adc3_mux),
 	SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if2_adc4_mux),
 	SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if2_adc1_swap_mux),
 	SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if2_adc2_swap_mux),
 	SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if2_adc3_swap_mux),
 	SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if2_adc4_swap_mux),
 	SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event,
 			SND_SOC_DAPM_PRE_PMU),
 	SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if3_adc_mux),
 	SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if4_adc_mux),
 	SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_slb_adc1_mux),
 	SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_slb_adc2_mux),
 	SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_slb_adc3_mux),
 	SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_slb_adc4_mux),
 	SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if1_dac0_tdm_sel_mux),
 	SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if1_dac1_tdm_sel_mux),
 	SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if1_dac2_tdm_sel_mux),
 	SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if1_dac3_tdm_sel_mux),
 	SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if1_dac4_tdm_sel_mux),
 	SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if1_dac5_tdm_sel_mux),
 	SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if1_dac6_tdm_sel_mux),
 	SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if1_dac7_tdm_sel_mux),
 	SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if2_dac0_tdm_sel_mux),
 	SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if2_dac1_tdm_sel_mux),
 	SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if2_dac2_tdm_sel_mux),
 	SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if2_dac3_tdm_sel_mux),
 	SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if2_dac4_tdm_sel_mux),
 	SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if2_dac5_tdm_sel_mux),
 	SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if2_dac6_tdm_sel_mux),
 	SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_if2_dac7_tdm_sel_mux),
 	/* Audio Interface */
 	SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
 	SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
 	SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
 	SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
 	SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
 	SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
 	SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
 	SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
 	SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
 	SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
 	/* Sidetone Mux */
 	SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_sidetone_mux),
 	SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL,
 		RT5677_ST_EN_SFT, 0, NULL, 0),
 	/* VAD Mux*/
 	SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_vad_src_mux),
 	/* Tensilica DSP */
 	SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
 		rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
 	SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
 		rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
 	SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
 		rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
 	SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
 		rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
 	SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
 		rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
 	SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
 		rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
 	/* Output Side */
 	/* DAC mixer before sound effect */
 	SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
 		rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
 	SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
 		rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
 	SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
 	/* DAC Mux */
 	SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
 				&rt5677_dac1_mux),
 	SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
 				&rt5677_adda1_mux),
 	SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
 				&rt5677_dac12_mux),
 	SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
 				&rt5677_dac3_mux),
 	/* DAC2 channel Mux */
 	SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
 				&rt5677_dac2_l_mux),
 	SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
 				&rt5677_dac2_r_mux),
 	/* DAC3 channel Mux */
 	SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_dac3_l_mux),
 	SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_dac3_r_mux),
 	/* DAC4 channel Mux */
 	SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_dac4_l_mux),
 	SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
 			&rt5677_dac4_r_mux),
 	/* DAC Mixer */
 	SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
 		RT5677_PWR_DAC_S1F_BIT, 0, NULL, 0),
 	SND_SOC_DAPM_SUPPLY("dac mono left filter", RT5677_PWR_DIG2,
 		RT5677_PWR_DAC_M2F_L_BIT, 0, NULL, 0),
 	SND_SOC_DAPM_SUPPLY("dac mono right filter", RT5677_PWR_DIG2,
 		RT5677_PWR_DAC_M2F_R_BIT, 0, NULL, 0),
 	SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
 		rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
 	SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
 		rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
 	SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
 		rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
 	SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
 		rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
 	SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
 		rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
 	SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
 		rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
 	SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
 		rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
 	SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
 		rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
 	SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
 	SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
 	/* DACs */
 	SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
 		RT5677_PWR_DAC1_BIT, 0),
 	SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
 		RT5677_PWR_DAC2_BIT, 0),
 	SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
 		RT5677_PWR_DAC3_BIT, 0),
 	/* PDM */
 	SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
 		RT5677_PWR_PDM1_BIT, 0, NULL, 0),
 	SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
 		RT5677_PWR_PDM2_BIT, 0, NULL, 0),
 	SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
 		1, &rt5677_pdm1_l_mux),
 	SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
 		1, &rt5677_pdm1_r_mux),
 	SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
 		1, &rt5677_pdm2_l_mux),
 	SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
 		1, &rt5677_pdm2_r_mux),
 	SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
 		0, NULL, 0),
 	SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
 		0, NULL, 0),
 	SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
 		0, NULL, 0),
 	SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0,
 		rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
 	SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0,
 		rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
 	SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0,
 		rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
 	/* Output Lines */
 	SND_SOC_DAPM_OUTPUT("LOUT1"),
 	SND_SOC_DAPM_OUTPUT("LOUT2"),
 	SND_SOC_DAPM_OUTPUT("LOUT3"),
 	SND_SOC_DAPM_OUTPUT("PDM1L"),
 	SND_SOC_DAPM_OUTPUT("PDM1R"),
 	SND_SOC_DAPM_OUTPUT("PDM2L"),
 	SND_SOC_DAPM_OUTPUT("PDM2R"),
 	SND_SOC_DAPM_POST("vref", rt5677_vref_event),
 };
 static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
 	{ "DMIC1", NULL, "DMIC L1" },
 	{ "DMIC1", NULL, "DMIC R1" },
 	{ "DMIC2", NULL, "DMIC L2" },
 	{ "DMIC2", NULL, "DMIC R2" },
 	{ "DMIC3", NULL, "DMIC L3" },
 	{ "DMIC3", NULL, "DMIC R3" },
 	{ "DMIC4", NULL, "DMIC L4" },
 	{ "DMIC4", NULL, "DMIC R4" },
 	{ "DMIC L1", NULL, "DMIC CLK" },
 	{ "DMIC R1", NULL, "DMIC CLK" },
 	{ "DMIC L2", NULL, "DMIC CLK" },
 	{ "DMIC R2", NULL, "DMIC CLK" },
 	{ "DMIC L3", NULL, "DMIC CLK" },
 	{ "DMIC R3", NULL, "DMIC CLK" },
 	{ "DMIC L4", NULL, "DMIC CLK" },
 	{ "DMIC R4", NULL, "DMIC CLK" },
 	{ "DMIC L1", NULL, "DMIC1 power" },
 	{ "DMIC R1", NULL, "DMIC1 power" },
 	{ "DMIC L3", NULL, "DMIC3 power" },
 	{ "DMIC R3", NULL, "DMIC3 power" },
 	{ "DMIC L4", NULL, "DMIC4 power" },
 	{ "DMIC R4", NULL, "DMIC4 power" },
 	{ "BST1", NULL, "IN1P" },
 	{ "BST1", NULL, "IN1N" },
 	{ "BST2", NULL, "IN2P" },
 	{ "BST2", NULL, "IN2N" },
 	{ "IN1P", NULL, "MICBIAS1" },
 	{ "IN1N", NULL, "MICBIAS1" },
 	{ "IN2P", NULL, "MICBIAS1" },
 	{ "IN2N", NULL, "MICBIAS1" },
 	{ "ADC 1", NULL, "BST1" },
 	{ "ADC 1", NULL, "ADC 1 power" },
 	{ "ADC 1", NULL, "ADC1 clock" },
 	{ "ADC 2", NULL, "BST2" },
 	{ "ADC 2", NULL, "ADC 2 power" },
 	{ "ADC 2", NULL, "ADC2 clock" },
 	{ "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
 	{ "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
 	{ "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
 	{ "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
 	{ "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
 	{ "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
 	{ "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
 	{ "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
 	{ "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
 	{ "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
 	{ "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
 	{ "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
 	{ "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
 	{ "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
 	{ "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
 	{ "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
 	{ "Mono DMIC L Mux", "DMIC1", "DMIC1" },
 	{ "Mono DMIC L Mux", "DMIC2", "DMIC2" },
 	{ "Mono DMIC L Mux", "DMIC3", "DMIC3" },
 	{ "Mono DMIC L Mux", "DMIC4", "DMIC4" },
 	{ "Mono DMIC R Mux", "DMIC1", "DMIC1" },
 	{ "Mono DMIC R Mux", "DMIC2", "DMIC2" },
 	{ "Mono DMIC R Mux", "DMIC3", "DMIC3" },
 	{ "Mono DMIC R Mux", "DMIC4", "DMIC4" },
 	{ "ADC 1_2", NULL, "ADC 1" },
 	{ "ADC 1_2", NULL, "ADC 2" },
 	{ "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
 	{ "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
 	{ "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
 	{ "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
 	{ "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
 	{ "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
 	{ "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
 	{ "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
 	{ "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
 	{ "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
 	{ "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
 	{ "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
 	{ "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
 	{ "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
 	{ "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
 	{ "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
 	{ "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
 	{ "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
 	{ "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
 	{ "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
 	{ "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
 	{ "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
 	{ "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
 	{ "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
 	{ "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
 	{ "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
 	{ "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
 	{ "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
 	{ "Mono ADC1 L Mux", "ADC1", "ADC 1" },
 	{ "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
 	{ "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
 	{ "Mono ADC1 R Mux", "ADC2", "ADC 2" },
 	{ "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
 	{ "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
 	{ "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
 	{ "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
 	{ "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
 	{ "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
 	{ "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
 	{ "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
 	{ "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
 	{ "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
 	{ "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
 	{ "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
 	{ "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
 	{ "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
 	{ "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
 	{ "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
 	{ "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
 	{ "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
 	{ "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
 	{ "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
 	{ "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
 	{ "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
 	{ "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
 	{ "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
 	{ "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
 	{ "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
 	{ "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
 	{ "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
 	{ "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
 	{ "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
 	{ "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
 	{ "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
 	{ "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
 	{ "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
 	{ "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
 	{ "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
 	{ "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
 	{ "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
 	{ "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
 	{ "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
 	{ "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
 	{ "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
 	{ "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
 	{ "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
 	{ "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
 	{ "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
 	{ "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
 	{ "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
 	{ "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
 	{ "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
 	{ "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
 	{ "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
 	{ "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
 	{ "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
 	{ "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
 	{ "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
 	{ "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
 	{ "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
 	{ "Mono ADC MIXL", NULL, "adc mono left filter" },
 	{ "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
 	{ "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
 	{ "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
 	{ "Mono ADC MIXR", NULL, "adc mono right filter" },
 	{ "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
 	{ "Mono ADC MIX", NULL, "Mono ADC MIXL" },
 	{ "Mono ADC MIX", NULL, "Mono ADC MIXR" },
 	{ "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
 	{ "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
 	{ "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
 	{ "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
 	{ "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
 	{ "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
 	{ "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
 	{ "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
 	{ "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
 	{ "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
 	{ "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
 	{ "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
 	{ "IF1 ADC3 Mux", "OB45", "OB45" },
 	{ "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
 	{ "IF1 ADC4 Mux", "OB67", "OB67" },
 	{ "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
 	{ "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" },
 	{ "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" },
 	{ "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" },
 	{ "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" },
 	{ "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" },
 	{ "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" },
 	{ "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" },
 	{ "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" },
 	{ "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" },
 	{ "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" },
 	{ "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" },
 	{ "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" },
 	{ "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" },
 	{ "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" },
 	{ "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" },
 	{ "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" },
 	{ "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" },
 	{ "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" },
 	{ "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" },
 	{ "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" },
 	{ "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" },
 	{ "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" },
 	{ "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" },
 	{ "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" },
 	{ "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" },
 	{ "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" },
 	{ "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" },
 	{ "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" },
 	{ "AIF1TX", NULL, "I2S1" },
 	{ "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" },
 	{ "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
 	{ "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
 	{ "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
 	{ "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
 	{ "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
 	{ "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
 	{ "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
 	{ "IF2 ADC3 Mux", "OB45", "OB45" },
 	{ "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
 	{ "IF2 ADC4 Mux", "OB67", "OB67" },
 	{ "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
 	{ "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" },
 	{ "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" },
 	{ "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" },
 	{ "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" },
 	{ "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" },
 	{ "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" },
 	{ "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" },
 	{ "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" },
 	{ "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" },
 	{ "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" },
 	{ "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" },
 	{ "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" },
 	{ "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" },
 	{ "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" },
 	{ "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" },
 	{ "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" },
 	{ "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" },
 	{ "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" },
 	{ "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" },
 	{ "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" },
 	{ "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" },
 	{ "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" },
 	{ "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" },
 	{ "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" },
 	{ "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" },
 	{ "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" },
 	{ "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" },
 	{ "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" },
 	{ "AIF2TX", NULL, "I2S2" },
 	{ "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" },
 	{ "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
 	{ "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
 	{ "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
 	{ "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
 	{ "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
 	{ "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
 	{ "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
 	{ "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
 	{ "AIF3TX", NULL, "I2S3" },
 	{ "AIF3TX", NULL, "IF3 ADC Mux" },
 	{ "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
 	{ "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
 	{ "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
 	{ "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
 	{ "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
 	{ "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
 	{ "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
 	{ "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
 	{ "AIF4TX", NULL, "I2S4" },
 	{ "AIF4TX", NULL, "IF4 ADC Mux" },
 	{ "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
 	{ "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
 	{ "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
 	{ "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
 	{ "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
 	{ "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
 	{ "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
 	{ "SLB ADC3 Mux", "OB45", "OB45" },
 	{ "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
 	{ "SLB ADC4 Mux", "OB67", "OB67" },
 	{ "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
 	{ "SLBTX", NULL, "SLB" },
 	{ "SLBTX", NULL, "SLB ADC1 Mux" },
 	{ "SLBTX", NULL, "SLB ADC2 Mux" },
 	{ "SLBTX", NULL, "SLB ADC3 Mux" },
 	{ "SLBTX", NULL, "SLB ADC4 Mux" },
 	{ "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
 	{ "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
 	{ "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
 	{ "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
 	{ "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
 	{ "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
 	{ "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
 	{ "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
 	{ "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
 	{ "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
 	{ "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
 	{ "IB23 Mux", "DAC1 FS", "DAC1 FS" },
 	{ "IB23 Mux", "IF4 DAC", "IF4 DAC" },
 	{ "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
 	{ "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
 	{ "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
 	{ "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
 	{ "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
 	{ "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
 	{ "IB45 Mux", "IF3 DAC", "IF3 DAC" },
 	{ "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
 	{ "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
 	{ "IB6 Mux", "IF1 DAC 6", "IF1 DAC6" },
 	{ "IB6 Mux", "IF2 DAC 6", "IF2 DAC6" },
 	{ "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
 	{ "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
 	{ "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
 	{ "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
 	{ "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
 	{ "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
 	{ "IB7 Mux", "IF1 DAC 7", "IF1 DAC7" },
 	{ "IB7 Mux", "IF2 DAC 7", "IF2 DAC7" },
 	{ "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
 	{ "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
 	{ "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
 	{ "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
 	{ "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
 	{ "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
 	{ "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
 	{ "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
 	{ "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
 	{ "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
 	{ "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
 	{ "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
 	{ "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
 	{ "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
 	{ "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
 	{ "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
 	{ "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
 	{ "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
 	{ "IB9 Mux", "DAC1 FS", "DAC1 FS" },
 	{ "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
 	{ "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
 	{ "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
 	{ "OB01 MIX", "IB6 Switch", "IB6 Mux" },
 	{ "OB01 MIX", "IB7 Switch", "IB7 Mux" },
 	{ "OB01 MIX", "IB8 Switch", "IB8 Mux" },
 	{ "OB01 MIX", "IB9 Switch", "IB9 Mux" },
 	{ "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
 	{ "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
 	{ "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
 	{ "OB23 MIX", "IB6 Switch", "IB6 Mux" },
 	{ "OB23 MIX", "IB7 Switch", "IB7 Mux" },
 	{ "OB23 MIX", "IB8 Switch", "IB8 Mux" },
 	{ "OB23 MIX", "IB9 Switch", "IB9 Mux" },
 	{ "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
 	{ "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
 	{ "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
 	{ "OB4 MIX", "IB6 Switch", "IB6 Mux" },
 	{ "OB4 MIX", "IB7 Switch", "IB7 Mux" },
 	{ "OB4 MIX", "IB8 Switch", "IB8 Mux" },
 	{ "OB4 MIX", "IB9 Switch", "IB9 Mux" },
 	{ "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
 	{ "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
 	{ "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
 	{ "OB5 MIX", "IB6 Switch", "IB6 Mux" },
 	{ "OB5 MIX", "IB7 Switch", "IB7 Mux" },
 	{ "OB5 MIX", "IB8 Switch", "IB8 Mux" },
 	{ "OB5 MIX", "IB9 Switch", "IB9 Mux" },
 	{ "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
 	{ "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
 	{ "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
 	{ "OB6 MIX", "IB6 Switch", "IB6 Mux" },
 	{ "OB6 MIX", "IB7 Switch", "IB7 Mux" },
 	{ "OB6 MIX", "IB8 Switch", "IB8 Mux" },
 	{ "OB6 MIX", "IB9 Switch", "IB9 Mux" },
 	{ "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
 	{ "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
 	{ "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
 	{ "OB7 MIX", "IB6 Switch", "IB6 Mux" },
 	{ "OB7 MIX", "IB7 Switch", "IB7 Mux" },
 	{ "OB7 MIX", "IB8 Switch", "IB8 Mux" },
 	{ "OB7 MIX", "IB9 Switch", "IB9 Mux" },
 	{ "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
 	{ "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
 	{ "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
 	{ "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
 	{ "OutBound2", NULL, "OB23 Bypass Mux" },
 	{ "OutBound3", NULL, "OB23 Bypass Mux" },
 	{ "OutBound4", NULL, "OB4 MIX" },
 	{ "OutBound5", NULL, "OB5 MIX" },
 	{ "OutBound6", NULL, "OB6 MIX" },
 	{ "OutBound7", NULL, "OB7 MIX" },
 	{ "OB45", NULL, "OutBound4" },
 	{ "OB45", NULL, "OutBound5" },
 	{ "OB67", NULL, "OutBound6" },
 	{ "OB67", NULL, "OutBound7" },
 	{ "IF1 DAC0", NULL, "AIF1RX" },
 	{ "IF1 DAC1", NULL, "AIF1RX" },
 	{ "IF1 DAC2", NULL, "AIF1RX" },
 	{ "IF1 DAC3", NULL, "AIF1RX" },
 	{ "IF1 DAC4", NULL, "AIF1RX" },
 	{ "IF1 DAC5", NULL, "AIF1RX" },
 	{ "IF1 DAC6", NULL, "AIF1RX" },
 	{ "IF1 DAC7", NULL, "AIF1RX" },
 	{ "IF1 DAC0", NULL, "I2S1" },
 	{ "IF1 DAC1", NULL, "I2S1" },
 	{ "IF1 DAC2", NULL, "I2S1" },
 	{ "IF1 DAC3", NULL, "I2S1" },
 	{ "IF1 DAC4", NULL, "I2S1" },
 	{ "IF1 DAC5", NULL, "I2S1" },
 	{ "IF1 DAC6", NULL, "I2S1" },
 	{ "IF1 DAC7", NULL, "I2S1" },
 	{ "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" },
 	{ "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" },
 	{ "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" },
 	{ "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" },
 	{ "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" },
 	{ "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" },
 	{ "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" },
 	{ "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" },
 	{ "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" },
 	{ "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" },
 	{ "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" },
 	{ "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" },
 	{ "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" },
 	{ "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" },
 	{ "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" },
 	{ "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" },
 	{ "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" },
 	{ "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" },
 	{ "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" },
 	{ "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" },
 	{ "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" },
 	{ "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" },
 	{ "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" },
 	{ "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" },
 	{ "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" },
 	{ "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" },
 	{ "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" },
 	{ "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" },
 	{ "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" },
 	{ "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" },
 	{ "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" },
 	{ "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" },
 	{ "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" },
 	{ "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" },
 	{ "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" },
 	{ "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" },
 	{ "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" },
 	{ "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" },
 	{ "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" },
 	{ "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" },
 	{ "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" },
 	{ "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" },
 	{ "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" },
 	{ "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" },
 	{ "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" },
 	{ "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" },
 	{ "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" },
 	{ "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" },
 	{ "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" },
 	{ "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" },
 	{ "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" },
 	{ "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" },
 	{ "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" },
 	{ "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" },
 	{ "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" },
 	{ "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" },
 	{ "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" },
 	{ "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" },
 	{ "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" },
 	{ "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" },
 	{ "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" },
 	{ "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" },
 	{ "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" },
 	{ "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" },
 	{ "IF1 DAC01", NULL, "IF1 DAC0 Mux" },
 	{ "IF1 DAC01", NULL, "IF1 DAC1 Mux" },
 	{ "IF1 DAC23", NULL, "IF1 DAC2 Mux" },
 	{ "IF1 DAC23", NULL, "IF1 DAC3 Mux" },
 	{ "IF1 DAC45", NULL, "IF1 DAC4 Mux" },
 	{ "IF1 DAC45", NULL, "IF1 DAC5 Mux" },
 	{ "IF1 DAC67", NULL, "IF1 DAC6 Mux" },
 	{ "IF1 DAC67", NULL, "IF1 DAC7 Mux" },
 	{ "IF2 DAC0", NULL, "AIF2RX" },
 	{ "IF2 DAC1", NULL, "AIF2RX" },
 	{ "IF2 DAC2", NULL, "AIF2RX" },
 	{ "IF2 DAC3", NULL, "AIF2RX" },
 	{ "IF2 DAC4", NULL, "AIF2RX" },
 	{ "IF2 DAC5", NULL, "AIF2RX" },
 	{ "IF2 DAC6", NULL, "AIF2RX" },
 	{ "IF2 DAC7", NULL, "AIF2RX" },
 	{ "IF2 DAC0", NULL, "I2S2" },
 	{ "IF2 DAC1", NULL, "I2S2" },
 	{ "IF2 DAC2", NULL, "I2S2" },
 	{ "IF2 DAC3", NULL, "I2S2" },
 	{ "IF2 DAC4", NULL, "I2S2" },
 	{ "IF2 DAC5", NULL, "I2S2" },
 	{ "IF2 DAC6", NULL, "I2S2" },
 	{ "IF2 DAC7", NULL, "I2S2" },
 	{ "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" },
 	{ "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" },
 	{ "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" },
 	{ "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" },
 	{ "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" },
 	{ "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" },
 	{ "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" },
 	{ "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" },
 	{ "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" },
 	{ "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" },
 	{ "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" },
 	{ "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" },
 	{ "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" },
 	{ "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" },
 	{ "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" },
 	{ "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" },
 	{ "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" },
 	{ "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" },
 	{ "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" },
 	{ "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" },
 	{ "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" },
 	{ "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" },
 	{ "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" },
 	{ "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" },
 	{ "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" },
 	{ "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" },
 	{ "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" },
 	{ "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" },
 	{ "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" },
 	{ "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" },
 	{ "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" },
 	{ "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" },
 	{ "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" },
 	{ "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" },
 	{ "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" },
 	{ "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" },
 	{ "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" },
 	{ "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" },
 	{ "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" },
 	{ "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" },
 	{ "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" },
 	{ "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" },
 	{ "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" },
 	{ "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" },
 	{ "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" },
 	{ "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" },
 	{ "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" },
 	{ "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" },
 	{ "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" },
 	{ "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" },
 	{ "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" },
 	{ "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" },
 	{ "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" },
 	{ "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" },
 	{ "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" },
 	{ "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" },
 	{ "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" },
 	{ "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" },
 	{ "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" },
 	{ "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" },
 	{ "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" },
 	{ "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" },
 	{ "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" },
 	{ "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" },
 	{ "IF2 DAC01", NULL, "IF2 DAC0 Mux" },
 	{ "IF2 DAC01", NULL, "IF2 DAC1 Mux" },
 	{ "IF2 DAC23", NULL, "IF2 DAC2 Mux" },
 	{ "IF2 DAC23", NULL, "IF2 DAC3 Mux" },
 	{ "IF2 DAC45", NULL, "IF2 DAC4 Mux" },
 	{ "IF2 DAC45", NULL, "IF2 DAC5 Mux" },
 	{ "IF2 DAC67", NULL, "IF2 DAC6 Mux" },
 	{ "IF2 DAC67", NULL, "IF2 DAC7 Mux" },
 	{ "IF3 DAC", NULL, "AIF3RX" },
 	{ "IF3 DAC", NULL, "I2S3" },
 	{ "IF4 DAC", NULL, "AIF4RX" },
 	{ "IF4 DAC", NULL, "I2S4" },
 	{ "IF3 DAC L", NULL, "IF3 DAC" },
 	{ "IF3 DAC R", NULL, "IF3 DAC" },
 	{ "IF4 DAC L", NULL, "IF4 DAC" },
 	{ "IF4 DAC R", NULL, "IF4 DAC" },
 	{ "SLB DAC0", NULL, "SLBRX" },
 	{ "SLB DAC1", NULL, "SLBRX" },
 	{ "SLB DAC2", NULL, "SLBRX" },
 	{ "SLB DAC3", NULL, "SLBRX" },
 	{ "SLB DAC4", NULL, "SLBRX" },
 	{ "SLB DAC5", NULL, "SLBRX" },
 	{ "SLB DAC6", NULL, "SLBRX" },
 	{ "SLB DAC7", NULL, "SLBRX" },
 	{ "SLB DAC0", NULL, "SLB" },
 	{ "SLB DAC1", NULL, "SLB" },
 	{ "SLB DAC2", NULL, "SLB" },
 	{ "SLB DAC3", NULL, "SLB" },
 	{ "SLB DAC4", NULL, "SLB" },
 	{ "SLB DAC5", NULL, "SLB" },
 	{ "SLB DAC6", NULL, "SLB" },
 	{ "SLB DAC7", NULL, "SLB" },
 	{ "SLB DAC01", NULL, "SLB DAC0" },
 	{ "SLB DAC01", NULL, "SLB DAC1" },
 	{ "SLB DAC23", NULL, "SLB DAC2" },
 	{ "SLB DAC23", NULL, "SLB DAC3" },
 	{ "SLB DAC45", NULL, "SLB DAC4" },
 	{ "SLB DAC45", NULL, "SLB DAC5" },
 	{ "SLB DAC67", NULL, "SLB DAC6" },
 	{ "SLB DAC67", NULL, "SLB DAC7" },
 	{ "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
 	{ "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
 	{ "ADDA1 Mux", "OB 67", "OB67" },
 	{ "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
 	{ "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
 	{ "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
 	{ "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
 	{ "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
 	{ "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
 	{ "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
 	{ "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
 	{ "DAC1 MIXL", NULL, "dac stereo1 filter" },
 	{ "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
 	{ "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
 	{ "DAC1 MIXR", NULL, "dac stereo1 filter" },
 	{ "DAC1 FS", NULL, "DAC1 MIXL" },
 	{ "DAC1 FS", NULL, "DAC1 MIXR" },
 	{ "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2" },
 	{ "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2" },
 	{ "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
 	{ "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
 	{ "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
 	{ "DAC2 L Mux", "OB 2", "OutBound2" },
 	{ "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3" },
 	{ "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3" },
 	{ "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
 	{ "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
 	{ "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
 	{ "DAC2 R Mux", "OB 3", "OutBound3" },
 	{ "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
 	{ "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
 	{ "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4" },
 	{ "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4" },
 	{ "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
 	{ "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
 	{ "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
 	{ "DAC3 L Mux", "OB 4", "OutBound4" },
 	{ "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC4" },
 	{ "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC4" },
 	{ "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
 	{ "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
 	{ "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
 	{ "DAC3 R Mux", "OB 5", "OutBound5" },
 	{ "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6" },
 	{ "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6" },
 	{ "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
 	{ "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
 	{ "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
 	{ "DAC4 L Mux", "OB 6", "OutBound6" },
 	{ "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7" },
 	{ "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7" },
 	{ "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
 	{ "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
 	{ "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
 	{ "DAC4 R Mux", "OB 7", "OutBound7" },
 	{ "Sidetone Mux", "DMIC1 L", "DMIC L1" },
 	{ "Sidetone Mux", "DMIC2 L", "DMIC L2" },
 	{ "Sidetone Mux", "DMIC3 L", "DMIC L3" },
 	{ "Sidetone Mux", "DMIC4 L", "DMIC L4" },
 	{ "Sidetone Mux", "ADC1", "ADC 1" },
 	{ "Sidetone Mux", "ADC2", "ADC 2" },
 	{ "Sidetone Mux", NULL, "Sidetone Power" },
 	{ "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
 	{ "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
 	{ "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
 	{ "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
 	{ "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
 	{ "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
 	{ "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
 	{ "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
 	{ "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
 	{ "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
 	{ "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
 	{ "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
 	{ "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
 	{ "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
 	{ "Mono DAC MIXL", NULL, "dac mono left filter" },
 	{ "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
 	{ "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
 	{ "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
 	{ "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
 	{ "Mono DAC MIXR", NULL, "dac mono right filter" },
 	{ "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
 	{ "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
 	{ "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
 	{ "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
 	{ "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
 	{ "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
 	{ "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
 	{ "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
 	{ "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
 	{ "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
 	{ "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
 	{ "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
 	{ "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
 	{ "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
 	{ "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
 	{ "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
 	{ "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
 	{ "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
 	{ "Mono DAC MIX", NULL, "Mono DAC MIXL" },
 	{ "Mono DAC MIX", NULL, "Mono DAC MIXR" },
 	{ "DD1 MIX", NULL, "DD1 MIXL" },
 	{ "DD1 MIX", NULL, "DD1 MIXR" },
 	{ "DD2 MIX", NULL, "DD2 MIXL" },
 	{ "DD2 MIX", NULL, "DD2 MIXR" },
 	{ "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
 	{ "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
 	{ "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
 	{ "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
 	{ "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
 	{ "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
 	{ "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
 	{ "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
 	{ "DAC 1", NULL, "DAC12 SRC Mux" },
 	{ "DAC 1", NULL, "PLL1", is_sys_clk_from_pll },
 	{ "DAC 2", NULL, "DAC12 SRC Mux" },
 	{ "DAC 2", NULL, "PLL1", is_sys_clk_from_pll },
 	{ "DAC 3", NULL, "DAC3 SRC Mux" },
 	{ "DAC 3", NULL, "PLL1", is_sys_clk_from_pll },
 	{ "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
 	{ "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
 	{ "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
 	{ "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
 	{ "PDM1 L Mux", NULL, "PDM1 Power" },
 	{ "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
 	{ "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
 	{ "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
 	{ "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
 	{ "PDM1 R Mux", NULL, "PDM1 Power" },
 	{ "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
 	{ "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
 	{ "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
 	{ "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
 	{ "PDM2 L Mux", NULL, "PDM2 Power" },
 	{ "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
 	{ "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
 	{ "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
 	{ "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
 	{ "PDM2 R Mux", NULL, "PDM2 Power" },
 	{ "LOUT1 amp", NULL, "DAC 1" },
 	{ "LOUT2 amp", NULL, "DAC 2" },
 	{ "LOUT3 amp", NULL, "DAC 3" },
 	{ "LOUT1 vref", NULL, "LOUT1 amp" },
 	{ "LOUT2 vref", NULL, "LOUT2 amp" },
 	{ "LOUT3 vref", NULL, "LOUT3 amp" },
 	{ "LOUT1", NULL, "LOUT1 vref" },
 	{ "LOUT2", NULL, "LOUT2 vref" },
 	{ "LOUT3", NULL, "LOUT3 vref" },
 	{ "PDM1L", NULL, "PDM1 L Mux" },
 	{ "PDM1R", NULL, "PDM1 R Mux" },
 	{ "PDM2L", NULL, "PDM2 L Mux" },
 	{ "PDM2R", NULL, "PDM2 R Mux" },
 };
 static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = {
 	{ "DMIC L2", NULL, "DMIC1 power" },
 	{ "DMIC R2", NULL, "DMIC1 power" },
 };
 static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = {
 	{ "DMIC L2", NULL, "DMIC2 power" },
 	{ "DMIC R2", NULL, "DMIC2 power" },
 };
 static int rt5677_hw_params(struct snd_pcm_substream *substream,
 	struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
 {
 	struct snd_soc_codec *codec = dai->codec;
 	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
 	unsigned int val_len = 0, val_clk, mask_clk;
 	int pre_div, bclk_ms, frame_size;
 	rt5677->lrck[dai->id] = params_rate(params);
 	pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
 	if (pre_div < 0) {
 		dev_err(codec->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n",
 			rt5677->sysclk, rt5677->lrck[dai->id]);
 		return -EINVAL;
 	}
 	frame_size = snd_soc_params_to_frame_size(params);
 	if (frame_size < 0) {
 		dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
 		return -EINVAL;
 	}
 	bclk_ms = frame_size > 32;
 	rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
 	dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
 		rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
 	dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
 				bclk_ms, pre_div, dai->id);
 	switch (params_width(params)) {
 	case 16:
 		break;
 	case 20:
 		val_len |= RT5677_I2S_DL_20;
 		break;
 	case 24:
 		val_len |= RT5677_I2S_DL_24;
 		break;
 	case 8:
 		val_len |= RT5677_I2S_DL_8;
 		break;
 	default:
 		return -EINVAL;
 	}
 	switch (dai->id) {
 	case RT5677_AIF1:
 		mask_clk = RT5677_I2S_PD1_MASK;
 		val_clk = pre_div << RT5677_I2S_PD1_SFT;
 		regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
 			RT5677_I2S_DL_MASK, val_len);
 		regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
 			mask_clk, val_clk);
 		break;
 	case RT5677_AIF2:
 		mask_clk = RT5677_I2S_PD2_MASK;
 		val_clk = pre_div << RT5677_I2S_PD2_SFT;
 		regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
 			RT5677_I2S_DL_MASK, val_len);
 		regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
 			mask_clk, val_clk);
 		break;
 	case RT5677_AIF3:
 		mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
 		val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
 			pre_div << RT5677_I2S_PD3_SFT;
 		regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
 			RT5677_I2S_DL_MASK, val_len);
 		regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
 			mask_clk, val_clk);
 		break;
 	case RT5677_AIF4:
 		mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
 		val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
 			pre_div << RT5677_I2S_PD4_SFT;
 		regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
 			RT5677_I2S_DL_MASK, val_len);
 		regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
 			mask_clk, val_clk);
 		break;
 	default:
 		break;
 	}
 	return 0;
 }
 static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 {
 	struct snd_soc_codec *codec = dai->codec;
 	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
 	unsigned int reg_val = 0;
 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 	case SND_SOC_DAIFMT_CBM_CFM:
 		rt5677->master[dai->id] = 1;
 		break;
 	case SND_SOC_DAIFMT_CBS_CFS:
 		reg_val |= RT5677_I2S_MS_S;
 		rt5677->master[dai->id] = 0;
 		break;
 	default:
 		return -EINVAL;
 	}
 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 	case SND_SOC_DAIFMT_NB_NF:
 		break;
 	case SND_SOC_DAIFMT_IB_NF:
 		reg_val |= RT5677_I2S_BP_INV;
 		break;
 	default:
 		return -EINVAL;
 	}
 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 	case SND_SOC_DAIFMT_I2S:
 		break;
 	case SND_SOC_DAIFMT_LEFT_J:
 		reg_val |= RT5677_I2S_DF_LEFT;
 		break;
 	case SND_SOC_DAIFMT_DSP_A:
 		reg_val |= RT5677_I2S_DF_PCM_A;
 		break;
 	case SND_SOC_DAIFMT_DSP_B:
 		reg_val |= RT5677_I2S_DF_PCM_B;
 		break;
 	default:
 		return -EINVAL;
 	}
 	switch (dai->id) {
 	case RT5677_AIF1:
 		regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
 			RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
 			RT5677_I2S_DF_MASK, reg_val);
 		break;
 	case RT5677_AIF2:
 		regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
 			RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
 			RT5677_I2S_DF_MASK, reg_val);
 		break;
 	case RT5677_AIF3:
 		regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
 			RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
 			RT5677_I2S_DF_MASK, reg_val);
 		break;
 	case RT5677_AIF4:
 		regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
 			RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
 			RT5677_I2S_DF_MASK, reg_val);
 		break;
 	default:
 		break;
 	}
 	return 0;
 }
 static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
 		int clk_id, unsigned int freq, int dir)
 {
 	struct snd_soc_codec *codec = dai->codec;
 	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
 	unsigned int reg_val = 0;
 	if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
 		return 0;
 	switch (clk_id) {
 	case RT5677_SCLK_S_MCLK:
 		reg_val |= RT5677_SCLK_SRC_MCLK;
 		break;
 	case RT5677_SCLK_S_PLL1:
 		reg_val |= RT5677_SCLK_SRC_PLL1;
 		break;
 	case RT5677_SCLK_S_RCCLK:
 		reg_val |= RT5677_SCLK_SRC_RCCLK;
 		break;
 	default:
 		dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
 		return -EINVAL;
 	}
 	regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
 		RT5677_SCLK_SRC_MASK, reg_val);
 	rt5677->sysclk = freq;
 	rt5677->sysclk_src = clk_id;
 	dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
 	return 0;
 }
 /**
  * rt5677_pll_calc - Calcualte PLL M/N/K code.
  * @freq_in: external clock provided to codec.
  * @freq_out: target clock which codec works on.
  * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
  *
  * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
  *
  * Returns 0 for success or negative error code.
  */
 static int rt5677_pll_calc(const unsigned int freq_in,
 	const unsigned int freq_out, struct rl6231_pll_code *pll_code)
 {
 	if (RT5677_PLL_INP_MIN > freq_in)
 		return -EINVAL;
 	return rl6231_pll_calc(freq_in, freq_out, pll_code);
 }
 static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
 			unsigned int freq_in, unsigned int freq_out)
 {
 	struct snd_soc_codec *codec = dai->codec;
 	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
 	struct rl6231_pll_code pll_code;
 	int ret;
 	if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
 	    freq_out == rt5677->pll_out)
 		return 0;
 	if (!freq_in || !freq_out) {
 		dev_dbg(codec->dev, "PLL disabled\n");
 		rt5677->pll_in = 0;
 		rt5677->pll_out = 0;
 		regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
 			RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
 		return 0;
 	}
 	switch (source) {
 	case RT5677_PLL1_S_MCLK:
 		regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
 			RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
 		break;
 	case RT5677_PLL1_S_BCLK1:
 	case RT5677_PLL1_S_BCLK2:
 	case RT5677_PLL1_S_BCLK3:
 	case RT5677_PLL1_S_BCLK4:
 		switch (dai->id) {
 		case RT5677_AIF1:
 			regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
 				RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
 			break;
 		case RT5677_AIF2:
 			regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
 				RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
 			break;
 		case RT5677_AIF3:
 			regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
 				RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
 			break;
 		case RT5677_AIF4:
 			regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
 				RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
 			break;
 		default:
 			break;
 		}
 		break;
 	default:
 		dev_err(codec->dev, "Unknown PLL source %d\n", source);
 		return -EINVAL;
 	}
 	ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
 	if (ret < 0) {
 		dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
 		return ret;
 	}
 	dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n",
 		pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
 		pll_code.n_code, pll_code.k_code);
 	regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
 		pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
 	regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
 		(pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
 		pll_code.m_bp << RT5677_PLL_M_BP_SFT);
 	rt5677->pll_in = freq_in;
 	rt5677->pll_out = freq_out;
 	rt5677->pll_src = source;
 	return 0;
 }
 static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
 			unsigned int rx_mask, int slots, int slot_width)
 {
 	struct snd_soc_codec *codec = dai->codec;
 	unsigned int val = 0;
 	if (rx_mask || tx_mask)
 		val |= (1 << 12);
 	switch (slots) {
 	case 4:
 		val |= (1 << 10);
 		break;
 	case 6:
 		val |= (2 << 10);
 		break;
 	case 8:
 		val |= (3 << 10);
 		break;
 	case 2:
 	default:
 		break;
 	}
 	switch (slot_width) {
 	case 20:
 		val |= (1 << 8);
 		break;
 	case 24:
 		val |= (2 << 8);
 		break;
 	case 32:
 		val |= (3 << 8);
 		break;
 	case 16:
 	default:
 		break;
 	}
 	switch (dai->id) {
 	case RT5677_AIF1:
 		snd_soc_update_bits(codec, RT5677_TDM1_CTRL1, 0x1f00, val);
 		break;
 	case RT5677_AIF2:
 		snd_soc_update_bits(codec, RT5677_TDM2_CTRL1, 0x1f00, val);
 		break;
 	default:
 		break;
 	}
 	return 0;
 }
 static int rt5677_set_bias_level(struct snd_soc_codec *codec,
 			enum snd_soc_bias_level level)
 {
 	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
 	switch (level) {
 	case SND_SOC_BIAS_ON:
 		break;
 	case SND_SOC_BIAS_PREPARE:
 		if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
 			rt5677_set_dsp_vad(codec, false);
 			regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
 				RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
 				0x0055);
 			regmap_update_bits(rt5677->regmap,
 				RT5677_PR_BASE + RT5677_BIAS_CUR4,
 				0x0f00, 0x0f00);
 			regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
 				RT5677_PWR_FV1 | RT5677_PWR_FV2 |
 				RT5677_PWR_VREF1 | RT5677_PWR_MB |
 				RT5677_PWR_BG | RT5677_PWR_VREF2,
 				RT5677_PWR_VREF1 | RT5677_PWR_MB |
 				RT5677_PWR_BG | RT5677_PWR_VREF2);
 			rt5677->is_vref_slow = false;
 			regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
 				RT5677_PWR_CORE, RT5677_PWR_CORE);
 			regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
 				0x1, 0x1);
 		}
 		break;
 	case SND_SOC_BIAS_STANDBY:
 		break;
 	case SND_SOC_BIAS_OFF:
 		regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
 		regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
 		regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
 		regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022);
 		regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
 		regmap_update_bits(rt5677->regmap,
 			RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
 		if (rt5677->dsp_vad_en)
 			rt5677_set_dsp_vad(codec, true);
 		break;
 	default:
 		break;
 	}
 	codec->dapm.bias_level = level;
 	return 0;
 }
 #ifdef CONFIG_GPIOLIB
 static inline struct rt5677_priv *gpio_to_rt5677(struct gpio_chip *chip)
 {
 	return container_of(chip, struct rt5677_priv, gpio_chip);
 }
 static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 {
 	struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
 	switch (offset) {
 	case RT5677_GPIO1 ... RT5677_GPIO5:
 		regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
 			0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1));
 		break;
 	case RT5677_GPIO6:
 		regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
 			RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT);
 		break;
 	default:
 		break;
 	}
 }
 static int rt5677_gpio_direction_out(struct gpio_chip *chip,
 				     unsigned offset, int value)
 {
 	struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
 	switch (offset) {
 	case RT5677_GPIO1 ... RT5677_GPIO5:
 		regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
 			0x3 << (offset * 3 + 1),
 			(0x2 | !!value) << (offset * 3 + 1));
 		break;
 	case RT5677_GPIO6:
 		regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
 			RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK,
 			RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT);
 		break;
 	default:
 		break;
 	}
 	return 0;
 }
 static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset)
 {
 	struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
 	int value, ret;
 	ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
 	if (ret < 0)
 		return ret;
 	return (value & (0x1 << offset)) >> offset;
 }
 static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
 {
 	struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
 	switch (offset) {
 	case RT5677_GPIO1 ... RT5677_GPIO5:
 		regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
 			0x1 << (offset * 3 + 2), 0x0);
 		break;
 	case RT5677_GPIO6:
 		regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
 			RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN);
 		break;
 	default:
 		break;
 	}
 	return 0;
 }
 /** Configures the gpio as
  *   0 - floating
  *   1 - pull down
  *   2 - pull up
  */
 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
 		int value)
 {
 	int shift;
 	switch (offset) {
 	case RT5677_GPIO1 ... RT5677_GPIO2:
 		shift = 2 * (1 - offset);
 		regmap_update_bits(rt5677->regmap,
 			RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2,
 			0x3 << shift,
 			(value & 0x3) << shift);
 		break;
 	case RT5677_GPIO3 ... RT5677_GPIO6:
 		shift = 2 * (9 - offset);
 		regmap_update_bits(rt5677->regmap,
 			RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3,
 			0x3 << shift,
 			(value & 0x3) << shift);
 		break;
 	default:
 		break;
 	}
 }
 static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset)
 {
 	struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
 	struct regmap_irq_chip_data *data = rt5677->irq_data;
 	int irq;
 	if (offset >= RT5677_GPIO1 && offset <= RT5677_GPIO3) {
 		if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) ||
 			(rt5677->pdata.jd1_gpio == 2 &&
 				offset == RT5677_GPIO2) ||
 			(rt5677->pdata.jd1_gpio == 3 &&
 				offset == RT5677_GPIO3)) {
 			irq = RT5677_IRQ_JD1;
 		} else {
 			return -ENXIO;
 		}
 	}
 	if (offset >= RT5677_GPIO4 && offset <= RT5677_GPIO6) {
 		if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) ||
 			(rt5677->pdata.jd2_gpio == 2 &&
 				offset == RT5677_GPIO5) ||
 			(rt5677->pdata.jd2_gpio == 3 &&
 				offset == RT5677_GPIO6)) {
 			irq = RT5677_IRQ_JD2;
 		} else if ((rt5677->pdata.jd3_gpio == 1 &&
 				offset == RT5677_GPIO4) ||
 			(rt5677->pdata.jd3_gpio == 2 &&
 				offset == RT5677_GPIO5) ||
 			(rt5677->pdata.jd3_gpio == 3 &&
 				offset == RT5677_GPIO6)) {
 			irq = RT5677_IRQ_JD3;
 		} else {
 			return -ENXIO;
 		}
 	}
 	return regmap_irq_get_virq(data, irq);
 }
 static struct gpio_chip rt5677_template_chip = {
 	.label			= "rt5677",
 	.owner			= THIS_MODULE,
 	.direction_output	= rt5677_gpio_direction_out,
 	.set			= rt5677_gpio_set,
 	.direction_input	= rt5677_gpio_direction_in,
 	.get			= rt5677_gpio_get,
 	.to_irq			= rt5677_to_irq,
 	.can_sleep		= 1,
 };
 static void rt5677_init_gpio(struct i2c_client *i2c)
 {
 	struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
 	int ret;
 	rt5677->gpio_chip = rt5677_template_chip;
 	rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
 	rt5677->gpio_chip.dev = &i2c->dev;
 	rt5677->gpio_chip.base = -1;
 	ret = gpiochip_add(&rt5677->gpio_chip);
 	if (ret != 0)
 		dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
 }
 static void rt5677_free_gpio(struct i2c_client *i2c)
 {
 	struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
 	gpiochip_remove(&rt5677->gpio_chip);
 }
 #else
 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
 		int value)
 {
 }
 static void rt5677_init_gpio(struct i2c_client *i2c)
 {
 }
 static void rt5677_free_gpio(struct i2c_client *i2c)
 {
 }
 #endif
 static int rt5677_probe(struct snd_soc_codec *codec)
 {
 	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
 	int i;
 	rt5677->codec = codec;
 	if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
 		snd_soc_dapm_add_routes(&codec->dapm,
 			rt5677_dmic2_clk_2,
 			ARRAY_SIZE(rt5677_dmic2_clk_2));
 	} else { /*use dmic1 clock by default*/
 		snd_soc_dapm_add_routes(&codec->dapm,
 			rt5677_dmic2_clk_1,
 			ARRAY_SIZE(rt5677_dmic2_clk_1));
 	}
 	rt5677_set_bias_level(codec, SND_SOC_BIAS_OFF);
 	regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020);
 	regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
 	for (i = 0; i < RT5677_GPIO_NUM; i++)
 		rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
 	if (rt5677->irq_data) {
 		regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 0x8000,
 			0x8000);
 		regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x0018,
 			0x0008);
 		if (rt5677->pdata.jd1_gpio)
 			regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
 				RT5677_SEL_GPIO_JD1_MASK,
 				rt5677->pdata.jd1_gpio <<
 				RT5677_SEL_GPIO_JD1_SFT);
 		if (rt5677->pdata.jd2_gpio)
 			regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
 				RT5677_SEL_GPIO_JD2_MASK,
 				rt5677->pdata.jd2_gpio <<
 				RT5677_SEL_GPIO_JD2_SFT);
 		if (rt5677->pdata.jd3_gpio)
 			regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
 				RT5677_SEL_GPIO_JD3_MASK,
 				rt5677->pdata.jd3_gpio <<
 				RT5677_SEL_GPIO_JD3_SFT);
 	}
 	mutex_init(&rt5677->dsp_cmd_lock);
 	mutex_init(&rt5677->dsp_pri_lock);
 	return 0;
 }
 static int rt5677_remove(struct snd_soc_codec *codec)
 {
 	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
 	regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
 	if (gpio_is_valid(rt5677->pow_ldo2))
 		gpio_set_value_cansleep(rt5677->pow_ldo2, 0);
 	return 0;
 }
 #ifdef CONFIG_PM
 static int rt5677_suspend(struct snd_soc_codec *codec)
 {
 	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
 	if (!rt5677->dsp_vad_en) {
 		regcache_cache_only(rt5677->regmap, true);
 		regcache_mark_dirty(rt5677->regmap);
 	}
 	if (gpio_is_valid(rt5677->pow_ldo2))
 		gpio_set_value_cansleep(rt5677->pow_ldo2, 0);
 	return 0;
 }
 static int rt5677_resume(struct snd_soc_codec *codec)
 {
 	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
 	if (gpio_is_valid(rt5677->pow_ldo2)) {
 		gpio_set_value_cansleep(rt5677->pow_ldo2, 1);
 		msleep(10);
 	}
 	if (!rt5677->dsp_vad_en) {
 		regcache_cache_only(rt5677->regmap, false);
 		regcache_sync(rt5677->regmap);
 	}
 	return 0;
 }
 #else
 #define rt5677_suspend NULL
 #define rt5677_resume NULL
 #endif
 static int rt5677_read(void *context, unsigned int reg, unsigned int *val)
 {
 	struct i2c_client *client = context;
 	struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
 	if (rt5677->is_dsp_mode) {
 		if (reg > 0xff) {
 			mutex_lock(&rt5677->dsp_pri_lock);
 			rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
 				reg & 0xff);
 			rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val);
 			mutex_unlock(&rt5677->dsp_pri_lock);
 		} else {
 			rt5677_dsp_mode_i2c_read(rt5677, reg, val);
 		}
 	} else {
 		regmap_read(rt5677->regmap_physical, reg, val);
 	}
 	return 0;
 }
 static int rt5677_write(void *context, unsigned int reg, unsigned int val)
 {
 	struct i2c_client *client = context;
 	struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
 	if (rt5677->is_dsp_mode) {
 		if (reg > 0xff) {
 			mutex_lock(&rt5677->dsp_pri_lock);
 			rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
 				reg & 0xff);
 			rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA,
 				val);
 			mutex_unlock(&rt5677->dsp_pri_lock);
 		} else {
 			rt5677_dsp_mode_i2c_write(rt5677, reg, val);
 		}
 	} else {
 		regmap_write(rt5677->regmap_physical, reg, val);
 	}
 	return 0;
 }
 #define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
 #define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
 			SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
 static struct snd_soc_dai_ops rt5677_aif_dai_ops = {
 	.hw_params = rt5677_hw_params,
 	.set_fmt = rt5677_set_dai_fmt,
 	.set_sysclk = rt5677_set_dai_sysclk,
 	.set_pll = rt5677_set_dai_pll,
 	.set_tdm_slot = rt5677_set_tdm_slot,
 };
 static struct snd_soc_dai_driver rt5677_dai[] = {
 	{
 		.name = "rt5677-aif1",
 		.id = RT5677_AIF1,
 		.playback = {
 			.stream_name = "AIF1 Playback",
 			.channels_min = 1,
 			.channels_max = 2,
 			.rates = RT5677_STEREO_RATES,
 			.formats = RT5677_FORMATS,
 		},
 		.capture = {
 			.stream_name = "AIF1 Capture",
 			.channels_min = 1,
 			.channels_max = 2,
 			.rates = RT5677_STEREO_RATES,
 			.formats = RT5677_FORMATS,
 		},
 		.ops = &rt5677_aif_dai_ops,
 	},
 	{
 		.name = "rt5677-aif2",
 		.id = RT5677_AIF2,
 		.playback = {
 			.stream_name = "AIF2 Playback",
 			.channels_min = 1,
 			.channels_max = 2,
 			.rates = RT5677_STEREO_RATES,
 			.formats = RT5677_FORMATS,
 		},
 		.capture = {
 			.stream_name = "AIF2 Capture",
 			.channels_min = 1,
 			.channels_max = 2,
 			.rates = RT5677_STEREO_RATES,
 			.formats = RT5677_FORMATS,
 		},
 		.ops = &rt5677_aif_dai_ops,
 	},
 	{
 		.name = "rt5677-aif3",
 		.id = RT5677_AIF3,
 		.playback = {
 			.stream_name = "AIF3 Playback",
 			.channels_min = 1,
 			.channels_max = 2,
 			.rates = RT5677_STEREO_RATES,
 			.formats = RT5677_FORMATS,
 		},
 		.capture = {
 			.stream_name = "AIF3 Capture",
 			.channels_min = 1,
 			.channels_max = 2,
 			.rates = RT5677_STEREO_RATES,
 			.formats = RT5677_FORMATS,
 		},
 		.ops = &rt5677_aif_dai_ops,
 	},
 	{
 		.name = "rt5677-aif4",
 		.id = RT5677_AIF4,
 		.playback = {
 			.stream_name = "AIF4 Playback",
 			.channels_min = 1,
 			.channels_max = 2,
 			.rates = RT5677_STEREO_RATES,
 			.formats = RT5677_FORMATS,
 		},
 		.capture = {
 			.stream_name = "AIF4 Capture",
 			.channels_min = 1,
 			.channels_max = 2,
 			.rates = RT5677_STEREO_RATES,
 			.formats = RT5677_FORMATS,
 		},
 		.ops = &rt5677_aif_dai_ops,
 	},
 	{
 		.name = "rt5677-slimbus",
 		.id = RT5677_AIF5,
 		.playback = {
 			.stream_name = "SLIMBus Playback",
 			.channels_min = 1,
 			.channels_max = 2,
 			.rates = RT5677_STEREO_RATES,
 			.formats = RT5677_FORMATS,
 		},
 		.capture = {
 			.stream_name = "SLIMBus Capture",
 			.channels_min = 1,
 			.channels_max = 2,
 			.rates = RT5677_STEREO_RATES,
 			.formats = RT5677_FORMATS,
 		},
 		.ops = &rt5677_aif_dai_ops,
 	},
 };
 static struct snd_soc_codec_driver soc_codec_dev_rt5677 = {
 	.probe = rt5677_probe,
 	.remove = rt5677_remove,
 	.suspend = rt5677_suspend,
 	.resume = rt5677_resume,
 	.set_bias_level = rt5677_set_bias_level,
 	.idle_bias_off = true,
 	.controls = rt5677_snd_controls,
 	.num_controls = ARRAY_SIZE(rt5677_snd_controls),
 	.dapm_widgets = rt5677_dapm_widgets,
 	.num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
 	.dapm_routes = rt5677_dapm_routes,
 	.num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
 };
 static const struct regmap_config rt5677_regmap_physical = {
 	.name = "physical",
 	.reg_bits = 8,
 	.val_bits = 16,
 	.max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
 						RT5677_PR_SPACING),
 	.readable_reg = rt5677_readable_register,
 	.cache_type = REGCACHE_NONE,
 	.ranges = rt5677_ranges,
 	.num_ranges = ARRAY_SIZE(rt5677_ranges),
 };
 static const struct regmap_config rt5677_regmap = {
 	.reg_bits = 8,
 	.val_bits = 16,
 	.max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
 						RT5677_PR_SPACING),
 	.volatile_reg = rt5677_volatile_register,
 	.readable_reg = rt5677_readable_register,
 	.reg_read = rt5677_read,
 	.reg_write = rt5677_write,
 	.cache_type = REGCACHE_RBTREE,
 	.reg_defaults = rt5677_reg,
 	.num_reg_defaults = ARRAY_SIZE(rt5677_reg),
 	.ranges = rt5677_ranges,
 	.num_ranges = ARRAY_SIZE(rt5677_ranges),
 };
 static const struct i2c_device_id rt5677_i2c_id[] = {
 	{ "rt5677", 0 },
 	{ }
 };
 MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id);
 static int rt5677_parse_dt(struct rt5677_priv *rt5677, struct device_node *np)
 {
 	rt5677->pdata.in1_diff = of_property_read_bool(np,
 					"realtek,in1-differential");
 	rt5677->pdata.in2_diff = of_property_read_bool(np,
 					"realtek,in2-differential");
 	rt5677->pdata.lout1_diff = of_property_read_bool(np,
 					"realtek,lout1-differential");
 	rt5677->pdata.lout2_diff = of_property_read_bool(np,
 					"realtek,lout2-differential");
 	rt5677->pdata.lout3_diff = of_property_read_bool(np,
 					"realtek,lout3-differential");
 	rt5677->pow_ldo2 = of_get_named_gpio(np,
 					"realtek,pow-ldo2-gpio", 0);
 	/*
 	 * POW_LDO2 is optional (it may be statically tied on the board).
 	 * -ENOENT means that the property doesn't exist, i.e. there is no
 	 * GPIO, so is not an error. Any other error code means the property
 	 * exists, but could not be parsed.
 	 */
 	if (!gpio_is_valid(rt5677->pow_ldo2) &&
 			(rt5677->pow_ldo2 != -ENOENT))
 		return rt5677->pow_ldo2;
 	of_property_read_u8_array(np, "realtek,gpio-config",
 		rt5677->pdata.gpio_config, RT5677_GPIO_NUM);
 	of_property_read_u32(np, "realtek,jd1-gpio", &rt5677->pdata.jd1_gpio);
 	of_property_read_u32(np, "realtek,jd2-gpio", &rt5677->pdata.jd2_gpio);
 	of_property_read_u32(np, "realtek,jd3-gpio", &rt5677->pdata.jd3_gpio);
 	return 0;
 }
 static struct regmap_irq rt5677_irqs[] = {
 	[RT5677_IRQ_JD1] = {
 		.reg_offset = 0,
 		.mask = RT5677_EN_IRQ_GPIO_JD1,
 	},
 	[RT5677_IRQ_JD2] = {
 		.reg_offset = 0,
 		.mask = RT5677_EN_IRQ_GPIO_JD2,
 	},
 	[RT5677_IRQ_JD3] = {
 		.reg_offset = 0,
 		.mask = RT5677_EN_IRQ_GPIO_JD3,
 	},
 };
 static struct regmap_irq_chip rt5677_irq_chip = {
 	.name = "rt5677",
 	.irqs = rt5677_irqs,
 	.num_irqs = ARRAY_SIZE(rt5677_irqs),
 	.num_regs = 1,
 	.status_base = RT5677_IRQ_CTRL1,
 	.mask_base = RT5677_IRQ_CTRL1,
 	.mask_invert = 1,
 };
 static int rt5677_init_irq(struct i2c_client *i2c)
 {
 	int ret;
 	struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
 	if (!rt5677->pdata.jd1_gpio &&
 		!rt5677->pdata.jd2_gpio &&
 		!rt5677->pdata.jd3_gpio)
 		return 0;
 	if (!i2c->irq) {
 		dev_err(&i2c->dev, "No interrupt specified\n");
 		return -EINVAL;
 	}
 	ret = regmap_add_irq_chip(rt5677->regmap, i2c->irq,
 		IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 0,
 		&rt5677_irq_chip, &rt5677->irq_data);
 	if (ret != 0) {
 		dev_err(&i2c->dev, "Failed to register IRQ chip: %d\n", ret);
 		return ret;
 	}
 	return 0;
 }
 static void rt5677_free_irq(struct i2c_client *i2c)
 {
 	struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
 	if (rt5677->irq_data)
 		regmap_del_irq_chip(i2c->irq, rt5677->irq_data);
 }
 static int rt5677_i2c_probe(struct i2c_client *i2c,
 		    const struct i2c_device_id *id)
 {
 	struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev);
 	struct rt5677_priv *rt5677;
 	int ret;
 	unsigned int val;
 	rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
 				GFP_KERNEL);
 	if (rt5677 == NULL)
 		return -ENOMEM;
 	i2c_set_clientdata(i2c, rt5677);
 	if (pdata)
 		rt5677->pdata = *pdata;
 	if (i2c->dev.of_node) {
 		ret = rt5677_parse_dt(rt5677, i2c->dev.of_node);
 		if (ret) {
 			dev_err(&i2c->dev, "Failed to parse device tree: %d\n",
 				ret);
 			return ret;
 		}
 	} else {
 		rt5677->pow_ldo2 = -EINVAL;
 	}
 	if (gpio_is_valid(rt5677->pow_ldo2)) {
 		ret = devm_gpio_request_one(&i2c->dev, rt5677->pow_ldo2,
 					    GPIOF_OUT_INIT_HIGH,
 					    "RT5677 POW_LDO2");
 		if (ret < 0) {
 			dev_err(&i2c->dev, "Failed to request POW_LDO2 %d: %d\n",
 				rt5677->pow_ldo2, ret);
 			return ret;
 		}
 		/* Wait a while until I2C bus becomes available. The datasheet
 		 * does not specify the exact we should wait but startup
 		 * sequence mentiones at least a few milliseconds.
 		 */
 		msleep(10);
 	}
 	rt5677->regmap_physical = devm_regmap_init_i2c(i2c,
 					&rt5677_regmap_physical);
 	if (IS_ERR(rt5677->regmap_physical)) {
 		ret = PTR_ERR(rt5677->regmap_physical);
 		dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
 			ret);
 		return ret;
 	}
 	rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap);
 	if (IS_ERR(rt5677->regmap)) {
 		ret = PTR_ERR(rt5677->regmap);
 		dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
 			ret);
 		return ret;
 	}
 	regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
 	if (val != RT5677_DEVICE_ID) {
 		dev_err(&i2c->dev,
 			"Device with ID register %x is not rt5677\n", val);
 		return -ENODEV;
 	}
 	regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
 	ret = regmap_register_patch(rt5677->regmap, init_list,
 				    ARRAY_SIZE(init_list));
 	if (ret != 0)
 		dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
 	if (rt5677->pdata.in1_diff)
 		regmap_update_bits(rt5677->regmap, RT5677_IN1,
 					RT5677_IN_DF1, RT5677_IN_DF1);
 	if (rt5677->pdata.in2_diff)
 		regmap_update_bits(rt5677->regmap, RT5677_IN1,
 					RT5677_IN_DF2, RT5677_IN_DF2);
 	if (rt5677->pdata.lout1_diff)
 		regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
 					RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF);
 	if (rt5677->pdata.lout2_diff)
 		regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
 					RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF);
 	if (rt5677->pdata.lout3_diff)
 		regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
 					RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF);
 	if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
 		regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
 					RT5677_GPIO5_FUNC_MASK,
 					RT5677_GPIO5_FUNC_DMIC);
 		regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
 					RT5677_GPIO5_DIR_MASK,
 					RT5677_GPIO5_DIR_OUT);
 	}
 	rt5677_init_gpio(i2c);
 	rt5677_init_irq(i2c);
 	return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
 				      rt5677_dai, ARRAY_SIZE(rt5677_dai));
 }
 static int rt5677_i2c_remove(struct i2c_client *i2c)
 {
 	snd_soc_unregister_codec(&i2c->dev);
 	rt5677_free_irq(i2c);
 	rt5677_free_gpio(i2c);
 	return 0;
 }
 static struct i2c_driver rt5677_i2c_driver = {
 	.driver = {
 		.name = "rt5677",
 		.owner = THIS_MODULE,
 	},
 	.probe = rt5677_i2c_probe,
 	.remove   = rt5677_i2c_remove,
 	.id_table = rt5677_i2c_id,
 };
 module_i2c_driver(rt5677_i2c_driver);
 MODULE_DESCRIPTION("ASoC RT5677 driver");
 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
 MODULE_LICENSE("GPL v2");

sound/soc/dwc/designware_i2s.c

Diff comments View file @ e83ce4a

 /*
  * ALSA SoC Synopsys I2S Audio Layer
  *
  * sound/soc/dwc/designware_i2s.c
  *
  * Copyright (C) 2010 ST Microelectronics
  * Rajeev Kumar <rajeevkumar.linux@gmail.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 #include <linux/clk.h>
 #include <linux/device.h>
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/interrupt.h>
 #include <linux/module.h>
 #include <linux/slab.h>
 #include <sound/designware_i2s.h>
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
 /* common register for all channel */
 #define IER		0x000
 #define IRER		0x004
 #define ITER		0x008
 #define CER		0x00C
 #define CCR		0x010
 #define RXFFR		0x014
 #define TXFFR		0x018
 /* I2STxRxRegisters for all channels */
 #define LRBR_LTHR(x)	(0x40 * x + 0x020)
 #define RRBR_RTHR(x)	(0x40 * x + 0x024)
 #define RER(x)		(0x40 * x + 0x028)
 #define TER(x)		(0x40 * x + 0x02C)
 #define RCR(x)		(0x40 * x + 0x030)
 #define TCR(x)		(0x40 * x + 0x034)
 #define ISR(x)		(0x40 * x + 0x038)
 #define IMR(x)		(0x40 * x + 0x03C)
 #define ROR(x)		(0x40 * x + 0x040)
 #define TOR(x)		(0x40 * x + 0x044)
 #define RFCR(x)		(0x40 * x + 0x048)
 #define TFCR(x)		(0x40 * x + 0x04C)
 #define RFF(x)		(0x40 * x + 0x050)
 #define TFF(x)		(0x40 * x + 0x054)
 /* I2SCOMPRegisters */
 #define I2S_COMP_PARAM_2	0x01F0
 #define I2S_COMP_PARAM_1	0x01F4
 #define I2S_COMP_VERSION	0x01F8
 #define I2S_COMP_TYPE		0x01FC
 #define MAX_CHANNEL_NUM		8
 #define MIN_CHANNEL_NUM		2
 struct dw_i2s_dev {
 	void __iomem *i2s_base;
 	struct clk *clk;
 	int active;
 	unsigned int capability;
 	struct device *dev;
 	/* data related to DMA transfers b/w i2s and DMAC */
 	struct i2s_dma_data play_dma_data;
 	struct i2s_dma_data capture_dma_data;
 	struct i2s_clk_config_data config;
 	int (*i2s_clk_cfg)(struct i2s_clk_config_data *config);
 };
 static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val)
 {
 	writel(val, io_base + reg);
 }
 static inline u32 i2s_read_reg(void __iomem *io_base, int reg)
 {
 	return readl(io_base + reg);
 }
 static inline void i2s_disable_channels(struct dw_i2s_dev *dev, u32 stream)
 {
 	u32 i = 0;
 	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
 		for (i = 0; i < 4; i++)
 			i2s_write_reg(dev->i2s_base, TER(i), 0);
 	} else {
 		for (i = 0; i < 4; i++)
 			i2s_write_reg(dev->i2s_base, RER(i), 0);
 	}
 }
 static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream)
 {
 	u32 i = 0;
 	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
 		for (i = 0; i < 4; i++)
 			i2s_write_reg(dev->i2s_base, TOR(i), 0);
 	} else {
 		for (i = 0; i < 4; i++)
 			i2s_write_reg(dev->i2s_base, ROR(i), 0);
 	}
 }
 static void i2s_start(struct dw_i2s_dev *dev,
 		      struct snd_pcm_substream *substream)
 {
 	i2s_write_reg(dev->i2s_base, IER, 1);
 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 		i2s_write_reg(dev->i2s_base, ITER, 1);
 	else
 		i2s_write_reg(dev->i2s_base, IRER, 1);
 	i2s_write_reg(dev->i2s_base, CER, 1);
 }
 static void i2s_stop(struct dw_i2s_dev *dev,
 		struct snd_pcm_substream *substream)
 {
 	u32 i = 0, irq;
 	i2s_clear_irqs(dev, substream->stream);
 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 		i2s_write_reg(dev->i2s_base, ITER, 0);
 		for (i = 0; i < 4; i++) {
 			irq = i2s_read_reg(dev->i2s_base, IMR(i));
 			i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30);
 		}
 	} else {
 		i2s_write_reg(dev->i2s_base, IRER, 0);
 		for (i = 0; i < 4; i++) {
 			irq = i2s_read_reg(dev->i2s_base, IMR(i));
 			i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03);
 		}
 	}
 	if (!dev->active) {
 		i2s_write_reg(dev->i2s_base, CER, 0);
 		i2s_write_reg(dev->i2s_base, IER, 0);
 	}
 }
 static int dw_i2s_startup(struct snd_pcm_substream *substream,
 		struct snd_soc_dai *cpu_dai)
 {
 	struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
 	struct i2s_dma_data *dma_data = NULL;
 	if (!(dev->capability & DWC_I2S_RECORD) &&
 			(substream->stream == SNDRV_PCM_STREAM_CAPTURE))
 		return -EINVAL;
 	if (!(dev->capability & DWC_I2S_PLAY) &&
 			(substream->stream == SNDRV_PCM_STREAM_PLAYBACK))
 		return -EINVAL;
 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 		dma_data = &dev->play_dma_data;
 	else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 		dma_data = &dev->capture_dma_data;
 	snd_soc_dai_set_dma_data(cpu_dai, substream, (void *)dma_data);
 	return 0;
 }
 static int dw_i2s_hw_params(struct snd_pcm_substream *substream,
 		struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
 {
 	struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 	struct i2s_clk_config_data *config = &dev->config;
 	u32 ccr, xfer_resolution, ch_reg, irq;
 	int ret;
 	switch (params_format(params)) {
 	case SNDRV_PCM_FORMAT_S16_LE:
 		config->data_width = 16;
 		ccr = 0x00;
 		xfer_resolution = 0x02;
 		break;
 	case SNDRV_PCM_FORMAT_S24_LE:
 		config->data_width = 24;
 		ccr = 0x08;
 		xfer_resolution = 0x04;
 		break;
 	case SNDRV_PCM_FORMAT_S32_LE:
 		config->data_width = 32;
 		ccr = 0x10;
 		xfer_resolution = 0x05;
 		break;
 	default:
 		dev_err(dev->dev, "designware-i2s: unsuppted PCM fmt");
 		return -EINVAL;
 	}
 	config->chan_nr = params_channels(params);
 	switch (config->chan_nr) {
 	case EIGHT_CHANNEL_SUPPORT:
-		ch_reg = 3;
-		break;
 	case SIX_CHANNEL_SUPPORT:
-		ch_reg = 2;
-		break;
 	case FOUR_CHANNEL_SUPPORT:
-		ch_reg = 1;
-		break;
 	case TWO_CHANNEL_SUPPORT:
-		ch_reg = 0;
 		break;
 	default:
 		dev_err(dev->dev, "channel not supported\n");
 		return -EINVAL;
 	}
 	i2s_disable_channels(dev, substream->stream);
-	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+	for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) {
-		i2s_write_reg(dev->i2s_base, TCR(ch_reg), xfer_resolution);
+		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
-		i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02);
+			i2s_write_reg(dev->i2s_base, TCR(ch_reg),
-		irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
+				      xfer_resolution);
-		i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30);
+			i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02);
-		i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);
+			irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
-	} else {
+			i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30);
-		i2s_write_reg(dev->i2s_base, RCR(ch_reg), xfer_resolution);
+			i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);
-		i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07);
+		} else {
-		irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
+			i2s_write_reg(dev->i2s_base, RCR(ch_reg),
-		i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x03);
+				      xfer_resolution);
-		i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);
+			i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07);
+			irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
+			i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x03);
+			i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);
+		}
 	}
 	i2s_write_reg(dev->i2s_base, CCR, ccr);
 	config->sample_rate = params_rate(params);
 	if (!dev->i2s_clk_cfg)
 		return -EINVAL;
 	ret = dev->i2s_clk_cfg(config);
 	if (ret < 0) {
 		dev_err(dev->dev, "runtime audio clk config fail\n");
 		return ret;
 	}
 	return 0;
 }
 static void dw_i2s_shutdown(struct snd_pcm_substream *substream,
 		struct snd_soc_dai *dai)
 {
 	snd_soc_dai_set_dma_data(dai, substream, NULL);
 }
+static int dw_i2s_prepare(struct snd_pcm_substream *substream,
+			  struct snd_soc_dai *dai)
+{
+	struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		i2s_write_reg(dev->i2s_base, TXFFR, 1);
+	else
+		i2s_write_reg(dev->i2s_base, RXFFR, 1);
+	return 0;
+}
 static int dw_i2s_trigger(struct snd_pcm_substream *substream,
 		int cmd, struct snd_soc_dai *dai)
 {
 	struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 	int ret = 0;
 	switch (cmd) {
 	case SNDRV_PCM_TRIGGER_START:
 	case SNDRV_PCM_TRIGGER_RESUME:
 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 		dev->active++;
 		i2s_start(dev, substream);
 		break;
 	case SNDRV_PCM_TRIGGER_STOP:
 	case SNDRV_PCM_TRIGGER_SUSPEND:
 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 		dev->active--;
 		i2s_stop(dev, substream);
 		break;
 	default:
 		ret = -EINVAL;
 		break;
 	}
 	return ret;
 }
 static struct snd_soc_dai_ops dw_i2s_dai_ops = {
 	.startup	= dw_i2s_startup,
 	.shutdown	= dw_i2s_shutdown,
 	.hw_params	= dw_i2s_hw_params,
+	.prepare	= dw_i2s_prepare,
 	.trigger	= dw_i2s_trigger,
 };
 static const struct snd_soc_component_driver dw_i2s_component = {
 	.name		= "dw-i2s",
 };
 #ifdef CONFIG_PM
 static int dw_i2s_suspend(struct snd_soc_dai *dai)
 {
 	struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 	clk_disable(dev->clk);
 	return 0;
 }
 static int dw_i2s_resume(struct snd_soc_dai *dai)
 {
 	struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 	clk_enable(dev->clk);
 	return 0;
 }
 #else
 #define dw_i2s_suspend	NULL
 #define dw_i2s_resume	NULL
 #endif
 static int dw_i2s_probe(struct platform_device *pdev)
 {
 	const struct i2s_platform_data *pdata = pdev->dev.platform_data;
 	struct dw_i2s_dev *dev;
 	struct resource *res;
 	int ret;
 	unsigned int cap;
 	struct snd_soc_dai_driver *dw_i2s_dai;
 	if (!pdata) {
 		dev_err(&pdev->dev, "Invalid platform data\n");
 		return -EINVAL;
 	}
 	dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
 	if (!dev) {
 		dev_warn(&pdev->dev, "kzalloc fail\n");
 		return -ENOMEM;
 	}
 	dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL);
 	if (!dw_i2s_dai) {
 		dev_err(&pdev->dev, "mem allocation failed for dai driver\n");
 		return -ENOMEM;
 	}
 	dw_i2s_dai->ops = &dw_i2s_dai_ops;
 	dw_i2s_dai->suspend = dw_i2s_suspend;
 	dw_i2s_dai->resume = dw_i2s_resume;
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!res) {
 		dev_err(&pdev->dev, "no i2s resource defined\n");
 		return -ENODEV;
 	}
 	dev->i2s_base = devm_ioremap_resource(&pdev->dev, res);
 	if (IS_ERR(dev->i2s_base)) {
 		dev_err(&pdev->dev, "ioremap fail for i2s_region\n");
 		return PTR_ERR(dev->i2s_base);
 	}
 	cap = pdata->cap;
 	dev->capability = cap;
 	dev->i2s_clk_cfg = pdata->i2s_clk_cfg;
 	/* Set DMA slaves info */
 	dev->play_dma_data.data = pdata->play_dma_data;
 	dev->capture_dma_data.data = pdata->capture_dma_data;
 	dev->play_dma_data.addr = res->start + I2S_TXDMA;
 	dev->capture_dma_data.addr = res->start + I2S_RXDMA;
 	dev->play_dma_data.max_burst = 16;
 	dev->capture_dma_data.max_burst = 16;
 	dev->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 	dev->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 	dev->play_dma_data.filter = pdata->filter;
 	dev->capture_dma_data.filter = pdata->filter;
 	dev->clk = clk_get(&pdev->dev, NULL);
 	if (IS_ERR(dev->clk))
 		return  PTR_ERR(dev->clk);
 	ret = clk_enable(dev->clk);
 	if (ret < 0)
 		goto err_clk_put;
 	if (cap & DWC_I2S_PLAY) {
 		dev_dbg(&pdev->dev, " designware: play supported\n");
 		dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM;
 		dw_i2s_dai->playback.channels_max = pdata->channel;
 		dw_i2s_dai->playback.formats = pdata->snd_fmts;
 		dw_i2s_dai->playback.rates = pdata->snd_rates;
 	}
 	if (cap & DWC_I2S_RECORD) {
 		dev_dbg(&pdev->dev, "designware: record supported\n");
 		dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM;
 		dw_i2s_dai->capture.channels_max = pdata->channel;
 		dw_i2s_dai->capture.formats = pdata->snd_fmts;
 		dw_i2s_dai->capture.rates = pdata->snd_rates;
 	}
 	dev->dev = &pdev->dev;
 	dev_set_drvdata(&pdev->dev, dev);
 	ret = snd_soc_register_component(&pdev->dev, &dw_i2s_component,
 					 dw_i2s_dai, 1);
 	if (ret != 0) {
 		dev_err(&pdev->dev, "not able to register dai\n");
 		goto err_clk_disable;
 	}
 	return 0;
 err_clk_disable:
 	clk_disable(dev->clk);
 err_clk_put:
 	clk_put(dev->clk);
 	return ret;
 }
 static int dw_i2s_remove(struct platform_device *pdev)
 {
 	struct dw_i2s_dev *dev = dev_get_drvdata(&pdev->dev);
 	snd_soc_unregister_component(&pdev->dev);
 	clk_put(dev->clk);
 	return 0;
 }
 static struct platform_driver dw_i2s_driver = {
 	.probe		= dw_i2s_probe,
 	.remove		= dw_i2s_remove,
 	.driver		= {
 		.name	= "designware-i2s",
 	},
 };

sound/soc/intel/Kconfig

Diff comments View file @ e83ce4a

1	config SND_MFLD_MACHINE	1	config SND_MFLD_MACHINE
2	tristate "SOC Machine Audio driver for Intel Medfield MID platform"	2	tristate "SOC Machine Audio driver for Intel Medfield MID platform"
3	depends on INTEL_SCU_IPC	3	depends on INTEL_SCU_IPC
4	select SND_SOC_SN95031	4	select SND_SOC_SN95031
5	select SND_SST_MFLD_PLATFORM	5	select SND_SST_MFLD_PLATFORM
6	select SND_SST_IPC_PCI	6	select SND_SST_IPC_PCI
7	help	7	help
8	This adds support for ASoC machine driver for Intel(R) MID Medfield platform	8	This adds support for ASoC machine driver for Intel(R) MID Medfield platform
9	used as alsa device in audio substem in Intel(R) MID devices	9	used as alsa device in audio substem in Intel(R) MID devices
10	Say Y if you have such a device	10	Say Y if you have such a device
11	If unsure select "N".	11	If unsure select "N".
12		12
13	config SND_SST_MFLD_PLATFORM	13	config SND_SST_MFLD_PLATFORM
14	tristate	14	tristate
15		15
16	config SND_SST_IPC	16	config SND_SST_IPC
17	tristate	17	tristate
18		18
19	config SND_SST_IPC_PCI	19	config SND_SST_IPC_PCI
20	tristate	20	tristate
21	select SND_SST_IPC	21	select SND_SST_IPC
22		22
23	config SND_SST_IPC_ACPI	23	config SND_SST_IPC_ACPI
24	tristate	24	tristate
25	select SND_SST_IPC	25	select SND_SST_IPC
26	depends on ACPI	26	depends on ACPI
27		27
28	config SND_SOC_INTEL_SST	28	config SND_SOC_INTEL_SST
29	tristate "ASoC support for Intel(R) Smart Sound Technology"	29	tristate "ASoC support for Intel(R) Smart Sound Technology"
30	select SND_SOC_INTEL_SST_ACPI if ACPI	30	select SND_SOC_INTEL_SST_ACPI if ACPI
31	depends on (X86 \|\| COMPILE_TEST)	31	depends on (X86 \|\| COMPILE_TEST)
32	depends on DW_DMAC_CORE	32	depends on DW_DMAC_CORE
33	help	33	help
34	This adds support for Intel(R) Smart Sound Technology (SST).	34	This adds support for Intel(R) Smart Sound Technology (SST).
35	Say Y if you have such a device	35	Say Y if you have such a device
36	If unsure select "N".	36	If unsure select "N".
37		37
38	config SND_SOC_INTEL_SST_ACPI	38	config SND_SOC_INTEL_SST_ACPI
39	tristate	39	tristate
40		40
41	config SND_SOC_INTEL_HASWELL	41	config SND_SOC_INTEL_HASWELL
42	tristate	42	tristate
43		43
44	config SND_SOC_INTEL_BAYTRAIL	44	config SND_SOC_INTEL_BAYTRAIL
45	tristate	45	tristate
46		46
47	config SND_SOC_INTEL_HASWELL_MACH	47	config SND_SOC_INTEL_HASWELL_MACH
48	tristate "ASoC Audio DSP support for Intel Haswell Lynxpoint"	48	tristate "ASoC Audio DSP support for Intel Haswell Lynxpoint"
49	depends on SND_SOC_INTEL_SST && X86_INTEL_LPSS && I2C && \\	49	depends on SND_SOC_INTEL_SST && X86_INTEL_LPSS && I2C && \\
50	I2C_DESIGNWARE_PLATFORM	50	I2C_DESIGNWARE_PLATFORM
51	select SND_SOC_INTEL_HASWELL	51	select SND_SOC_INTEL_HASWELL
52	select SND_SOC_RT5640	52	select SND_SOC_RT5640
53	help	53	help
54	This adds support for the Lynxpoint Audio DSP on Intel(R) Haswell	54	This adds support for the Lynxpoint Audio DSP on Intel(R) Haswell
55	Ultrabook platforms.	55	Ultrabook platforms.
56	Say Y if you have such a device	56	Say Y if you have such a device
57	If unsure select "N".	57	If unsure select "N".
58		58
59	config SND_SOC_INTEL_BYT_RT5640_MACH	59	config SND_SOC_INTEL_BYT_RT5640_MACH
60	tristate "ASoC Audio driver for Intel Baytrail with RT5640 codec"	60	tristate "ASoC Audio driver for Intel Baytrail with RT5640 codec"
61	depends on SND_SOC_INTEL_SST && X86_INTEL_LPSS && I2C	61	depends on SND_SOC_INTEL_SST && X86_INTEL_LPSS && I2C
62	select SND_SOC_INTEL_BAYTRAIL	62	select SND_SOC_INTEL_BAYTRAIL
63	select SND_SOC_RT5640	63	select SND_SOC_RT5640
64	help	64	help
65	This adds audio driver for Intel Baytrail platform based boards	65	This adds audio driver for Intel Baytrail platform based boards
66	with the RT5640 audio codec.	66	with the RT5640 audio codec.
67		67
68	config SND_SOC_INTEL_BYT_MAX98090_MACH	68	config SND_SOC_INTEL_BYT_MAX98090_MACH
69	tristate "ASoC Audio driver for Intel Baytrail with MAX98090 codec"	69	tristate "ASoC Audio driver for Intel Baytrail with MAX98090 codec"
70	depends on SND_SOC_INTEL_SST && X86_INTEL_LPSS && I2C	70	depends on SND_SOC_INTEL_SST && X86_INTEL_LPSS && I2C
71	select SND_SOC_INTEL_BAYTRAIL	71	select SND_SOC_INTEL_BAYTRAIL
72	select SND_SOC_MAX98090	72	select SND_SOC_MAX98090
73	help	73	help
74	This adds audio driver for Intel Baytrail platform based boards	74	This adds audio driver for Intel Baytrail platform based boards
75	with the MAX98090 audio codec.	75	with the MAX98090 audio codec.
76		76
77	config SND_SOC_INTEL_BROADWELL_MACH	77	config SND_SOC_INTEL_BROADWELL_MACH
78	tristate "ASoC Audio DSP support for Intel Broadwell Wildcatpoint"	78	tristate "ASoC Audio DSP support for Intel Broadwell Wildcatpoint"
79	depends on SND_SOC_INTEL_SST && X86_INTEL_LPSS && DW_DMAC && \\	79	depends on SND_SOC_INTEL_SST && X86_INTEL_LPSS && DW_DMAC && \\
80	I2C_DESIGNWARE_PLATFORM	80	I2C_DESIGNWARE_PLATFORM
81	select SND_SOC_INTEL_HASWELL	81	select SND_SOC_INTEL_HASWELL
82	select SND_COMPRESS_OFFLOAD	82	select SND_COMPRESS_OFFLOAD
83	select SND_SOC_RT286	83	select SND_SOC_RT286
84	help	84	help
85	This adds support for the Wilcatpoint Audio DSP on Intel(R) Broadwell	85	This adds support for the Wilcatpoint Audio DSP on Intel(R) Broadwell
86	Ultrabook platforms.	86	Ultrabook platforms.
87	Say Y if you have such a device	87	Say Y if you have such a device
88	If unsure select "N".	88	If unsure select "N".
89		89
90	config SND_SOC_INTEL_BYTCR_RT5640_MACH	90	config SND_SOC_INTEL_BYTCR_RT5640_MACH
91	tristate "ASoC Audio DSP Support for MID BYT Platform"	91	tristate "ASoC Audio DSP Support for MID BYT Platform"
92	depends on X86	92	depends on X86 && I2C
93	select SND_SOC_RT5640	93	select SND_SOC_RT5640
94	select SND_SST_MFLD_PLATFORM	94	select SND_SST_MFLD_PLATFORM
95	select SND_SST_IPC_ACPI	95	select SND_SST_IPC_ACPI
96	help	96	help
97	This adds support for ASoC machine driver for Intel(R) MID Baytrail platform	97	This adds support for ASoC machine driver for Intel(R) MID Baytrail platform
98	used as alsa device in audio substem in Intel(R) MID devices	98	used as alsa device in audio substem in Intel(R) MID devices
99	Say Y if you have such a device	99	Say Y if you have such a device
100	If unsure select "N".	100	If unsure select "N".
101		101
102	config SND_SOC_INTEL_CHT_BSW_RT5672_MACH	102	config SND_SOC_INTEL_CHT_BSW_RT5672_MACH
103	tristate "ASoC Audio driver for Intel Cherrytrail & Braswell with RT5672 codec"	103	tristate "ASoC Audio driver for Intel Cherrytrail & Braswell with RT5672 codec"
104	depends on X86_INTEL_LPSS	104	depends on X86_INTEL_LPSS && I2C
105	select SND_SOC_RT5670	105	select SND_SOC_RT5670
106	select SND_SST_MFLD_PLATFORM	106	select SND_SST_MFLD_PLATFORM
107	select SND_SST_IPC_ACPI	107	select SND_SST_IPC_ACPI
108	help	108	help
109	This adds support for ASoC machine driver for Intel(R) Cherrytrail & Braswell	109	This adds support for ASoC machine driver for Intel(R) Cherrytrail & Braswell
110	platforms with RT5672 audio codec.	110	platforms with RT5672 audio codec.
111	Say Y if you have such a device	111	Say Y if you have such a device
112	If unsure select "N".	112	If unsure select "N".
113		113

sound/soc/intel/bytcr_dpcm_rt5640.c

Diff comments View file @ e83ce4a

1	/*	1	/*
2	* byt_cr_dpcm_rt5640.c - ASoc Machine driver for Intel Byt CR platform	2	* byt_cr_dpcm_rt5640.c - ASoc Machine driver for Intel Byt CR platform
3	*	3	*
4	* Copyright (C) 2014 Intel Corp	4	* Copyright (C) 2014 Intel Corp
5	* Author: Subhransu S. Prusty <subhransu.s.prusty@intel.com>	5	* Author: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
6	* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~	6	* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
7	*	7	*
8	* This program is free software; you can redistribute it and/or modify	8	* This program is free software; you can redistribute it and/or modify
9	* it under the terms of the GNU General Public License as published by	9	* it under the terms of the GNU General Public License as published by
10	* the Free Software Foundation; version 2 of the License.	10	* the Free Software Foundation; version 2 of the License.
11	*	11	*
12	* This program is distributed in the hope that it will be useful, but	12	* This program is distributed in the hope that it will be useful, but
13	* WITHOUT ANY WARRANTY; without even the implied warranty of	13	* WITHOUT ANY WARRANTY; without even the implied warranty of
14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15	* General Public License for more details.	15	* General Public License for more details.
16	*	16	*
17	* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~	17	* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
18	*/	18	*/
19		19
20	#include <linux/init.h>	20	#include <linux/init.h>
21	#include <linux/module.h>	21	#include <linux/module.h>
22	#include <linux/platform_device.h>	22	#include <linux/platform_device.h>
23	#include <linux/device.h>	23	#include <linux/device.h>
24	#include <linux/slab.h>	24	#include <linux/slab.h>
25	#include <linux/input.h>	25	#include <linux/input.h>
26	#include <sound/pcm.h>	26	#include <sound/pcm.h>
27	#include <sound/pcm_params.h>	27	#include <sound/pcm_params.h>
28	#include <sound/soc.h>	28	#include <sound/soc.h>
29	#include "../codecs/rt5640.h"	29	#include "../codecs/rt5640.h"
30	#include "sst-atom-controls.h"	30	#include "sst-atom-controls.h"
31		31
32	static const struct snd_soc_dapm_widget byt_dapm_widgets[] = {	32	static const struct snd_soc_dapm_widget byt_dapm_widgets[] = {
33	SND_SOC_DAPM_HP("Headphone", NULL),	33	SND_SOC_DAPM_HP("Headphone", NULL),
34	SND_SOC_DAPM_MIC("Headset Mic", NULL),	34	SND_SOC_DAPM_MIC("Headset Mic", NULL),
35	SND_SOC_DAPM_MIC("Int Mic", NULL),	35	SND_SOC_DAPM_MIC("Int Mic", NULL),
36	SND_SOC_DAPM_SPK("Ext Spk", NULL),	36	SND_SOC_DAPM_SPK("Ext Spk", NULL),
37	};	37	};
38		38
39	static const struct snd_soc_dapm_route byt_audio_map[] = {	39	static const struct snd_soc_dapm_route byt_audio_map[] = {
40	{"IN2P", NULL, "Headset Mic"},	40	{"IN2P", NULL, "Headset Mic"},
41	{"IN2N", NULL, "Headset Mic"},	41	{"IN2N", NULL, "Headset Mic"},
42	{"Headset Mic", NULL, "MICBIAS1"},	42	{"Headset Mic", NULL, "MICBIAS1"},
43	{"IN1P", NULL, "MICBIAS1"},	43	{"IN1P", NULL, "MICBIAS1"},
44	{"LDO2", NULL, "Int Mic"},	44	{"LDO2", NULL, "Int Mic"},
45	{"Headphone", NULL, "HPOL"},	45	{"Headphone", NULL, "HPOL"},
46	{"Headphone", NULL, "HPOR"},	46	{"Headphone", NULL, "HPOR"},
47	{"Ext Spk", NULL, "SPOLP"},	47	{"Ext Spk", NULL, "SPOLP"},
48	{"Ext Spk", NULL, "SPOLN"},	48	{"Ext Spk", NULL, "SPOLN"},
49	{"Ext Spk", NULL, "SPORP"},	49	{"Ext Spk", NULL, "SPORP"},
50	{"Ext Spk", NULL, "SPORN"},	50	{"Ext Spk", NULL, "SPORN"},
51		51
52	{"AIF1 Playback", NULL, "ssp2 Tx"},	52	{"AIF1 Playback", NULL, "ssp2 Tx"},
53	{"ssp2 Tx", NULL, "codec_out0"},	53	{"ssp2 Tx", NULL, "codec_out0"},
54	{"ssp2 Tx", NULL, "codec_out1"},	54	{"ssp2 Tx", NULL, "codec_out1"},
55	{"codec_in0", NULL, "ssp2 Rx"},	55	{"codec_in0", NULL, "ssp2 Rx"},
56	{"codec_in1", NULL, "ssp2 Rx"},	56	{"codec_in1", NULL, "ssp2 Rx"},
57	{"ssp2 Rx", NULL, "AIF1 Capture"},	57	{"ssp2 Rx", NULL, "AIF1 Capture"},
58	};	58	};
59		59
60	static const struct snd_kcontrol_new byt_mc_controls[] = {	60	static const struct snd_kcontrol_new byt_mc_controls[] = {
61	SOC_DAPM_PIN_SWITCH("Headphone"),	61	SOC_DAPM_PIN_SWITCH("Headphone"),
62	SOC_DAPM_PIN_SWITCH("Headset Mic"),	62	SOC_DAPM_PIN_SWITCH("Headset Mic"),
63	SOC_DAPM_PIN_SWITCH("Int Mic"),	63	SOC_DAPM_PIN_SWITCH("Int Mic"),
64	SOC_DAPM_PIN_SWITCH("Ext Spk"),	64	SOC_DAPM_PIN_SWITCH("Ext Spk"),
65	};	65	};
66		66
67	static int byt_aif1_hw_params(struct snd_pcm_substream *substream,	67	static int byt_aif1_hw_params(struct snd_pcm_substream *substream,
68	struct snd_pcm_hw_params *params)	68	struct snd_pcm_hw_params *params)
69	{	69	{
70	struct snd_soc_pcm_runtime *rtd = substream->private_data;	70	struct snd_soc_pcm_runtime *rtd = substream->private_data;
71	struct snd_soc_dai *codec_dai = rtd->codec_dai;	71	struct snd_soc_dai *codec_dai = rtd->codec_dai;
72	int ret;	72	int ret;
73		73
74	snd_soc_dai_set_bclk_ratio(codec_dai, 50);	74	snd_soc_dai_set_bclk_ratio(codec_dai, 50);
75		75
76	ret = snd_soc_dai_set_sysclk(codec_dai, RT5640_SCLK_S_PLL1,	76	ret = snd_soc_dai_set_sysclk(codec_dai, RT5640_SCLK_S_PLL1,
77	params_rate(params) * 512,	77	params_rate(params) * 512,
78	SND_SOC_CLOCK_IN);	78	SND_SOC_CLOCK_IN);
79	if (ret < 0) {	79	if (ret < 0) {
80	dev_err(rtd->dev, "can't set codec clock %d\n", ret);	80	dev_err(rtd->dev, "can't set codec clock %d\n", ret);
81	return ret;	81	return ret;
82	}	82	}
83		83
84	ret = snd_soc_dai_set_pll(codec_dai, 0, RT5640_PLL1_S_BCLK1,	84	ret = snd_soc_dai_set_pll(codec_dai, 0, RT5640_PLL1_S_BCLK1,
85	params_rate(params) * 50,	85	params_rate(params) * 50,
86	params_rate(params) * 512);	86	params_rate(params) * 512);
87	if (ret < 0) {	87	if (ret < 0) {
88	dev_err(rtd->dev, "can't set codec pll: %d\n", ret);	88	dev_err(rtd->dev, "can't set codec pll: %d\n", ret);
89	return ret;	89	return ret;
90	}	90	}
91		91
92	return 0;	92	return 0;
93	}	93	}
94		94
95	static const struct snd_soc_pcm_stream byt_dai_params = {	95	static const struct snd_soc_pcm_stream byt_dai_params = {
96	.formats = SNDRV_PCM_FMTBIT_S24_LE,	96	.formats = SNDRV_PCM_FMTBIT_S24_LE,
97	.rate_min = 48000,	97	.rate_min = 48000,
98	.rate_max = 48000,	98	.rate_max = 48000,
99	.channels_min = 2,	99	.channels_min = 2,
100	.channels_max = 2,	100	.channels_max = 2,
101	};	101	};
102		102
103	static int byt_codec_fixup(struct snd_soc_pcm_runtime *rtd,	103	static int byt_codec_fixup(struct snd_soc_pcm_runtime *rtd,
104	struct snd_pcm_hw_params *params)	104	struct snd_pcm_hw_params *params)
105	{	105	{
106	struct snd_interval *rate = hw_param_interval(params,	106	struct snd_interval *rate = hw_param_interval(params,
107	SNDRV_PCM_HW_PARAM_RATE);	107	SNDRV_PCM_HW_PARAM_RATE);
108	struct snd_interval *channels = hw_param_interval(params,	108	struct snd_interval *channels = hw_param_interval(params,
109	SNDRV_PCM_HW_PARAM_CHANNELS);	109	SNDRV_PCM_HW_PARAM_CHANNELS);
110		110
111	/* The DSP will covert the FE rate to 48k, stereo, 24bits */	111	/* The DSP will covert the FE rate to 48k, stereo, 24bits */
112	rate->min = rate->max = 48000;	112	rate->min = rate->max = 48000;
113	channels->min = channels->max = 2;	113	channels->min = channels->max = 2;
114		114
115	/* set SSP2 to 24-bit */	115	/* set SSP2 to 24-bit */
116	snd_mask_set(&params->masks[SNDRV_PCM_HW_PARAM_FORMAT -	116	snd_mask_set(&params->masks[SNDRV_PCM_HW_PARAM_FORMAT -
117	SNDRV_PCM_HW_PARAM_FIRST_MASK],	117	SNDRV_PCM_HW_PARAM_FIRST_MASK],
118	SNDRV_PCM_FORMAT_S24_LE);	118	SNDRV_PCM_FORMAT_S24_LE);
119	return 0;	119	return 0;
120	}	120	}
121		121
122	static unsigned int rates_48000[] = {	122	static unsigned int rates_48000[] = {
123	48000,	123	48000,
124	};	124	};
125		125
126	static struct snd_pcm_hw_constraint_list constraints_48000 = {	126	static struct snd_pcm_hw_constraint_list constraints_48000 = {
127	.count = ARRAY_SIZE(rates_48000),	127	.count = ARRAY_SIZE(rates_48000),
128	.list = rates_48000,	128	.list = rates_48000,
129	};	129	};
130		130
131	static int byt_aif1_startup(struct snd_pcm_substream *substream)	131	static int byt_aif1_startup(struct snd_pcm_substream *substream)
132	{	132	{
133	return snd_pcm_hw_constraint_list(substream->runtime, 0,	133	return snd_pcm_hw_constraint_list(substream->runtime, 0,
134	SNDRV_PCM_HW_PARAM_RATE,	134	SNDRV_PCM_HW_PARAM_RATE,
135	&constraints_48000);	135	&constraints_48000);
136	}	136	}
137		137
138	static struct snd_soc_ops byt_aif1_ops = {	138	static struct snd_soc_ops byt_aif1_ops = {
139	.startup = byt_aif1_startup,	139	.startup = byt_aif1_startup,
140	};	140	};
141		141
142	static struct snd_soc_ops byt_be_ssp2_ops = {	142	static struct snd_soc_ops byt_be_ssp2_ops = {
143	.hw_params = byt_aif1_hw_params,	143	.hw_params = byt_aif1_hw_params,
144	};	144	};
145		145
146	static struct snd_soc_dai_link byt_dailink[] = {	146	static struct snd_soc_dai_link byt_dailink[] = {
147	[MERR_DPCM_AUDIO] = {	147	[MERR_DPCM_AUDIO] = {
148	.name = "Baytrail Audio Port",	148	.name = "Baytrail Audio Port",
149	.stream_name = "Baytrail Audio",	149	.stream_name = "Baytrail Audio",
150	.cpu_dai_name = "media-cpu-dai",	150	.cpu_dai_name = "media-cpu-dai",
151	.codec_dai_name = "snd-soc-dummy-dai",	151	.codec_dai_name = "snd-soc-dummy-dai",
152	.codec_name = "snd-soc-dummy",	152	.codec_name = "snd-soc-dummy",
153	.platform_name = "sst-mfld-platform",	153	.platform_name = "sst-mfld-platform",
154	.ignore_suspend = 1,	154	.ignore_suspend = 1,
155	.dynamic = 1,	155	.dynamic = 1,
156	.dpcm_playback = 1,	156	.dpcm_playback = 1,
157	.dpcm_capture = 1,	157	.dpcm_capture = 1,
158	.ops = &byt_aif1_ops,	158	.ops = &byt_aif1_ops,
159	},	159	},
160	[MERR_DPCM_COMPR] = {	160	[MERR_DPCM_COMPR] = {
161	.name = "Baytrail Compressed Port",	161	.name = "Baytrail Compressed Port",
162	.stream_name = "Baytrail Compress",	162	.stream_name = "Baytrail Compress",
163	.cpu_dai_name = "compress-cpu-dai",	163	.cpu_dai_name = "compress-cpu-dai",
164	.codec_dai_name = "snd-soc-dummy-dai",	164	.codec_dai_name = "snd-soc-dummy-dai",
165	.codec_name = "snd-soc-dummy",	165	.codec_name = "snd-soc-dummy",
166	.platform_name = "sst-mfld-platform",	166	.platform_name = "sst-mfld-platform",
167	},	167	},
168	/* back ends */	168	/* back ends */
169	{	169	{
170	.name = "SSP2-Codec",	170	.name = "SSP2-Codec",
171	.be_id = 1,	171	.be_id = 1,
172	.cpu_dai_name = "ssp2-port",	172	.cpu_dai_name = "ssp2-port",
173	.platform_name = "sst-mfld-platform",	173	.platform_name = "sst-mfld-platform",
174	.no_pcm = 1,	174	.no_pcm = 1,
175	.codec_dai_name = "rt5640-aif1",	175	.codec_dai_name = "rt5640-aif1",
176	.codec_name = "i2c-10EC5640:00",	176	.codec_name = "i2c-10EC5640:00",
177	.dai_fmt = SND_SOC_DAIFMT_I2S \| SND_SOC_DAIFMT_NB_NF	177	.dai_fmt = SND_SOC_DAIFMT_I2S \| SND_SOC_DAIFMT_NB_NF
178	\| SND_SOC_DAIFMT_CBS_CFS,	178	\| SND_SOC_DAIFMT_CBS_CFS,
179	.be_hw_params_fixup = byt_codec_fixup,	179	.be_hw_params_fixup = byt_codec_fixup,
180	.ignore_suspend = 1,	180	.ignore_suspend = 1,
181	.dpcm_playback = 1,	181	.dpcm_playback = 1,
182	.dpcm_capture = 1,	182	.dpcm_capture = 1,
183	.ops = &byt_be_ssp2_ops,	183	.ops = &byt_be_ssp2_ops,
184	},	184	},
185	};	185	};
186		186
187	/* SoC card */	187	/* SoC card */
188	static struct snd_soc_card snd_soc_card_byt = {	188	static struct snd_soc_card snd_soc_card_byt = {
189	.name = "baytrailcraudio",	189	.name = "baytrailcraudio",
190	.dai_link = byt_dailink,	190	.dai_link = byt_dailink,
191	.num_links = ARRAY_SIZE(byt_dailink),	191	.num_links = ARRAY_SIZE(byt_dailink),
192	.dapm_widgets = byt_dapm_widgets,	192	.dapm_widgets = byt_dapm_widgets,
193	.num_dapm_widgets = ARRAY_SIZE(byt_dapm_widgets),	193	.num_dapm_widgets = ARRAY_SIZE(byt_dapm_widgets),
194	.dapm_routes = byt_audio_map,	194	.dapm_routes = byt_audio_map,
195	.num_dapm_routes = ARRAY_SIZE(byt_audio_map),	195	.num_dapm_routes = ARRAY_SIZE(byt_audio_map),
196	.controls = byt_mc_controls,	196	.controls = byt_mc_controls,
197	.num_controls = ARRAY_SIZE(byt_mc_controls),	197	.num_controls = ARRAY_SIZE(byt_mc_controls),
198	};	198	};
199		199
200	static int snd_byt_mc_probe(struct platform_device *pdev)	200	static int snd_byt_mc_probe(struct platform_device *pdev)
201	{	201	{
202	int ret_val = 0;	202	int ret_val = 0;
203		203
204	/* register the soc card */	204	/* register the soc card */
205	snd_soc_card_byt.dev = &pdev->dev;	205	snd_soc_card_byt.dev = &pdev->dev;
206		206
207	ret_val = devm_snd_soc_register_card(&pdev->dev, &snd_soc_card_byt);	207	ret_val = devm_snd_soc_register_card(&pdev->dev, &snd_soc_card_byt);
208	if (ret_val) {	208	if (ret_val) {
209	dev_err(&pdev->dev, "devm_snd_soc_register_card failed %d\n", ret_val);	209	dev_err(&pdev->dev, "devm_snd_soc_register_card failed %d\n", ret_val);
210	return ret_val;	210	return ret_val;
211	}	211	}
212	platform_set_drvdata(pdev, &snd_soc_card_byt);	212	platform_set_drvdata(pdev, &snd_soc_card_byt);
213	return ret_val;	213	return ret_val;
214	}	214	}
215		215
216	static struct platform_driver snd_byt_mc_driver = {	216	static struct platform_driver snd_byt_mc_driver = {
217	.driver = {	217	.driver = {
218	.owner = THIS_MODULE,	218	.owner = THIS_MODULE,
219	.name = "bytt100_rt5640",	219	.name = "bytt100_rt5640",
220	.pm = &snd_soc_pm_ops,	220	.pm = &snd_soc_pm_ops,
221	},	221	},
222	.probe = snd_byt_mc_probe,	222	.probe = snd_byt_mc_probe,
223	};	223	};
224		224
225	module_platform_driver(snd_byt_mc_driver);	225	module_platform_driver(snd_byt_mc_driver);
226		226
227	MODULE_DESCRIPTION("ASoC Intel(R) Baytrail CR Machine driver");	227	MODULE_DESCRIPTION("ASoC Intel(R) Baytrail CR Machine driver");
228	MODULE_AUTHOR("Subhransu S. Prusty <subhransu.s.prusty@intel.com>");	228	MODULE_AUTHOR("Subhransu S. Prusty <subhransu.s.prusty@intel.com>");
229	MODULE_LICENSE("GPL v2");	229	MODULE_LICENSE("GPL v2");
230	MODULE_ALIAS("platform:bytrt5640-audio");	230	MODULE_ALIAS("platform:bytt100_rt5640");
231		231

sound/soc/intel/sst-firmware.c

Diff comments View file @ e83ce4a

 /*
  * Intel SST Firmware Loader
  *
  * Copyright (C) 2013, Intel Corporation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License version
  * 2 as published by the Free Software Foundation.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  */
 #include <linux/kernel.h>
 #include <linux/slab.h>
 #include <linux/sched.h>
 #include <linux/firmware.h>
 #include <linux/export.h>
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/dmaengine.h>
 #include <linux/pci.h>
 #include <linux/acpi.h>
 /* supported DMA engine drivers */
 #include <linux/platform_data/dma-dw.h>
 #include <linux/dma/dw.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include "sst-dsp.h"
 #include "sst-dsp-priv.h"
 #define SST_DMA_RESOURCES	2
 #define SST_DSP_DMA_MAX_BURST	0x3
 #define SST_HSW_BLOCK_ANY	0xffffffff
 #define SST_HSW_MASK_DMA_ADDR_DSP 0xfff00000
 struct sst_dma {
 	struct sst_dsp *sst;
 	struct dw_dma_chip *chip;
 	struct dma_async_tx_descriptor *desc;
 	struct dma_chan *ch;
 };
 static inline void sst_memcpy32(volatile void __iomem *dest, void *src, u32 bytes)
 {
 	/* __iowrite32_copy use 32bit size values so divide by 4 */
 	__iowrite32_copy((void *)dest, src, bytes/4);
 }
 static void sst_dma_transfer_complete(void *arg)
 {
 	struct sst_dsp *sst = (struct sst_dsp *)arg;
 	dev_dbg(sst->dev, "DMA: callback\n");
 }
 static int sst_dsp_dma_copy(struct sst_dsp *sst, dma_addr_t dest_addr,
 	dma_addr_t src_addr, size_t size)
 {
 	struct dma_async_tx_descriptor *desc;
 	struct sst_dma *dma = sst->dma;
 	if (dma->ch == NULL) {
 		dev_err(sst->dev, "error: no DMA channel\n");
 		return -ENODEV;
 	}
 	dev_dbg(sst->dev, "DMA: src: 0x%lx dest 0x%lx size %zu\n",
 		(unsigned long)src_addr, (unsigned long)dest_addr, size);
 	desc = dma->ch->device->device_prep_dma_memcpy(dma->ch, dest_addr,
 		src_addr, size, DMA_CTRL_ACK);
 	if (!desc){
 		dev_err(sst->dev, "error: dma prep memcpy failed\n");
 		return -EINVAL;
 	}
 	desc->callback = sst_dma_transfer_complete;
 	desc->callback_param = sst;
 	desc->tx_submit(desc);
 	dma_wait_for_async_tx(desc);
 	return 0;
 }
 /* copy to DSP */
 int sst_dsp_dma_copyto(struct sst_dsp *sst, dma_addr_t dest_addr,
 	dma_addr_t src_addr, size_t size)
 {
 	return sst_dsp_dma_copy(sst, dest_addr | SST_HSW_MASK_DMA_ADDR_DSP,
 			src_addr, size);
 }
 EXPORT_SYMBOL_GPL(sst_dsp_dma_copyto);
 /* copy from DSP */
 int sst_dsp_dma_copyfrom(struct sst_dsp *sst, dma_addr_t dest_addr,
 	dma_addr_t src_addr, size_t size)
 {
 	return sst_dsp_dma_copy(sst, dest_addr,
 		src_addr | SST_HSW_MASK_DMA_ADDR_DSP, size);
 }
 EXPORT_SYMBOL_GPL(sst_dsp_dma_copyfrom);
 /* remove module from memory - callers hold locks */
 static void block_list_remove(struct sst_dsp *dsp,
 	struct list_head *block_list)
 {
 	struct sst_mem_block *block, *tmp;
 	int err;
 	/* disable each block  */
 	list_for_each_entry(block, block_list, module_list) {
 		if (block->ops && block->ops->disable) {
 			err = block->ops->disable(block);
 			if (err < 0)
 				dev_err(dsp->dev,
 					"error: cant disable block %d:%d\n",
 					block->type, block->index);
 		}
 	}
 	/* mark each block as free */
 	list_for_each_entry_safe(block, tmp, block_list, module_list) {
 		list_del(&block->module_list);
 		list_move(&block->list, &dsp->free_block_list);
 		dev_dbg(dsp->dev, "block freed %d:%d at offset 0x%x\n",
 			block->type, block->index, block->offset);
 	}
 }
 /* prepare the memory block to receive data from host - callers hold locks */
 static int block_list_prepare(struct sst_dsp *dsp,
 	struct list_head *block_list)
 {
 	struct sst_mem_block *block;
 	int ret = 0;
 	/* enable each block so that's it'e ready for data */
 	list_for_each_entry(block, block_list, module_list) {
 		if (block->ops && block->ops->enable && !block->users) {
 			ret = block->ops->enable(block);
 			if (ret < 0) {
 				dev_err(dsp->dev,
 					"error: cant disable block %d:%d\n",
 					block->type, block->index);
 				goto err;
 			}
 		}
 	}
 	return ret;
 err:
 	list_for_each_entry(block, block_list, module_list) {
 		if (block->ops && block->ops->disable)
 			block->ops->disable(block);
 	}
 	return ret;
 }
 static struct dw_dma_platform_data dw_pdata = {
 	.is_private = 1,
 	.chan_allocation_order = CHAN_ALLOCATION_ASCENDING,
 	.chan_priority = CHAN_PRIORITY_ASCENDING,
 };
 static struct dw_dma_chip *dw_probe(struct device *dev, struct resource *mem,
 	int irq)
 {
 	struct dw_dma_chip *chip;
 	int err;
 	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
 	if (!chip)
 		return ERR_PTR(-ENOMEM);
 	chip->irq = irq;
 	chip->regs = devm_ioremap_resource(dev, mem);
 	if (IS_ERR(chip->regs))
 		return ERR_CAST(chip->regs);
 	err = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(31));
 	if (err)
 		return ERR_PTR(err);
 	chip->dev = dev;
 	err = dw_dma_probe(chip, &dw_pdata);
 	if (err)
 		return ERR_PTR(err);
 	return chip;
 }
 static void dw_remove(struct dw_dma_chip *chip)
 {
 	dw_dma_remove(chip);
 }
 static bool dma_chan_filter(struct dma_chan *chan, void *param)
 {
 	struct sst_dsp *dsp = (struct sst_dsp *)param;
 	return chan->device->dev == dsp->dma_dev;
 }
 int sst_dsp_dma_get_channel(struct sst_dsp *dsp, int chan_id)
 {
 	struct sst_dma *dma = dsp->dma;
 	struct dma_slave_config slave;
 	dma_cap_mask_t mask;
 	int ret;
 	/* The Intel MID DMA engine driver needs the slave config set but
 	 * Synopsis DMA engine driver safely ignores the slave config */
 	dma_cap_zero(mask);
 	dma_cap_set(DMA_SLAVE, mask);
 	dma_cap_set(DMA_MEMCPY, mask);
 	dma->ch = dma_request_channel(mask, dma_chan_filter, dsp);
 	if (dma->ch == NULL) {
 		dev_err(dsp->dev, "error: DMA request channel failed\n");
 		return -EIO;
 	}
 	memset(&slave, 0, sizeof(slave));
 	slave.direction = DMA_MEM_TO_DEV;
 	slave.src_addr_width =
 		slave.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 	slave.src_maxburst = slave.dst_maxburst = SST_DSP_DMA_MAX_BURST;
 	ret = dmaengine_slave_config(dma->ch, &slave);
 	if (ret) {
 		dev_err(dsp->dev, "error: unable to set DMA slave config %d\n",
 			ret);
 		dma_release_channel(dma->ch);
 		dma->ch = NULL;
 	}
 	return ret;
 }
 EXPORT_SYMBOL_GPL(sst_dsp_dma_get_channel);
 void sst_dsp_dma_put_channel(struct sst_dsp *dsp)
 {
 	struct sst_dma *dma = dsp->dma;
 	if (!dma->ch)
 		return;
 	dma_release_channel(dma->ch);
 	dma->ch = NULL;
 }
 EXPORT_SYMBOL_GPL(sst_dsp_dma_put_channel);
 int sst_dma_new(struct sst_dsp *sst)
 {
 	struct sst_pdata *sst_pdata = sst->pdata;
 	struct sst_dma *dma;
 	struct resource mem;
 	const char *dma_dev_name;
 	int ret = 0;
 	/* configure the correct platform data for whatever DMA engine
 	* is attached to the ADSP IP. */
 	switch (sst->pdata->dma_engine) {
 	case SST_DMA_TYPE_DW:
 		dma_dev_name = "dw_dmac";
 		break;
 	case SST_DMA_TYPE_MID:
 		dma_dev_name = "Intel MID DMA";
 		break;
 	default:
 		dev_err(sst->dev, "error: invalid DMA engine %d\n",
 			sst->pdata->dma_engine);
 		return -EINVAL;
 	}
 	dma = devm_kzalloc(sst->dev, sizeof(struct sst_dma), GFP_KERNEL);
 	if (!dma)
 		return -ENOMEM;
 	dma->sst = sst;
 	memset(&mem, 0, sizeof(mem));
 	mem.start = sst->addr.lpe_base + sst_pdata->dma_base;
 	mem.end   = sst->addr.lpe_base + sst_pdata->dma_base + sst_pdata->dma_size - 1;
 	mem.flags = IORESOURCE_MEM;
 	/* now register DMA engine device */
 	dma->chip = dw_probe(sst->dma_dev, &mem, sst_pdata->irq);
 	if (IS_ERR(dma->chip)) {
 		dev_err(sst->dev, "error: DMA device register failed\n");
 		ret = PTR_ERR(dma->chip);
 		goto err_dma_dev;
 	}
 	sst->dma = dma;
 	sst->fw_use_dma = true;
 	return 0;
 err_dma_dev:
 	devm_kfree(sst->dev, dma);
 	return ret;
 }
 EXPORT_SYMBOL(sst_dma_new);
 void sst_dma_free(struct sst_dma *dma)
 {
 	if (dma == NULL)
 		return;
 	if (dma->ch)
 		dma_release_channel(dma->ch);
 	if (dma->chip)
 		dw_remove(dma->chip);
 }
 EXPORT_SYMBOL(sst_dma_free);
 /* create new generic firmware object */
 struct sst_fw *sst_fw_new(struct sst_dsp *dsp,
 	const struct firmware *fw, void *private)
 {
 	struct sst_fw *sst_fw;
 	int err;
 	if (!dsp->ops->parse_fw)
 		return NULL;
 	sst_fw = kzalloc(sizeof(*sst_fw), GFP_KERNEL);
 	if (sst_fw == NULL)
 		return NULL;
 	sst_fw->dsp = dsp;
 	sst_fw->private = private;
 	sst_fw->size = fw->size;
 	/* allocate DMA buffer to store FW data */
 	sst_fw->dma_buf = dma_alloc_coherent(dsp->dma_dev, sst_fw->size,
 				&sst_fw->dmable_fw_paddr, GFP_DMA | GFP_KERNEL);
 	if (!sst_fw->dma_buf) {
 		dev_err(dsp->dev, "error: DMA alloc failed\n");
 		kfree(sst_fw);
 		return NULL;
 	}
 	/* copy FW data to DMA-able memory */
 	memcpy((void *)sst_fw->dma_buf, (void *)fw->data, fw->size);
 	if (dsp->fw_use_dma) {
 		err = sst_dsp_dma_get_channel(dsp, 0);
 		if (err < 0)
 			goto chan_err;
 	}
 	/* call core specific FW paser to load FW data into DSP */
 	err = dsp->ops->parse_fw(sst_fw);
 	if (err < 0) {
 		dev_err(dsp->dev, "error: parse fw failed %d\n", err);
 		goto parse_err;
 	}
 	if (dsp->fw_use_dma)
 		sst_dsp_dma_put_channel(dsp);
 	mutex_lock(&dsp->mutex);
 	list_add(&sst_fw->list, &dsp->fw_list);
 	mutex_unlock(&dsp->mutex);
 	return sst_fw;
 parse_err:
 	if (dsp->fw_use_dma)
 		sst_dsp_dma_put_channel(dsp);
 chan_err:
 	dma_free_coherent(dsp->dma_dev, sst_fw->size,
 				sst_fw->dma_buf,
 				sst_fw->dmable_fw_paddr);
 	sst_fw->dma_buf = NULL;
 	kfree(sst_fw);
 	return NULL;
 }
 EXPORT_SYMBOL_GPL(sst_fw_new);
 int sst_fw_reload(struct sst_fw *sst_fw)
 {
 	struct sst_dsp *dsp = sst_fw->dsp;
 	int ret;
 	dev_dbg(dsp->dev, "reloading firmware\n");
 	/* call core specific FW paser to load FW data into DSP */
 	ret = dsp->ops->parse_fw(sst_fw);
 	if (ret < 0)
 		dev_err(dsp->dev, "error: parse fw failed %d\n", ret);
 	return ret;
 }
 EXPORT_SYMBOL_GPL(sst_fw_reload);
 void sst_fw_unload(struct sst_fw *sst_fw)
 {
 	struct sst_dsp *dsp = sst_fw->dsp;
 	struct sst_module *module, *mtmp;
 	struct sst_module_runtime *runtime, *rtmp;
 	dev_dbg(dsp->dev, "unloading firmware\n");
 	mutex_lock(&dsp->mutex);
 	/* check module by module */
 	list_for_each_entry_safe(module, mtmp, &dsp->module_list, list) {
 		if (module->sst_fw == sst_fw) {
 			/* remove runtime modules */
 			list_for_each_entry_safe(runtime, rtmp, &module->runtime_list, list) {
 				block_list_remove(dsp, &runtime->block_list);
 				list_del(&runtime->list);
 				kfree(runtime);
 			}
 			/* now remove the module */
 			block_list_remove(dsp, &module->block_list);
 			list_del(&module->list);
 			kfree(module);
 		}
 	}
 	/* remove all scratch blocks */
 	block_list_remove(dsp, &dsp->scratch_block_list);
 	mutex_unlock(&dsp->mutex);
 }
 EXPORT_SYMBOL_GPL(sst_fw_unload);
 /* free single firmware object */
 void sst_fw_free(struct sst_fw *sst_fw)
 {
 	struct sst_dsp *dsp = sst_fw->dsp;
 	mutex_lock(&dsp->mutex);
 	list_del(&sst_fw->list);
 	mutex_unlock(&dsp->mutex);
 	if (sst_fw->dma_buf)
 		dma_free_coherent(dsp->dma_dev, sst_fw->size, sst_fw->dma_buf,
 			sst_fw->dmable_fw_paddr);
 	kfree(sst_fw);
 }
 EXPORT_SYMBOL_GPL(sst_fw_free);
 /* free all firmware objects */
 void sst_fw_free_all(struct sst_dsp *dsp)
 {
 	struct sst_fw *sst_fw, *t;
 	mutex_lock(&dsp->mutex);
 	list_for_each_entry_safe(sst_fw, t, &dsp->fw_list, list) {
 		list_del(&sst_fw->list);
 		dma_free_coherent(dsp->dev, sst_fw->size, sst_fw->dma_buf,
 			sst_fw->dmable_fw_paddr);
 		kfree(sst_fw);
 	}
 	mutex_unlock(&dsp->mutex);
 }
 EXPORT_SYMBOL_GPL(sst_fw_free_all);
 /* create a new SST generic module from FW template */
 struct sst_module *sst_module_new(struct sst_fw *sst_fw,
 	struct sst_module_template *template, void *private)
 {
 	struct sst_dsp *dsp = sst_fw->dsp;
 	struct sst_module *sst_module;
 	sst_module = kzalloc(sizeof(*sst_module), GFP_KERNEL);
 	if (sst_module == NULL)
 		return NULL;
 	sst_module->id = template->id;
 	sst_module->dsp = dsp;
 	sst_module->sst_fw = sst_fw;
 	sst_module->scratch_size = template->scratch_size;
 	sst_module->persistent_size = template->persistent_size;
 	INIT_LIST_HEAD(&sst_module->block_list);
 	INIT_LIST_HEAD(&sst_module->runtime_list);
 	mutex_lock(&dsp->mutex);
 	list_add(&sst_module->list, &dsp->module_list);
 	mutex_unlock(&dsp->mutex);
 	return sst_module;
 }
 EXPORT_SYMBOL_GPL(sst_module_new);
 /* free firmware module and remove from available list */
 void sst_module_free(struct sst_module *sst_module)
 {
 	struct sst_dsp *dsp = sst_module->dsp;
 	mutex_lock(&dsp->mutex);
 	list_del(&sst_module->list);
 	mutex_unlock(&dsp->mutex);
 	kfree(sst_module);
 }
 EXPORT_SYMBOL_GPL(sst_module_free);
 struct sst_module_runtime *sst_module_runtime_new(struct sst_module *module,
 	int id, void *private)
 {
 	struct sst_dsp *dsp = module->dsp;
 	struct sst_module_runtime *runtime;
 	runtime = kzalloc(sizeof(*runtime), GFP_KERNEL);
 	if (runtime == NULL)
 		return NULL;
 	runtime->id = id;
 	runtime->dsp = dsp;
 	runtime->module = module;
 	INIT_LIST_HEAD(&runtime->block_list);
 	mutex_lock(&dsp->mutex);
 	list_add(&runtime->list, &module->runtime_list);
 	mutex_unlock(&dsp->mutex);
 	return runtime;
 }
 EXPORT_SYMBOL_GPL(sst_module_runtime_new);
 void sst_module_runtime_free(struct sst_module_runtime *runtime)
 {
 	struct sst_dsp *dsp = runtime->dsp;
 	mutex_lock(&dsp->mutex);
 	list_del(&runtime->list);
 	mutex_unlock(&dsp->mutex);
 	kfree(runtime);
 }
 EXPORT_SYMBOL_GPL(sst_module_runtime_free);
 static struct sst_mem_block *find_block(struct sst_dsp *dsp,
 	struct sst_block_allocator *ba)
 {
 	struct sst_mem_block *block;
 	list_for_each_entry(block, &dsp->free_block_list, list) {
 		if (block->type == ba->type && block->offset == ba->offset)
 			return block;
 	}
 	return NULL;
 }
 /* Block allocator must be on block boundary */
 static int block_alloc_contiguous(struct sst_dsp *dsp,
 	struct sst_block_allocator *ba, struct list_head *block_list)
 {
 	struct list_head tmp = LIST_HEAD_INIT(tmp);
 	struct sst_mem_block *block;
 	u32 block_start = SST_HSW_BLOCK_ANY;
 	int size = ba->size, offset = ba->offset;
 	while (ba->size > 0) {
 		block = find_block(dsp, ba);
 		if (!block) {
 			list_splice(&tmp, &dsp->free_block_list);
 			ba->size = size;
 			ba->offset = offset;
 			return -ENOMEM;
 		}
 		list_move_tail(&block->list, &tmp);
 		ba->offset += block->size;
 		ba->size -= block->size;
 	}
 	ba->size = size;
 	ba->offset = offset;
 	list_for_each_entry(block, &tmp, list) {
 		if (block->offset < block_start)
 			block_start = block->offset;
 		list_add(&block->module_list, block_list);
 		dev_dbg(dsp->dev, "block allocated %d:%d at offset 0x%x\n",
 			block->type, block->index, block->offset);
 	}
 	list_splice(&tmp, &dsp->used_block_list);
 	return 0;
 }
 /* allocate first free DSP blocks for data - callers hold locks */
 static int block_alloc(struct sst_dsp *dsp, struct sst_block_allocator *ba,
 	struct list_head *block_list)
 {
 	struct sst_mem_block *block, *tmp;
 	int ret = 0;
 	if (ba->size == 0)
 		return 0;
 	/* find first free whole blocks that can hold module */
 	list_for_each_entry_safe(block, tmp, &dsp->free_block_list, list) {
 		/* ignore blocks with wrong type */
 		if (block->type != ba->type)
 			continue;
 		if (ba->size > block->size)
 			continue;
 		ba->offset = block->offset;
 		block->bytes_used = ba->size % block->size;
 		list_add(&block->module_list, block_list);
 		list_move(&block->list, &dsp->used_block_list);
 		dev_dbg(dsp->dev, "block allocated %d:%d at offset 0x%x\n",
 			block->type, block->index, block->offset);
 		return 0;
 	}
 	/* then find free multiple blocks that can hold module */
 	list_for_each_entry_safe(block, tmp, &dsp->free_block_list, list) {
 		/* ignore blocks with wrong type */
 		if (block->type != ba->type)
 			continue;
 		/* do we span > 1 blocks */
 		if (ba->size > block->size) {
 			/* align ba to block boundary */
 			ba->offset = block->offset;
 			ret = block_alloc_contiguous(dsp, ba, block_list);
 			if (ret == 0)
 				return ret;
 		}
 	}
 	/* not enough free block space */
 	return -ENOMEM;
 }
 int sst_alloc_blocks(struct sst_dsp *dsp, struct sst_block_allocator *ba,
 	struct list_head *block_list)
 {
 	int ret;
 	dev_dbg(dsp->dev, "block request 0x%x bytes at offset 0x%x type %d\n",
 		ba->size, ba->offset, ba->type);
 	mutex_lock(&dsp->mutex);
 	ret = block_alloc(dsp, ba, block_list);
 	if (ret < 0) {
 		dev_err(dsp->dev, "error: can't alloc blocks %d\n", ret);
 		goto out;
 	}
 	/* prepare DSP blocks for module usage */
 	ret = block_list_prepare(dsp, block_list);
 	if (ret < 0)
 		dev_err(dsp->dev, "error: prepare failed\n");
 out:
 	mutex_unlock(&dsp->mutex);
 	return ret;
 }
 EXPORT_SYMBOL_GPL(sst_alloc_blocks);
 int sst_free_blocks(struct sst_dsp *dsp, struct list_head *block_list)
 {
 	mutex_lock(&dsp->mutex);
 	block_list_remove(dsp, block_list);
 	mutex_unlock(&dsp->mutex);
 	return 0;
 }
 EXPORT_SYMBOL_GPL(sst_free_blocks);
 /* allocate memory blocks for static module addresses - callers hold locks */
 static int block_alloc_fixed(struct sst_dsp *dsp, struct sst_block_allocator *ba,
 	struct list_head *block_list)
 {
 	struct sst_mem_block *block, *tmp;
 	u32 end = ba->offset + ba->size, block_end;
 	int err;
 	/* only IRAM/DRAM blocks are managed */
 	if (ba->type != SST_MEM_IRAM && ba->type != SST_MEM_DRAM)
 		return 0;
 	/* are blocks already attached to this module */
 	list_for_each_entry_safe(block, tmp, block_list, module_list) {
 		/* ignore blocks with wrong type */
 		if (block->type != ba->type)
 			continue;
 		block_end = block->offset + block->size;
 		/* find block that holds section */
 		if (ba->offset >= block->offset && end <= block_end)
 			return 0;
 		/* does block span more than 1 section */
 		if (ba->offset >= block->offset && ba->offset < block_end) {
 			/* align ba to block boundary */
 			ba->size -= block_end - ba->offset;
 			ba->offset = block_end;
 			err = block_alloc_contiguous(dsp, ba, block_list);
 			if (err < 0)
 				return -ENOMEM;
 			/* module already owns blocks */
 			return 0;
 		}
 	}
 	/* find first free blocks that can hold section in free list */
 	list_for_each_entry_safe(block, tmp, &dsp->free_block_list, list) {
 		block_end = block->offset + block->size;
 		/* ignore blocks with wrong type */
 		if (block->type != ba->type)
 			continue;
 		/* find block that holds section */
 		if (ba->offset >= block->offset && end <= block_end) {
 			/* add block */
 			list_move(&block->list, &dsp->used_block_list);
 			list_add(&block->module_list, block_list);
 			dev_dbg(dsp->dev, "block allocated %d:%d at offset 0x%x\n",
 				block->type, block->index, block->offset);
 			return 0;
 		}
 		/* does block span more than 1 section */
 		if (ba->offset >= block->offset && ba->offset < block_end) {
+			/* add block */
+			list_move(&block->list, &dsp->used_block_list);
+			list_add(&block->module_list, block_list);
 			/* align ba to block boundary */
-			ba->offset = block->offset;
+			ba->size -= block_end - ba->offset;
+			ba->offset = block_end;
 			err = block_alloc_contiguous(dsp, ba, block_list);
 			if (err < 0)
 				return -ENOMEM;
 			return 0;
 		}
 	}
 	return -ENOMEM;
 }
 /* Load fixed module data into DSP memory blocks */
 int sst_module_alloc_blocks(struct sst_module *module)
 {
 	struct sst_dsp *dsp = module->dsp;
 	struct sst_fw *sst_fw = module->sst_fw;
 	struct sst_block_allocator ba;
 	int ret;
 	ba.size = module->size;
 	ba.type = module->type;
 	ba.offset = module->offset;
 	dev_dbg(dsp->dev, "block request 0x%x bytes at offset 0x%x type %d\n",
 		ba.size, ba.offset, ba.type);
 	mutex_lock(&dsp->mutex);
 	/* alloc blocks that includes this section */
 	ret = block_alloc_fixed(dsp, &ba, &module->block_list);
 	if (ret < 0) {
 		dev_err(dsp->dev,
 			"error: no free blocks for section at offset 0x%x size 0x%x\n",
 			module->offset, module->size);
 		mutex_unlock(&dsp->mutex);
 		return -ENOMEM;
 	}
 	/* prepare DSP blocks for module copy */
 	ret = block_list_prepare(dsp, &module->block_list);
 	if (ret < 0) {
 		dev_err(dsp->dev, "error: fw module prepare failed\n");
 		goto err;
 	}
 	/* copy partial module data to blocks */
 	if (dsp->fw_use_dma) {
 		ret = sst_dsp_dma_copyto(dsp,
 			dsp->addr.lpe_base + module->offset,
 			sst_fw->dmable_fw_paddr + module->data_offset,
 			module->size);
 		if (ret < 0) {
 			dev_err(dsp->dev, "error: module copy failed\n");
 			goto err;
 		}
 	} else
 		sst_memcpy32(dsp->addr.lpe + module->offset, module->data,
 			module->size);
 	mutex_unlock(&dsp->mutex);
 	return ret;
 err:
 	block_list_remove(dsp, &module->block_list);
 	mutex_unlock(&dsp->mutex);
 	return ret;
 }
 EXPORT_SYMBOL_GPL(sst_module_alloc_blocks);
 /* Unload entire module from DSP memory */
 int sst_module_free_blocks(struct sst_module *module)
 {
 	struct sst_dsp *dsp = module->dsp;
 	mutex_lock(&dsp->mutex);
 	block_list_remove(dsp, &module->block_list);
 	mutex_unlock(&dsp->mutex);
 	return 0;
 }
 EXPORT_SYMBOL_GPL(sst_module_free_blocks);
 int sst_module_runtime_alloc_blocks(struct sst_module_runtime *runtime,
 	int offset)
 {
 	struct sst_dsp *dsp = runtime->dsp;
 	struct sst_module *module = runtime->module;
 	struct sst_block_allocator ba;
 	int ret;
 	if (module->persistent_size == 0)
 		return 0;
 	ba.size = module->persistent_size;
 	ba.type = SST_MEM_DRAM;
 	mutex_lock(&dsp->mutex);
 	/* do we need to allocate at a fixed address ? */
 	if (offset != 0) {
 		ba.offset = offset;
 		dev_dbg(dsp->dev, "persistent fixed block request 0x%x bytes type %d offset 0x%x\n",
 			ba.size, ba.type, ba.offset);
 		/* alloc blocks that includes this section */
 		ret = block_alloc_fixed(dsp, &ba, &runtime->block_list);
 	} else {
 		dev_dbg(dsp->dev, "persistent block request 0x%x bytes type %d\n",
 			ba.size, ba.type);
 		/* alloc blocks that includes this section */
 		ret = block_alloc(dsp, &ba, &runtime->block_list);
 	}
 	if (ret < 0) {
 		dev_err(dsp->dev,
 		"error: no free blocks for runtime module size 0x%x\n",
 			module->persistent_size);
 		mutex_unlock(&dsp->mutex);
 		return -ENOMEM;
 	}
 	runtime->persistent_offset = ba.offset;
 	/* prepare DSP blocks for module copy */
 	ret = block_list_prepare(dsp, &runtime->block_list);
 	if (ret < 0) {
 		dev_err(dsp->dev, "error: runtime block prepare failed\n");
 		goto err;
 	}
 	mutex_unlock(&dsp->mutex);
 	return ret;
 err:
 	block_list_remove(dsp, &module->block_list);
 	mutex_unlock(&dsp->mutex);
 	return ret;
 }
 EXPORT_SYMBOL_GPL(sst_module_runtime_alloc_blocks);
 int sst_module_runtime_free_blocks(struct sst_module_runtime *runtime)
 {
 	struct sst_dsp *dsp = runtime->dsp;
 	mutex_lock(&dsp->mutex);
 	block_list_remove(dsp, &runtime->block_list);
 	mutex_unlock(&dsp->mutex);
 	return 0;
 }
 EXPORT_SYMBOL_GPL(sst_module_runtime_free_blocks);
 int sst_module_runtime_save(struct sst_module_runtime *runtime,
 	struct sst_module_runtime_context *context)
 {
 	struct sst_dsp *dsp = runtime->dsp;
 	struct sst_module *module = runtime->module;
 	int ret = 0;
 	dev_dbg(dsp->dev, "saving runtime %d memory at 0x%x size 0x%x\n",
 		runtime->id, runtime->persistent_offset,
 		module->persistent_size);
 	context->buffer = dma_alloc_coherent(dsp->dma_dev,
 		module->persistent_size,
 		&context->dma_buffer, GFP_DMA | GFP_KERNEL);
 	if (!context->buffer) {
 		dev_err(dsp->dev, "error: DMA context alloc failed\n");
 		return -ENOMEM;
 	}
 	mutex_lock(&dsp->mutex);
 	if (dsp->fw_use_dma) {
 		ret = sst_dsp_dma_get_channel(dsp, 0);
 		if (ret < 0)
 			goto err;
 		ret = sst_dsp_dma_copyfrom(dsp, context->dma_buffer,
 			dsp->addr.lpe_base + runtime->persistent_offset,
 			module->persistent_size);
 		sst_dsp_dma_put_channel(dsp);
 		if (ret < 0) {
 			dev_err(dsp->dev, "error: context copy failed\n");
 			goto err;
 		}
 	} else
 		sst_memcpy32(context->buffer, dsp->addr.lpe +
 			runtime->persistent_offset,
 			module->persistent_size);
 err:
 	mutex_unlock(&dsp->mutex);
 	return ret;
 }
 EXPORT_SYMBOL_GPL(sst_module_runtime_save);
 int sst_module_runtime_restore(struct sst_module_runtime *runtime,
 	struct sst_module_runtime_context *context)
 {
 	struct sst_dsp *dsp = runtime->dsp;
 	struct sst_module *module = runtime->module;
 	int ret = 0;
 	dev_dbg(dsp->dev, "restoring runtime %d memory at 0x%x size 0x%x\n",
 		runtime->id, runtime->persistent_offset,
 		module->persistent_size);
 	mutex_lock(&dsp->mutex);
 	if (!context->buffer) {
 		dev_info(dsp->dev, "no context buffer need to restore!\n");
 		goto err;
 	}
 	if (dsp->fw_use_dma) {
 		ret = sst_dsp_dma_get_channel(dsp, 0);
 		if (ret < 0)
 			goto err;
 		ret = sst_dsp_dma_copyto(dsp,
 			dsp->addr.lpe_base + runtime->persistent_offset,
 			context->dma_buffer, module->persistent_size);
 		sst_dsp_dma_put_channel(dsp);
 		if (ret < 0) {
 			dev_err(dsp->dev, "error: module copy failed\n");
 			goto err;
 		}
 	} else
 		sst_memcpy32(dsp->addr.lpe + runtime->persistent_offset,
 			context->buffer, module->persistent_size);
 	dma_free_coherent(dsp->dma_dev, module->persistent_size,
 				context->buffer, context->dma_buffer);
 	context->buffer = NULL;
 err:
 	mutex_unlock(&dsp->mutex);
 	return ret;
 }
 EXPORT_SYMBOL_GPL(sst_module_runtime_restore);
 /* register a DSP memory block for use with FW based modules */
 struct sst_mem_block *sst_mem_block_register(struct sst_dsp *dsp, u32 offset,
 	u32 size, enum sst_mem_type type, struct sst_block_ops *ops, u32 index,
 	void *private)
 {
 	struct sst_mem_block *block;
 	block = kzalloc(sizeof(*block), GFP_KERNEL);
 	if (block == NULL)
 		return NULL;
 	block->offset = offset;
 	block->size = size;
 	block->index = index;
 	block->type = type;
 	block->dsp = dsp;
 	block->private = private;
 	block->ops = ops;
 	mutex_lock(&dsp->mutex);
 	list_add(&block->list, &dsp->free_block_list);
 	mutex_unlock(&dsp->mutex);
 	return block;
 }
 EXPORT_SYMBOL_GPL(sst_mem_block_register);
 /* unregister all DSP memory blocks */
 void sst_mem_block_unregister_all(struct sst_dsp *dsp)
 {
 	struct sst_mem_block *block, *tmp;
 	mutex_lock(&dsp->mutex);
 	/* unregister used blocks */
 	list_for_each_entry_safe(block, tmp, &dsp->used_block_list, list) {
 		list_del(&block->list);
 		kfree(block);
 	}
 	/* unregister free blocks */
 	list_for_each_entry_safe(block, tmp, &dsp->free_block_list, list) {
 		list_del(&block->list);
 		kfree(block);
 	}
 	mutex_unlock(&dsp->mutex);
 }
 EXPORT_SYMBOL_GPL(sst_mem_block_unregister_all);
 /* allocate scratch buffer blocks */
 int sst_block_alloc_scratch(struct sst_dsp *dsp)
 {
 	struct sst_module *module;
 	struct sst_block_allocator ba;
 	int ret;
 	mutex_lock(&dsp->mutex);
 	/* calculate required scratch size */
 	dsp->scratch_size = 0;
 	list_for_each_entry(module, &dsp->module_list, list) {
 		dev_dbg(dsp->dev, "module %d scratch req 0x%x bytes\n",
 			module->id, module->scratch_size);
 		if (dsp->scratch_size < module->scratch_size)
 			dsp->scratch_size = module->scratch_size;
 	}
 	dev_dbg(dsp->dev, "scratch buffer required is 0x%x bytes\n",
 		dsp->scratch_size);
 	if (dsp->scratch_size == 0) {
 		dev_info(dsp->dev, "no modules need scratch buffer\n");
 		mutex_unlock(&dsp->mutex);
 		return 0;
 	}
 	/* allocate blocks for module scratch buffers */
 	dev_dbg(dsp->dev, "allocating scratch blocks\n");
 	ba.size = dsp->scratch_size;
 	ba.type = SST_MEM_DRAM;
 	/* do we need to allocate at fixed offset */
 	if (dsp->scratch_offset != 0) {
 		dev_dbg(dsp->dev, "block request 0x%x bytes type %d at 0x%x\n",
 			ba.size, ba.type, ba.offset);
 		ba.offset = dsp->scratch_offset;
 		/* alloc blocks that includes this section */
 		ret = block_alloc_fixed(dsp, &ba, &dsp->scratch_block_list);
 	} else {
 		dev_dbg(dsp->dev, "block request 0x%x bytes type %d\n",
 			ba.size, ba.type);
 		ba.offset = 0;
 		ret = block_alloc(dsp, &ba, &dsp->scratch_block_list);
 	}
 	if (ret < 0) {
 		dev_err(dsp->dev, "error: can't alloc scratch blocks\n");
 		mutex_unlock(&dsp->mutex);
 		return ret;
 	}
 	ret = block_list_prepare(dsp, &dsp->scratch_block_list);
 	if (ret < 0) {
 		dev_err(dsp->dev, "error: scratch block prepare failed\n");
 		mutex_unlock(&dsp->mutex);
 		return ret;
 	}
 	/* assign the same offset of scratch to each module */
 	dsp->scratch_offset = ba.offset;
 	mutex_unlock(&dsp->mutex);
 	return dsp->scratch_size;
 }
 EXPORT_SYMBOL_GPL(sst_block_alloc_scratch);
 /* free all scratch blocks */
 void sst_block_free_scratch(struct sst_dsp *dsp)
 {
 	mutex_lock(&dsp->mutex);
 	block_list_remove(dsp, &dsp->scratch_block_list);
 	mutex_unlock(&dsp->mutex);
 }
 EXPORT_SYMBOL_GPL(sst_block_free_scratch);
 /* get a module from it's unique ID */
 struct sst_module *sst_module_get_from_id(struct sst_dsp *dsp, u32 id)
 {
 	struct sst_module *module;
 	mutex_lock(&dsp->mutex);
 	list_for_each_entry(module, &dsp->module_list, list) {
 		if (module->id == id) {
 			mutex_unlock(&dsp->mutex);
 			return module;
 		}
 	}
 	mutex_unlock(&dsp->mutex);
 	return NULL;
 }
 EXPORT_SYMBOL_GPL(sst_module_get_from_id);
 struct sst_module_runtime *sst_module_runtime_get_from_id(
 	struct sst_module *module, u32 id)
 {
 	struct sst_module_runtime *runtime;
 	struct sst_dsp *dsp = module->dsp;
 	mutex_lock(&dsp->mutex);
 	list_for_each_entry(runtime, &module->runtime_list, list) {
 		if (runtime->id == id) {
 			mutex_unlock(&dsp->mutex);
 			return runtime;
 		}
 	}
 	mutex_unlock(&dsp->mutex);
 	return NULL;
 }
 EXPORT_SYMBOL_GPL(sst_module_runtime_get_from_id);
 /* returns block address in DSP address space */
 u32 sst_dsp_get_offset(struct sst_dsp *dsp, u32 offset,
 	enum sst_mem_type type)
 {
 	switch (type) {
 	case SST_MEM_IRAM:
 		return offset - dsp->addr.iram_offset +
 			dsp->addr.dsp_iram_offset;
 	case SST_MEM_DRAM:
 		return offset - dsp->addr.dram_offset +
 			dsp->addr.dsp_dram_offset;
 	default:
 		return 0;
 	}
 }
 EXPORT_SYMBOL_GPL(sst_dsp_get_offset);

sound/soc/intel/sst/sst_acpi.c

Diff comments View file @ e83ce4a

1	/*	1	/*
2	* sst_acpi.c - SST (LPE) driver init file for ACPI enumeration.	2	* sst_acpi.c - SST (LPE) driver init file for ACPI enumeration.
3	*	3	*
4	* Copyright (c) 2013, Intel Corporation.	4	* Copyright (c) 2013, Intel Corporation.
5	*	5	*
6	* Authors: Ramesh Babu K V <Ramesh.Babu@intel.com>	6	* Authors: Ramesh Babu K V <Ramesh.Babu@intel.com>
7	* Authors: Omair Mohammed Abdullah <omair.m.abdullah@intel.com>	7	* Authors: Omair Mohammed Abdullah <omair.m.abdullah@intel.com>
8	*	8	*
9	* This program is free software; you can redistribute it and/or modify it	9	* This program is free software; you can redistribute it and/or modify it
10	* under the terms and conditions of the GNU General Public License,	10	* under the terms and conditions of the GNU General Public License,
11	* version 2, as published by the Free Software Foundation.	11	* version 2, as published by the Free Software Foundation.
12	*	12	*
13	* This program is distributed in the hope it will be useful, but WITHOUT	13	* This program is distributed in the hope it will be useful, but WITHOUT
14	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or	14	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for	15	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16	* more details.	16	* more details.
17	*	17	*
18	*	18	*
19	*/	19	*/
20		20
21	#include <linux/module.h>	21	#include <linux/module.h>
22	#include <linux/fs.h>	22	#include <linux/fs.h>
23	#include <linux/interrupt.h>	23	#include <linux/interrupt.h>
24	#include <linux/slab.h>	24	#include <linux/slab.h>
25	#include <linux/io.h>	25	#include <linux/io.h>
26	#include <linux/miscdevice.h>	26	#include <linux/miscdevice.h>
27	#include <linux/platform_device.h>	27	#include <linux/platform_device.h>
28	#include <linux/firmware.h>	28	#include <linux/firmware.h>
29	#include <linux/pm_runtime.h>	29	#include <linux/pm_runtime.h>
30	#include <linux/pm_qos.h>	30	#include <linux/pm_qos.h>
31	#include <linux/acpi.h>	31	#include <linux/acpi.h>
32	#include <asm/platform_sst_audio.h>	32	#include <asm/platform_sst_audio.h>
33	#include <sound/core.h>	33	#include <sound/core.h>
34	#include <sound/soc.h>	34	#include <sound/soc.h>
35	#include <sound/compress_driver.h>	35	#include <sound/compress_driver.h>
36	#include <acpi/acbuffer.h>	36	#include <acpi/acbuffer.h>
37	#include <acpi/platform/acenv.h>	37	#include <acpi/platform/acenv.h>
38	#include <acpi/platform/aclinux.h>	38	#include <acpi/platform/aclinux.h>
39	#include <acpi/actypes.h>	39	#include <acpi/actypes.h>
40	#include <acpi/acpi_bus.h>	40	#include <acpi/acpi_bus.h>
41	#include "../sst-mfld-platform.h"	41	#include "../sst-mfld-platform.h"
42	#include "../sst-dsp.h"	42	#include "../sst-dsp.h"
43	#include "sst.h"	43	#include "sst.h"
44		44
45	struct sst_machines {	45	struct sst_machines {
46	char *codec_id;	46	char *codec_id;
47	char board[32];	47	char board[32];
48	char machine[32];	48	char machine[32];
49	void (*machine_quirk)(void);	49	void (*machine_quirk)(void);
50	char firmware[32];	50	char firmware[32];
51	struct sst_platform_info *pdata;	51	struct sst_platform_info *pdata;
52		52
53	};	53	};
54		54
55	/* LPE viewpoint addresses */	55	/* LPE viewpoint addresses */
56	#define SST_BYT_IRAM_PHY_START 0xff2c0000	56	#define SST_BYT_IRAM_PHY_START 0xff2c0000
57	#define SST_BYT_IRAM_PHY_END 0xff2d4000	57	#define SST_BYT_IRAM_PHY_END 0xff2d4000
58	#define SST_BYT_DRAM_PHY_START 0xff300000	58	#define SST_BYT_DRAM_PHY_START 0xff300000
59	#define SST_BYT_DRAM_PHY_END 0xff320000	59	#define SST_BYT_DRAM_PHY_END 0xff320000
60	#define SST_BYT_IMR_VIRT_START 0xc0000000 /* virtual addr in LPE */	60	#define SST_BYT_IMR_VIRT_START 0xc0000000 /* virtual addr in LPE */
61	#define SST_BYT_IMR_VIRT_END 0xc01fffff	61	#define SST_BYT_IMR_VIRT_END 0xc01fffff
62	#define SST_BYT_SHIM_PHY_ADDR 0xff340000	62	#define SST_BYT_SHIM_PHY_ADDR 0xff340000
63	#define SST_BYT_MBOX_PHY_ADDR 0xff344000	63	#define SST_BYT_MBOX_PHY_ADDR 0xff344000
64	#define SST_BYT_DMA0_PHY_ADDR 0xff298000	64	#define SST_BYT_DMA0_PHY_ADDR 0xff298000
65	#define SST_BYT_DMA1_PHY_ADDR 0xff29c000	65	#define SST_BYT_DMA1_PHY_ADDR 0xff29c000
66	#define SST_BYT_SSP0_PHY_ADDR 0xff2a0000	66	#define SST_BYT_SSP0_PHY_ADDR 0xff2a0000
67	#define SST_BYT_SSP2_PHY_ADDR 0xff2a2000	67	#define SST_BYT_SSP2_PHY_ADDR 0xff2a2000
68		68
69	#define BYT_FW_MOD_TABLE_OFFSET 0x80000	69	#define BYT_FW_MOD_TABLE_OFFSET 0x80000
70	#define BYT_FW_MOD_TABLE_SIZE 0x100	70	#define BYT_FW_MOD_TABLE_SIZE 0x100
71	#define BYT_FW_MOD_OFFSET (BYT_FW_MOD_TABLE_OFFSET + BYT_FW_MOD_TABLE_SIZE)	71	#define BYT_FW_MOD_OFFSET (BYT_FW_MOD_TABLE_OFFSET + BYT_FW_MOD_TABLE_SIZE)
72		72
73	static const struct sst_info byt_fwparse_info = {	73	static const struct sst_info byt_fwparse_info = {
74	.use_elf = false,	74	.use_elf = false,
75	.max_streams = 25,	75	.max_streams = 25,
76	.iram_start = SST_BYT_IRAM_PHY_START,	76	.iram_start = SST_BYT_IRAM_PHY_START,
77	.iram_end = SST_BYT_IRAM_PHY_END,	77	.iram_end = SST_BYT_IRAM_PHY_END,
78	.iram_use = true,	78	.iram_use = true,
79	.dram_start = SST_BYT_DRAM_PHY_START,	79	.dram_start = SST_BYT_DRAM_PHY_START,
80	.dram_end = SST_BYT_DRAM_PHY_END,	80	.dram_end = SST_BYT_DRAM_PHY_END,
81	.dram_use = true,	81	.dram_use = true,
82	.imr_start = SST_BYT_IMR_VIRT_START,	82	.imr_start = SST_BYT_IMR_VIRT_START,
83	.imr_end = SST_BYT_IMR_VIRT_END,	83	.imr_end = SST_BYT_IMR_VIRT_END,
84	.imr_use = true,	84	.imr_use = true,
85	.mailbox_start = SST_BYT_MBOX_PHY_ADDR,	85	.mailbox_start = SST_BYT_MBOX_PHY_ADDR,
86	.num_probes = 0,	86	.num_probes = 0,
87	.lpe_viewpt_rqd = true,	87	.lpe_viewpt_rqd = true,
88	};	88	};
89		89
90	static const struct sst_ipc_info byt_ipc_info = {	90	static const struct sst_ipc_info byt_ipc_info = {
91	.ipc_offset = 0,	91	.ipc_offset = 0,
92	.mbox_recv_off = 0x400,	92	.mbox_recv_off = 0x400,
93	};	93	};
94		94
95	static const struct sst_lib_dnld_info byt_lib_dnld_info = {	95	static const struct sst_lib_dnld_info byt_lib_dnld_info = {
96	.mod_base = SST_BYT_IMR_VIRT_START,	96	.mod_base = SST_BYT_IMR_VIRT_START,
97	.mod_end = SST_BYT_IMR_VIRT_END,	97	.mod_end = SST_BYT_IMR_VIRT_END,
98	.mod_table_offset = BYT_FW_MOD_TABLE_OFFSET,	98	.mod_table_offset = BYT_FW_MOD_TABLE_OFFSET,
99	.mod_table_size = BYT_FW_MOD_TABLE_SIZE,	99	.mod_table_size = BYT_FW_MOD_TABLE_SIZE,
100	.mod_ddr_dnld = false,	100	.mod_ddr_dnld = false,
101	};	101	};
102		102
103	static const struct sst_res_info byt_rvp_res_info = {	103	static const struct sst_res_info byt_rvp_res_info = {
104	.shim_offset = 0x140000,	104	.shim_offset = 0x140000,
105	.shim_size = 0x000100,	105	.shim_size = 0x000100,
106	.shim_phy_addr = SST_BYT_SHIM_PHY_ADDR,	106	.shim_phy_addr = SST_BYT_SHIM_PHY_ADDR,
107	.ssp0_offset = 0xa0000,	107	.ssp0_offset = 0xa0000,
108	.ssp0_size = 0x1000,	108	.ssp0_size = 0x1000,
109	.dma0_offset = 0x98000,	109	.dma0_offset = 0x98000,
110	.dma0_size = 0x4000,	110	.dma0_size = 0x4000,
111	.dma1_offset = 0x9c000,	111	.dma1_offset = 0x9c000,
112	.dma1_size = 0x4000,	112	.dma1_size = 0x4000,
113	.iram_offset = 0x0c0000,	113	.iram_offset = 0x0c0000,
114	.iram_size = 0x14000,	114	.iram_size = 0x14000,
115	.dram_offset = 0x100000,	115	.dram_offset = 0x100000,
116	.dram_size = 0x28000,	116	.dram_size = 0x28000,
117	.mbox_offset = 0x144000,	117	.mbox_offset = 0x144000,
118	.mbox_size = 0x1000,	118	.mbox_size = 0x1000,
119	.acpi_lpe_res_index = 0,	119	.acpi_lpe_res_index = 0,
120	.acpi_ddr_index = 2,	120	.acpi_ddr_index = 2,
121	.acpi_ipc_irq_index = 5,	121	.acpi_ipc_irq_index = 5,
122	};	122	};
123		123
124	static struct sst_platform_info byt_rvp_platform_data = {	124	static struct sst_platform_info byt_rvp_platform_data = {
125	.probe_data = &byt_fwparse_info,	125	.probe_data = &byt_fwparse_info,
126	.ipc_info = &byt_ipc_info,	126	.ipc_info = &byt_ipc_info,
127	.lib_info = &byt_lib_dnld_info,	127	.lib_info = &byt_lib_dnld_info,
128	.res_info = &byt_rvp_res_info,	128	.res_info = &byt_rvp_res_info,
129	.platform = "sst-mfld-platform",	129	.platform = "sst-mfld-platform",
130	};	130	};
131		131
132	/* Cherryview (Cherrytrail and Braswell) uses same mrfld dpcm fw as Baytrail,	132	/* Cherryview (Cherrytrail and Braswell) uses same mrfld dpcm fw as Baytrail,
133	* so pdata is same as Baytrail.	133	* so pdata is same as Baytrail.
134	*/	134	*/
135	static struct sst_platform_info chv_platform_data = {	135	static struct sst_platform_info chv_platform_data = {
136	.probe_data = &byt_fwparse_info,	136	.probe_data = &byt_fwparse_info,
137	.ipc_info = &byt_ipc_info,	137	.ipc_info = &byt_ipc_info,
138	.lib_info = &byt_lib_dnld_info,	138	.lib_info = &byt_lib_dnld_info,
139	.res_info = &byt_rvp_res_info,	139	.res_info = &byt_rvp_res_info,
140	.platform = "sst-mfld-platform",	140	.platform = "sst-mfld-platform",
141	};	141	};
142		142
143	static int sst_platform_get_resources(struct intel_sst_drv *ctx)	143	static int sst_platform_get_resources(struct intel_sst_drv *ctx)
144	{	144	{
145	struct resource *rsrc;	145	struct resource *rsrc;
146	struct platform_device *pdev = to_platform_device(ctx->dev);	146	struct platform_device *pdev = to_platform_device(ctx->dev);
147		147
148	/* All ACPI resource request here */	148	/* All ACPI resource request here */
149	/* Get Shim addr */	149	/* Get Shim addr */
150	rsrc = platform_get_resource(pdev, IORESOURCE_MEM,	150	rsrc = platform_get_resource(pdev, IORESOURCE_MEM,
151	ctx->pdata->res_info->acpi_lpe_res_index);	151	ctx->pdata->res_info->acpi_lpe_res_index);
152	if (!rsrc) {	152	if (!rsrc) {
153	dev_err(ctx->dev, "Invalid SHIM base from IFWI");	153	dev_err(ctx->dev, "Invalid SHIM base from IFWI");
154	return -EIO;	154	return -EIO;
155	}	155	}
156	dev_info(ctx->dev, "LPE base: %#x size:%#x", (unsigned int) rsrc->start,	156	dev_info(ctx->dev, "LPE base: %#x size:%#x", (unsigned int) rsrc->start,
157	(unsigned int)resource_size(rsrc));	157	(unsigned int)resource_size(rsrc));
158		158
159	ctx->iram_base = rsrc->start + ctx->pdata->res_info->iram_offset;	159	ctx->iram_base = rsrc->start + ctx->pdata->res_info->iram_offset;
160	ctx->iram_end = ctx->iram_base + ctx->pdata->res_info->iram_size - 1;	160	ctx->iram_end = ctx->iram_base + ctx->pdata->res_info->iram_size - 1;
161	dev_info(ctx->dev, "IRAM base: %#x", ctx->iram_base);	161	dev_info(ctx->dev, "IRAM base: %#x", ctx->iram_base);
162	ctx->iram = devm_ioremap_nocache(ctx->dev, ctx->iram_base,	162	ctx->iram = devm_ioremap_nocache(ctx->dev, ctx->iram_base,
163	ctx->pdata->res_info->iram_size);	163	ctx->pdata->res_info->iram_size);
164	if (!ctx->iram) {	164	if (!ctx->iram) {
165	dev_err(ctx->dev, "unable to map IRAM");	165	dev_err(ctx->dev, "unable to map IRAM");
166	return -EIO;	166	return -EIO;
167	}	167	}
168		168
169	ctx->dram_base = rsrc->start + ctx->pdata->res_info->dram_offset;	169	ctx->dram_base = rsrc->start + ctx->pdata->res_info->dram_offset;
170	ctx->dram_end = ctx->dram_base + ctx->pdata->res_info->dram_size - 1;	170	ctx->dram_end = ctx->dram_base + ctx->pdata->res_info->dram_size - 1;
171	dev_info(ctx->dev, "DRAM base: %#x", ctx->dram_base);	171	dev_info(ctx->dev, "DRAM base: %#x", ctx->dram_base);
172	ctx->dram = devm_ioremap_nocache(ctx->dev, ctx->dram_base,	172	ctx->dram = devm_ioremap_nocache(ctx->dev, ctx->dram_base,
173	ctx->pdata->res_info->dram_size);	173	ctx->pdata->res_info->dram_size);
174	if (!ctx->dram) {	174	if (!ctx->dram) {
175	dev_err(ctx->dev, "unable to map DRAM");	175	dev_err(ctx->dev, "unable to map DRAM");
176	return -EIO;	176	return -EIO;
177	}	177	}
178		178
179	ctx->shim_phy_add = rsrc->start + ctx->pdata->res_info->shim_offset;	179	ctx->shim_phy_add = rsrc->start + ctx->pdata->res_info->shim_offset;
180	dev_info(ctx->dev, "SHIM base: %#x", ctx->shim_phy_add);	180	dev_info(ctx->dev, "SHIM base: %#x", ctx->shim_phy_add);
181	ctx->shim = devm_ioremap_nocache(ctx->dev, ctx->shim_phy_add,	181	ctx->shim = devm_ioremap_nocache(ctx->dev, ctx->shim_phy_add,
182	ctx->pdata->res_info->shim_size);	182	ctx->pdata->res_info->shim_size);
183	if (!ctx->shim) {	183	if (!ctx->shim) {
184	dev_err(ctx->dev, "unable to map SHIM");	184	dev_err(ctx->dev, "unable to map SHIM");
185	return -EIO;	185	return -EIO;
186	}	186	}
187		187
188	/* reassign physical address to LPE viewpoint address */	188	/* reassign physical address to LPE viewpoint address */
189	ctx->shim_phy_add = ctx->pdata->res_info->shim_phy_addr;	189	ctx->shim_phy_add = ctx->pdata->res_info->shim_phy_addr;
190		190
191	/* Get mailbox addr */	191	/* Get mailbox addr */
192	ctx->mailbox_add = rsrc->start + ctx->pdata->res_info->mbox_offset;	192	ctx->mailbox_add = rsrc->start + ctx->pdata->res_info->mbox_offset;
193	dev_info(ctx->dev, "Mailbox base: %#x", ctx->mailbox_add);	193	dev_info(ctx->dev, "Mailbox base: %#x", ctx->mailbox_add);
194	ctx->mailbox = devm_ioremap_nocache(ctx->dev, ctx->mailbox_add,	194	ctx->mailbox = devm_ioremap_nocache(ctx->dev, ctx->mailbox_add,
195	ctx->pdata->res_info->mbox_size);	195	ctx->pdata->res_info->mbox_size);
196	if (!ctx->mailbox) {	196	if (!ctx->mailbox) {
197	dev_err(ctx->dev, "unable to map mailbox");	197	dev_err(ctx->dev, "unable to map mailbox");
198	return -EIO;	198	return -EIO;
199	}	199	}
200		200
201	/* reassign physical address to LPE viewpoint address */	201	/* reassign physical address to LPE viewpoint address */
202	ctx->mailbox_add = ctx->info.mailbox_start;	202	ctx->mailbox_add = ctx->info.mailbox_start;
203		203
204	rsrc = platform_get_resource(pdev, IORESOURCE_MEM,	204	rsrc = platform_get_resource(pdev, IORESOURCE_MEM,
205	ctx->pdata->res_info->acpi_ddr_index);	205	ctx->pdata->res_info->acpi_ddr_index);
206	if (!rsrc) {	206	if (!rsrc) {
207	dev_err(ctx->dev, "Invalid DDR base from IFWI");	207	dev_err(ctx->dev, "Invalid DDR base from IFWI");
208	return -EIO;	208	return -EIO;
209	}	209	}
210	ctx->ddr_base = rsrc->start;	210	ctx->ddr_base = rsrc->start;
211	ctx->ddr_end = rsrc->end;	211	ctx->ddr_end = rsrc->end;
212	dev_info(ctx->dev, "DDR base: %#x", ctx->ddr_base);	212	dev_info(ctx->dev, "DDR base: %#x", ctx->ddr_base);
213	ctx->ddr = devm_ioremap_nocache(ctx->dev, ctx->ddr_base,	213	ctx->ddr = devm_ioremap_nocache(ctx->dev, ctx->ddr_base,
214	resource_size(rsrc));	214	resource_size(rsrc));
215	if (!ctx->ddr) {	215	if (!ctx->ddr) {
216	dev_err(ctx->dev, "unable to map DDR");	216	dev_err(ctx->dev, "unable to map DDR");
217	return -EIO;	217	return -EIO;
218	}	218	}
219		219
220	/* Find the IRQ */	220	/* Find the IRQ */
221	ctx->irq_num = platform_get_irq(pdev,	221	ctx->irq_num = platform_get_irq(pdev,
222	ctx->pdata->res_info->acpi_ipc_irq_index);	222	ctx->pdata->res_info->acpi_ipc_irq_index);
223	return 0;	223	return 0;
224	}	224	}
225		225
226	static acpi_status sst_acpi_mach_match(acpi_handle handle, u32 level,	226	static acpi_status sst_acpi_mach_match(acpi_handle handle, u32 level,
227	void context, void *ret)	227	void context, void *ret)
228	{	228	{
229	(bool )context = true;	229	(bool )context = true;
230	return AE_OK;	230	return AE_OK;
231	}	231	}
232		232
233	static struct sst_machines *sst_acpi_find_machine(	233	static struct sst_machines *sst_acpi_find_machine(
234	struct sst_machines *machines)	234	struct sst_machines *machines)
235	{	235	{
236	struct sst_machines *mach;	236	struct sst_machines *mach;
237	bool found = false;	237	bool found = false;
238		238
239	for (mach = machines; mach->codec_id; mach++)	239	for (mach = machines; mach->codec_id; mach++)
240	if (ACPI_SUCCESS(acpi_get_devices(mach->codec_id,	240	if (ACPI_SUCCESS(acpi_get_devices(mach->codec_id,
241	sst_acpi_mach_match,	241	sst_acpi_mach_match,
242	&found, NULL)) && found)	242	&found, NULL)) && found)
243	return mach;	243	return mach;
244		244
245	return NULL;	245	return NULL;
246	}	246	}
247		247
248	int sst_acpi_probe(struct platform_device *pdev)	248	int sst_acpi_probe(struct platform_device *pdev)
249	{	249	{
250	struct device *dev = &pdev->dev;	250	struct device *dev = &pdev->dev;
251	int ret = 0;	251	int ret = 0;
252	struct intel_sst_drv *ctx;	252	struct intel_sst_drv *ctx;
253	const struct acpi_device_id *id;	253	const struct acpi_device_id *id;
254	struct sst_machines *mach;	254	struct sst_machines *mach;
255	struct platform_device *mdev;	255	struct platform_device *mdev;
256	struct platform_device *plat_dev;	256	struct platform_device *plat_dev;
257	unsigned int dev_id;	257	unsigned int dev_id;
258		258
259	id = acpi_match_device(dev->driver->acpi_match_table, dev);	259	id = acpi_match_device(dev->driver->acpi_match_table, dev);
260	if (!id)	260	if (!id)
261	return -ENODEV;	261	return -ENODEV;
262	dev_dbg(dev, "for %s", id->id);	262	dev_dbg(dev, "for %s", id->id);
263		263
264	mach = (struct sst_machines *)id->driver_data;	264	mach = (struct sst_machines *)id->driver_data;
265	mach = sst_acpi_find_machine(mach);	265	mach = sst_acpi_find_machine(mach);
266	if (mach == NULL) {	266	if (mach == NULL) {
267	dev_err(dev, "No matching machine driver found\n");	267	dev_err(dev, "No matching machine driver found\n");
268	return -ENODEV;	268	return -ENODEV;
269	}	269	}
270		270
271	ret = kstrtouint(id->id, 16, &dev_id);	271	ret = kstrtouint(id->id, 16, &dev_id);
272	if (ret < 0) {	272	if (ret < 0) {
273	dev_err(dev, "Unique device id conversion error: %d\n", ret);	273	dev_err(dev, "Unique device id conversion error: %d\n", ret);
274	return ret;	274	return ret;
275	}	275	}
276		276
277	dev_dbg(dev, "ACPI device id: %x\n", dev_id);	277	dev_dbg(dev, "ACPI device id: %x\n", dev_id);
278		278
279	plat_dev = platform_device_register_data(dev, mach->pdata->platform, -1, NULL, 0);	279	plat_dev = platform_device_register_data(dev, mach->pdata->platform, -1, NULL, 0);
280	if (IS_ERR(plat_dev)) {	280	if (IS_ERR(plat_dev)) {
281	dev_err(dev, "Failed to create machine device: %s\n", mach->pdata->platform);	281	dev_err(dev, "Failed to create machine device: %s\n", mach->pdata->platform);
282	return PTR_ERR(plat_dev);	282	return PTR_ERR(plat_dev);
283	}	283	}
284		284
285	/* Create platform device for sst machine driver */	285	/* Create platform device for sst machine driver */
286	mdev = platform_device_register_data(dev, mach->machine, -1, NULL, 0);	286	mdev = platform_device_register_data(dev, mach->machine, -1, NULL, 0);
287	if (IS_ERR(mdev)) {	287	if (IS_ERR(mdev)) {
288	dev_err(dev, "Failed to create machine device: %s\n", mach->machine);	288	dev_err(dev, "Failed to create machine device: %s\n", mach->machine);
289	return PTR_ERR(mdev);	289	return PTR_ERR(mdev);
290	}	290	}
291		291
292	ret = sst_alloc_drv_context(&ctx, dev, dev_id);	292	ret = sst_alloc_drv_context(&ctx, dev, dev_id);
293	if (ret < 0)	293	if (ret < 0)
294	return ret;	294	return ret;
295		295
296	/* Fill sst platform data */	296	/* Fill sst platform data */
297	ctx->pdata = mach->pdata;	297	ctx->pdata = mach->pdata;
298	strcpy(ctx->firmware_name, mach->firmware);	298	strcpy(ctx->firmware_name, mach->firmware);
299		299
300	ret = sst_platform_get_resources(ctx);	300	ret = sst_platform_get_resources(ctx);
301	if (ret)	301	if (ret)
302	return ret;	302	return ret;
303		303
304	ret = sst_context_init(ctx);	304	ret = sst_context_init(ctx);
305	if (ret < 0)	305	if (ret < 0)
306	return ret;	306	return ret;
307		307
308	/* need to save shim registers in BYT */	308	/* need to save shim registers in BYT */
309	ctx->shim_regs64 = devm_kzalloc(ctx->dev, sizeof(*ctx->shim_regs64),	309	ctx->shim_regs64 = devm_kzalloc(ctx->dev, sizeof(*ctx->shim_regs64),
310	GFP_KERNEL);	310	GFP_KERNEL);
311	if (!ctx->shim_regs64) {	311	if (!ctx->shim_regs64) {
312	return -ENOMEM;	312	return -ENOMEM;
313	goto do_sst_cleanup;	313	goto do_sst_cleanup;
314	}	314	}
315		315
316	sst_configure_runtime_pm(ctx);	316	sst_configure_runtime_pm(ctx);
317	platform_set_drvdata(pdev, ctx);	317	platform_set_drvdata(pdev, ctx);
318	return ret;	318	return ret;
319		319
320	do_sst_cleanup:	320	do_sst_cleanup:
321	sst_context_cleanup(ctx);	321	sst_context_cleanup(ctx);
322	platform_set_drvdata(pdev, NULL);	322	platform_set_drvdata(pdev, NULL);
323	dev_err(ctx->dev, "failed with %d\n", ret);	323	dev_err(ctx->dev, "failed with %d\n", ret);
324	return ret;	324	return ret;
325	}	325	}
326		326
327	/**	327	/**
328	* intel_sst_remove - remove function	328	* intel_sst_remove - remove function
329	*	329	*
330	* @pdev: platform device structure	330	* @pdev: platform device structure
331	*	331	*
332	* This function is called by OS when a device is unloaded	332	* This function is called by OS when a device is unloaded
333	* This frees the interrupt etc	333	* This frees the interrupt etc
334	*/	334	*/
335	int sst_acpi_remove(struct platform_device *pdev)	335	int sst_acpi_remove(struct platform_device *pdev)
336	{	336	{
337	struct intel_sst_drv *ctx;	337	struct intel_sst_drv *ctx;
338		338
339	ctx = platform_get_drvdata(pdev);	339	ctx = platform_get_drvdata(pdev);
340	sst_context_cleanup(ctx);	340	sst_context_cleanup(ctx);
341	platform_set_drvdata(pdev, NULL);	341	platform_set_drvdata(pdev, NULL);
342	return 0;	342	return 0;
343	}	343	}
344		344
345	static struct sst_machines sst_acpi_bytcr[] = {	345	static struct sst_machines sst_acpi_bytcr[] = {
346	{"10EC5640", "T100", "bytt100_rt5640", NULL, "fw_sst_0f28.bin",	346	{"10EC5640", "T100", "bytt100_rt5640", NULL, "intel/fw_sst_0f28.bin",
347	&byt_rvp_platform_data },	347	&byt_rvp_platform_data },
348	{},	348	{},
349	};	349	};
350		350
351	/* Cherryview-based platforms: CherryTrail and Braswell */	351	/* Cherryview-based platforms: CherryTrail and Braswell */
352	static struct sst_machines sst_acpi_chv[] = {	352	static struct sst_machines sst_acpi_chv[] = {
353	{"10EC5670", "cht-bsw", "cht-bsw-rt5672", NULL, "fw_sst_22a8.bin",	353	{"10EC5670", "cht-bsw", "cht-bsw-rt5672", NULL, "fw_sst_22a8.bin",
354	&chv_platform_data },	354	&chv_platform_data },
355	{},	355	{},
356	};	356	};
357		357
358	static const struct acpi_device_id sst_acpi_ids[] = {	358	static const struct acpi_device_id sst_acpi_ids[] = {
359	{ "80860F28", (unsigned long)&sst_acpi_bytcr},	359	{ "80860F28", (unsigned long)&sst_acpi_bytcr},
360	{ "808622A8", (unsigned long) &sst_acpi_chv},	360	{ "808622A8", (unsigned long) &sst_acpi_chv},
361	{ },	361	{ },
362	};	362	};
363		363
364	MODULE_DEVICE_TABLE(acpi, sst_acpi_ids);	364	MODULE_DEVICE_TABLE(acpi, sst_acpi_ids);
365		365
366	static struct platform_driver sst_acpi_driver = {	366	static struct platform_driver sst_acpi_driver = {
367	.driver = {	367	.driver = {
368	.name = "intel_sst_acpi",	368	.name = "intel_sst_acpi",
369	.owner = THIS_MODULE,	369	.owner = THIS_MODULE,
370	.acpi_match_table = ACPI_PTR(sst_acpi_ids),	370	.acpi_match_table = ACPI_PTR(sst_acpi_ids),
371	.pm = &intel_sst_pm,	371	.pm = &intel_sst_pm,
372	},	372	},
373	.probe = sst_acpi_probe,	373	.probe = sst_acpi_probe,
374	.remove = sst_acpi_remove,	374	.remove = sst_acpi_remove,
375	};	375	};
376		376
377	module_platform_driver(sst_acpi_driver);	377	module_platform_driver(sst_acpi_driver);
378		378
379	MODULE_DESCRIPTION("Intel (R) SST(R) Audio Engine ACPI Driver");	379	MODULE_DESCRIPTION("Intel (R) SST(R) Audio Engine ACPI Driver");
380	MODULE_AUTHOR("Ramesh Babu K V");	380	MODULE_AUTHOR("Ramesh Babu K V");
381	MODULE_AUTHOR("Omair Mohammed Abdullah");	381	MODULE_AUTHOR("Omair Mohammed Abdullah");
382	MODULE_LICENSE("GPL v2");	382	MODULE_LICENSE("GPL v2");
383	MODULE_ALIAS("sst");	383	MODULE_ALIAS("sst");
384		384

sound/soc/rockchip/rockchip_i2s.c

Diff comments View file @ e83ce4a

1	/* sound/soc/rockchip/rockchip_i2s.c	1	/* sound/soc/rockchip/rockchip_i2s.c
2	*	2	*
3	* ALSA SoC Audio Layer - Rockchip I2S Controller driver	3	* ALSA SoC Audio Layer - Rockchip I2S Controller driver
4	*	4	*
5	* Copyright (c) 2014 Rockchip Electronics Co. Ltd.	5	* Copyright (c) 2014 Rockchip Electronics Co. Ltd.
6	* Author: Jianqun <jay.xu@rock-chips.com>	6	* Author: Jianqun <jay.xu@rock-chips.com>
7	*	7	*
8	* This program is free software; you can redistribute it and/or modify	8	* This program is free software; you can redistribute it and/or modify
9	* it under the terms of the GNU General Public License version 2 as	9	* it under the terms of the GNU General Public License version 2 as
10	* published by the Free Software Foundation.	10	* published by the Free Software Foundation.
11	*/	11	*/
12		12
13	#include <linux/module.h>	13	#include <linux/module.h>
14	#include <linux/delay.h>	14	#include <linux/delay.h>
15	#include <linux/of_gpio.h>	15	#include <linux/of_gpio.h>
16	#include <linux/clk.h>	16	#include <linux/clk.h>
17	#include <linux/pm_runtime.h>	17	#include <linux/pm_runtime.h>
18	#include <linux/regmap.h>	18	#include <linux/regmap.h>
19	#include <sound/pcm_params.h>	19	#include <sound/pcm_params.h>
20	#include <sound/dmaengine_pcm.h>	20	#include <sound/dmaengine_pcm.h>
21		21
22	#include "rockchip_i2s.h"	22	#include "rockchip_i2s.h"
23		23
24	#define DRV_NAME "rockchip-i2s"	24	#define DRV_NAME "rockchip-i2s"
25		25
26	struct rk_i2s_dev {	26	struct rk_i2s_dev {
27	struct device *dev;	27	struct device *dev;
28		28
29	struct clk *hclk;	29	struct clk *hclk;
30	struct clk *mclk;	30	struct clk *mclk;
31		31
32	struct snd_dmaengine_dai_dma_data capture_dma_data;	32	struct snd_dmaengine_dai_dma_data capture_dma_data;
33	struct snd_dmaengine_dai_dma_data playback_dma_data;	33	struct snd_dmaengine_dai_dma_data playback_dma_data;
34		34
35	struct regmap *regmap;	35	struct regmap *regmap;
36		36
37	/*	37	/*
38	* Used to indicate the tx/rx status.	38	* Used to indicate the tx/rx status.
39	* I2S controller hopes to start the tx and rx together,	39	* I2S controller hopes to start the tx and rx together,
40	* also to stop them when they are both try to stop.	40	* also to stop them when they are both try to stop.
41	*/	41	*/
42	bool tx_start;	42	bool tx_start;
43	bool rx_start;	43	bool rx_start;
44	};	44	};
45		45
46	static int i2s_runtime_suspend(struct device *dev)	46	static int i2s_runtime_suspend(struct device *dev)
47	{	47	{
48	struct rk_i2s_dev *i2s = dev_get_drvdata(dev);	48	struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
49		49
50	clk_disable_unprepare(i2s->mclk);	50	clk_disable_unprepare(i2s->mclk);
51		51
52	return 0;	52	return 0;
53	}	53	}
54		54
55	static int i2s_runtime_resume(struct device *dev)	55	static int i2s_runtime_resume(struct device *dev)
56	{	56	{
57	struct rk_i2s_dev *i2s = dev_get_drvdata(dev);	57	struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
58	int ret;	58	int ret;
59		59
60	ret = clk_prepare_enable(i2s->mclk);	60	ret = clk_prepare_enable(i2s->mclk);
61	if (ret) {	61	if (ret) {
62	dev_err(i2s->dev, "clock enable failed %d\n", ret);	62	dev_err(i2s->dev, "clock enable failed %d\n", ret);
63	return ret;	63	return ret;
64	}	64	}
65		65
66	return 0;	66	return 0;
67	}	67	}
68		68
69	static inline struct rk_i2s_dev to_info(struct snd_soc_dai dai)	69	static inline struct rk_i2s_dev to_info(struct snd_soc_dai dai)
70	{	70	{
71	return snd_soc_dai_get_drvdata(dai);	71	return snd_soc_dai_get_drvdata(dai);
72	}	72	}
73		73
74	static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)	74	static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
75	{	75	{
76	unsigned int val = 0;	76	unsigned int val = 0;
77	int retry = 10;	77	int retry = 10;
78		78
79	if (on) {	79	if (on) {
80	regmap_update_bits(i2s->regmap, I2S_DMACR,	80	regmap_update_bits(i2s->regmap, I2S_DMACR,
81	I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);	81	I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
82		82
83	regmap_update_bits(i2s->regmap, I2S_XFER,	83	regmap_update_bits(i2s->regmap, I2S_XFER,
84	I2S_XFER_TXS_START \| I2S_XFER_RXS_START,	84	I2S_XFER_TXS_START \| I2S_XFER_RXS_START,
85	I2S_XFER_TXS_START \| I2S_XFER_RXS_START);	85	I2S_XFER_TXS_START \| I2S_XFER_RXS_START);
86		86
87	i2s->tx_start = true;	87	i2s->tx_start = true;
88	} else {	88	} else {
89	i2s->tx_start = false;	89	i2s->tx_start = false;
90		90
91	regmap_update_bits(i2s->regmap, I2S_DMACR,	91	regmap_update_bits(i2s->regmap, I2S_DMACR,
92	I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);	92	I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
93		93
94	if (!i2s->rx_start) {	94	if (!i2s->rx_start) {
95	regmap_update_bits(i2s->regmap, I2S_XFER,	95	regmap_update_bits(i2s->regmap, I2S_XFER,
96	I2S_XFER_TXS_START \|	96	I2S_XFER_TXS_START \|
97	I2S_XFER_RXS_START,	97	I2S_XFER_RXS_START,
98	I2S_XFER_TXS_STOP \|	98	I2S_XFER_TXS_STOP \|
99	I2S_XFER_RXS_STOP);	99	I2S_XFER_RXS_STOP);
100		100
101	regmap_update_bits(i2s->regmap, I2S_CLR,	101	regmap_update_bits(i2s->regmap, I2S_CLR,
102	I2S_CLR_TXC \| I2S_CLR_RXC,	102	I2S_CLR_TXC \| I2S_CLR_RXC,
103	I2S_CLR_TXC \| I2S_CLR_RXC);	103	I2S_CLR_TXC \| I2S_CLR_RXC);
104		104
105	regmap_read(i2s->regmap, I2S_CLR, &val);	105	regmap_read(i2s->regmap, I2S_CLR, &val);
106		106
107	/* Should wait for clear operation to finish */	107	/* Should wait for clear operation to finish */
108	while (val) {	108	while (val) {
109	regmap_read(i2s->regmap, I2S_CLR, &val);	109	regmap_read(i2s->regmap, I2S_CLR, &val);
110	retry--;	110	retry--;
111	if (!retry) {	111	if (!retry) {
112	dev_warn(i2s->dev, "fail to clear\n");	112	dev_warn(i2s->dev, "fail to clear\n");
113	break;	113	break;
114	}	114	}
115	}	115	}
116	}	116	}
117	}	117	}
118	}	118	}
119		119
120	static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)	120	static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
121	{	121	{
122	unsigned int val = 0;	122	unsigned int val = 0;
123	int retry = 10;	123	int retry = 10;
124		124
125	if (on) {	125	if (on) {
126	regmap_update_bits(i2s->regmap, I2S_DMACR,	126	regmap_update_bits(i2s->regmap, I2S_DMACR,
127	I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);	127	I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
128		128
129	regmap_update_bits(i2s->regmap, I2S_XFER,	129	regmap_update_bits(i2s->regmap, I2S_XFER,
130	I2S_XFER_TXS_START \| I2S_XFER_RXS_START,	130	I2S_XFER_TXS_START \| I2S_XFER_RXS_START,
131	I2S_XFER_TXS_START \| I2S_XFER_RXS_START);	131	I2S_XFER_TXS_START \| I2S_XFER_RXS_START);
132		132
133	i2s->rx_start = true;	133	i2s->rx_start = true;
134	} else {	134	} else {
135	i2s->rx_start = false;	135	i2s->rx_start = false;
136		136
137	regmap_update_bits(i2s->regmap, I2S_DMACR,	137	regmap_update_bits(i2s->regmap, I2S_DMACR,
138	I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);	138	I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
139		139
140	if (!i2s->tx_start) {	140	if (!i2s->tx_start) {
141	regmap_update_bits(i2s->regmap, I2S_XFER,	141	regmap_update_bits(i2s->regmap, I2S_XFER,
142	I2S_XFER_TXS_START \|	142	I2S_XFER_TXS_START \|
143	I2S_XFER_RXS_START,	143	I2S_XFER_RXS_START,
144	I2S_XFER_TXS_STOP \|	144	I2S_XFER_TXS_STOP \|
145	I2S_XFER_RXS_STOP);	145	I2S_XFER_RXS_STOP);
146		146
147	regmap_update_bits(i2s->regmap, I2S_CLR,	147	regmap_update_bits(i2s->regmap, I2S_CLR,
148	I2S_CLR_TXC \| I2S_CLR_RXC,	148	I2S_CLR_TXC \| I2S_CLR_RXC,
149	I2S_CLR_TXC \| I2S_CLR_RXC);	149	I2S_CLR_TXC \| I2S_CLR_RXC);
150		150
151	regmap_read(i2s->regmap, I2S_CLR, &val);	151	regmap_read(i2s->regmap, I2S_CLR, &val);
152		152
153	/* Should wait for clear operation to finish */	153	/* Should wait for clear operation to finish */
154	while (val) {	154	while (val) {
155	regmap_read(i2s->regmap, I2S_CLR, &val);	155	regmap_read(i2s->regmap, I2S_CLR, &val);
156	retry--;	156	retry--;
157	if (!retry) {	157	if (!retry) {
158	dev_warn(i2s->dev, "fail to clear\n");	158	dev_warn(i2s->dev, "fail to clear\n");
159	break;	159	break;
160	}	160	}
161	}	161	}
162	}	162	}
163	}	163	}
164	}	164	}
165		165
166	static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,	166	static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
167	unsigned int fmt)	167	unsigned int fmt)
168	{	168	{
169	struct rk_i2s_dev *i2s = to_info(cpu_dai);	169	struct rk_i2s_dev *i2s = to_info(cpu_dai);
170	unsigned int mask = 0, val = 0;	170	unsigned int mask = 0, val = 0;
171		171
172	mask = I2S_CKR_MSS_MASK;	172	mask = I2S_CKR_MSS_MASK;
173	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {	173	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
174	case SND_SOC_DAIFMT_CBS_CFS:	174	case SND_SOC_DAIFMT_CBS_CFS:
175	/* Set source clock in Master mode */	175	/* Set source clock in Master mode */
176	val = I2S_CKR_MSS_MASTER;	176	val = I2S_CKR_MSS_MASTER;
177	break;	177	break;
178	case SND_SOC_DAIFMT_CBM_CFM:	178	case SND_SOC_DAIFMT_CBM_CFM:
179	val = I2S_CKR_MSS_SLAVE;	179	val = I2S_CKR_MSS_SLAVE;
180	break;	180	break;
181	default:	181	default:
182	return -EINVAL;	182	return -EINVAL;
183	}	183	}
184		184
185	regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);	185	regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
186		186
187	mask = I2S_TXCR_IBM_MASK;	187	mask = I2S_TXCR_IBM_MASK;
188	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {	188	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
189	case SND_SOC_DAIFMT_RIGHT_J:	189	case SND_SOC_DAIFMT_RIGHT_J:
190	val = I2S_TXCR_IBM_RSJM;	190	val = I2S_TXCR_IBM_RSJM;
191	break;	191	break;
192	case SND_SOC_DAIFMT_LEFT_J:	192	case SND_SOC_DAIFMT_LEFT_J:
193	val = I2S_TXCR_IBM_LSJM;	193	val = I2S_TXCR_IBM_LSJM;
194	break;	194	break;
195	case SND_SOC_DAIFMT_I2S:	195	case SND_SOC_DAIFMT_I2S:
196	val = I2S_TXCR_IBM_NORMAL;	196	val = I2S_TXCR_IBM_NORMAL;
197	break;	197	break;
198	default:	198	default:
199	return -EINVAL;	199	return -EINVAL;
200	}	200	}
201		201
202	regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);	202	regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
203		203
204	mask = I2S_RXCR_IBM_MASK;	204	mask = I2S_RXCR_IBM_MASK;
205	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {	205	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
206	case SND_SOC_DAIFMT_RIGHT_J:	206	case SND_SOC_DAIFMT_RIGHT_J:
207	val = I2S_RXCR_IBM_RSJM;	207	val = I2S_RXCR_IBM_RSJM;
208	break;	208	break;
209	case SND_SOC_DAIFMT_LEFT_J:	209	case SND_SOC_DAIFMT_LEFT_J:
210	val = I2S_RXCR_IBM_LSJM;	210	val = I2S_RXCR_IBM_LSJM;
211	break;	211	break;
212	case SND_SOC_DAIFMT_I2S:	212	case SND_SOC_DAIFMT_I2S:
213	val = I2S_RXCR_IBM_NORMAL;	213	val = I2S_RXCR_IBM_NORMAL;
214	break;	214	break;
215	default:	215	default:
216	return -EINVAL;	216	return -EINVAL;
217	}	217	}
218		218
219	regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);	219	regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
220		220
221	return 0;	221	return 0;
222	}	222	}
223		223
224	static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,	224	static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
225	struct snd_pcm_hw_params *params,	225	struct snd_pcm_hw_params *params,
226	struct snd_soc_dai *dai)	226	struct snd_soc_dai *dai)
227	{	227	{
228	struct rk_i2s_dev *i2s = to_info(dai);	228	struct rk_i2s_dev *i2s = to_info(dai);
229	unsigned int val = 0;	229	unsigned int val = 0;
230		230
231	switch (params_format(params)) {	231	switch (params_format(params)) {
232	case SNDRV_PCM_FORMAT_S8:	232	case SNDRV_PCM_FORMAT_S8:
233	val \|= I2S_TXCR_VDW(8);	233	val \|= I2S_TXCR_VDW(8);
234	break;	234	break;
235	case SNDRV_PCM_FORMAT_S16_LE:	235	case SNDRV_PCM_FORMAT_S16_LE:
236	val \|= I2S_TXCR_VDW(16);	236	val \|= I2S_TXCR_VDW(16);
237	break;	237	break;
238	case SNDRV_PCM_FORMAT_S20_3LE:	238	case SNDRV_PCM_FORMAT_S20_3LE:
239	val \|= I2S_TXCR_VDW(20);	239	val \|= I2S_TXCR_VDW(20);
240	break;	240	break;
241	case SNDRV_PCM_FORMAT_S24_LE:	241	case SNDRV_PCM_FORMAT_S24_LE:
242	val \|= I2S_TXCR_VDW(24);	242	val \|= I2S_TXCR_VDW(24);
243	break;	243	break;
244	default:	244	default:
245	return -EINVAL;	245	return -EINVAL;
246	}	246	}
247		247
248	regmap_update_bits(i2s->regmap, I2S_TXCR, I2S_TXCR_VDW_MASK, val);	248	regmap_update_bits(i2s->regmap, I2S_TXCR, I2S_TXCR_VDW_MASK, val);
249	regmap_update_bits(i2s->regmap, I2S_RXCR, I2S_RXCR_VDW_MASK, val);	249	regmap_update_bits(i2s->regmap, I2S_RXCR, I2S_RXCR_VDW_MASK, val);
250		250
251	return 0;	251	return 0;
252	}	252	}
253		253
254	static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,	254	static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
255	int cmd, struct snd_soc_dai *dai)	255	int cmd, struct snd_soc_dai *dai)
256	{	256	{
257	struct rk_i2s_dev *i2s = to_info(dai);	257	struct rk_i2s_dev *i2s = to_info(dai);
258	int ret = 0;	258	int ret = 0;
259		259
260	switch (cmd) {	260	switch (cmd) {
261	case SNDRV_PCM_TRIGGER_START:	261	case SNDRV_PCM_TRIGGER_START:
262	case SNDRV_PCM_TRIGGER_RESUME:	262	case SNDRV_PCM_TRIGGER_RESUME:
263	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:	263	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
264	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)	264	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
265	rockchip_snd_rxctrl(i2s, 1);	265	rockchip_snd_rxctrl(i2s, 1);
266	else	266	else
267	rockchip_snd_txctrl(i2s, 1);	267	rockchip_snd_txctrl(i2s, 1);
268	break;	268	break;
269	case SNDRV_PCM_TRIGGER_SUSPEND:	269	case SNDRV_PCM_TRIGGER_SUSPEND:
270	case SNDRV_PCM_TRIGGER_STOP:	270	case SNDRV_PCM_TRIGGER_STOP:
271	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:	271	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
272	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)	272	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
273	rockchip_snd_rxctrl(i2s, 0);	273	rockchip_snd_rxctrl(i2s, 0);
274	else	274	else
275	rockchip_snd_txctrl(i2s, 0);	275	rockchip_snd_txctrl(i2s, 0);
276	break;	276	break;
277	default:	277	default:
278	ret = -EINVAL;	278	ret = -EINVAL;
279	break;	279	break;
280	}	280	}
281		281
282	return ret;	282	return ret;
283	}	283	}
284		284
285	static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,	285	static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
286	unsigned int freq, int dir)	286	unsigned int freq, int dir)
287	{	287	{
288	struct rk_i2s_dev *i2s = to_info(cpu_dai);	288	struct rk_i2s_dev *i2s = to_info(cpu_dai);
289	int ret;	289	int ret;
290		290
291	ret = clk_set_rate(i2s->mclk, freq);	291	ret = clk_set_rate(i2s->mclk, freq);
292	if (ret)	292	if (ret)
293	dev_err(i2s->dev, "Fail to set mclk %d\n", ret);	293	dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
294		294
295	return ret;	295	return ret;
296	}	296	}
297		297
298	static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)	298	static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
299	{	299	{
300	struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);	300	struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
301		301
302	dai->capture_dma_data = &i2s->capture_dma_data;	302	dai->capture_dma_data = &i2s->capture_dma_data;
303	dai->playback_dma_data = &i2s->playback_dma_data;	303	dai->playback_dma_data = &i2s->playback_dma_data;
304		304
305	return 0;	305	return 0;
306	}	306	}
307		307
308	static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {	308	static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
309	.hw_params = rockchip_i2s_hw_params,	309	.hw_params = rockchip_i2s_hw_params,
310	.set_sysclk = rockchip_i2s_set_sysclk,	310	.set_sysclk = rockchip_i2s_set_sysclk,
311	.set_fmt = rockchip_i2s_set_fmt,	311	.set_fmt = rockchip_i2s_set_fmt,
312	.trigger = rockchip_i2s_trigger,	312	.trigger = rockchip_i2s_trigger,
313	};	313	};
314		314
315	static struct snd_soc_dai_driver rockchip_i2s_dai = {	315	static struct snd_soc_dai_driver rockchip_i2s_dai = {
316	.probe = rockchip_i2s_dai_probe,	316	.probe = rockchip_i2s_dai_probe,
317	.playback = {	317	.playback = {
318	.stream_name = "Playback",	318	.stream_name = "Playback",
319	.channels_min = 2,	319	.channels_min = 2,
320	.channels_max = 8,	320	.channels_max = 8,
321	.rates = SNDRV_PCM_RATE_8000_192000,	321	.rates = SNDRV_PCM_RATE_8000_192000,
322	.formats = (SNDRV_PCM_FMTBIT_S8 \|	322	.formats = (SNDRV_PCM_FMTBIT_S8 \|
323	SNDRV_PCM_FMTBIT_S16_LE \|	323	SNDRV_PCM_FMTBIT_S16_LE \|
324	SNDRV_PCM_FMTBIT_S20_3LE \|	324	SNDRV_PCM_FMTBIT_S20_3LE \|
325	SNDRV_PCM_FMTBIT_S24_LE),	325	SNDRV_PCM_FMTBIT_S24_LE),
326	},	326	},
327	.capture = {	327	.capture = {
328	.stream_name = "Capture",	328	.stream_name = "Capture",
329	.channels_min = 2,	329	.channels_min = 2,
330	.channels_max = 2,	330	.channels_max = 2,
331	.rates = SNDRV_PCM_RATE_8000_192000,	331	.rates = SNDRV_PCM_RATE_8000_192000,
332	.formats = (SNDRV_PCM_FMTBIT_S8 \|	332	.formats = (SNDRV_PCM_FMTBIT_S8 \|
333	SNDRV_PCM_FMTBIT_S16_LE \|	333	SNDRV_PCM_FMTBIT_S16_LE \|
334	SNDRV_PCM_FMTBIT_S20_3LE \|	334	SNDRV_PCM_FMTBIT_S20_3LE \|
335	SNDRV_PCM_FMTBIT_S24_LE),	335	SNDRV_PCM_FMTBIT_S24_LE),
336	},	336	},
337	.ops = &rockchip_i2s_dai_ops,	337	.ops = &rockchip_i2s_dai_ops,
338	};	338	};
339		339
340	static const struct snd_soc_component_driver rockchip_i2s_component = {	340	static const struct snd_soc_component_driver rockchip_i2s_component = {
341	.name = DRV_NAME,	341	.name = DRV_NAME,
342	};	342	};
343		343
344	static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)	344	static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
345	{	345	{
346	switch (reg) {	346	switch (reg) {
347	case I2S_TXCR:	347	case I2S_TXCR:
348	case I2S_RXCR:	348	case I2S_RXCR:
349	case I2S_CKR:	349	case I2S_CKR:
350	case I2S_DMACR:	350	case I2S_DMACR:
351	case I2S_INTCR:	351	case I2S_INTCR:
352	case I2S_XFER:	352	case I2S_XFER:
353	case I2S_CLR:	353	case I2S_CLR:
354	case I2S_TXDR:	354	case I2S_TXDR:
355	return true;	355	return true;
356	default:	356	default:
357	return false;	357	return false;
358	}	358	}
359	}	359	}
360		360
361	static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)	361	static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
362	{	362	{
363	switch (reg) {	363	switch (reg) {
364	case I2S_TXCR:	364	case I2S_TXCR:
365	case I2S_RXCR:	365	case I2S_RXCR:
366	case I2S_CKR:	366	case I2S_CKR:
367	case I2S_DMACR:	367	case I2S_DMACR:
368	case I2S_INTCR:	368	case I2S_INTCR:
369	case I2S_XFER:	369	case I2S_XFER:
370	case I2S_CLR:	370	case I2S_CLR:
371	case I2S_RXDR:	371	case I2S_RXDR:
372	case I2S_FIFOLR:	372	case I2S_FIFOLR:
373	case I2S_INTSR:	373	case I2S_INTSR:
374	return true;	374	return true;
375	default:	375	default:
376	return false;	376	return false;
377	}	377	}
378	}	378	}
379		379
380	static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)	380	static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
381	{	381	{
382	switch (reg) {	382	switch (reg) {
383	case I2S_INTSR:	383	case I2S_INTSR:
384	case I2S_CLR:	384	case I2S_CLR:
385	return true;	385	return true;
386	default:	386	default:
387	return false;	387	return false;
388	}	388	}
389	}	389	}
390		390
391	static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)	391	static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
392	{	392	{
393	switch (reg) {	393	switch (reg) {
394	default:	394	default:
395	return false;	395	return false;
396	}	396	}
397	}	397	}
398		398
399	static const struct regmap_config rockchip_i2s_regmap_config = {	399	static const struct regmap_config rockchip_i2s_regmap_config = {
400	.reg_bits = 32,	400	.reg_bits = 32,
401	.reg_stride = 4,	401	.reg_stride = 4,
402	.val_bits = 32,	402	.val_bits = 32,
403	.max_register = I2S_RXDR,	403	.max_register = I2S_RXDR,
404	.writeable_reg = rockchip_i2s_wr_reg,	404	.writeable_reg = rockchip_i2s_wr_reg,
405	.readable_reg = rockchip_i2s_rd_reg,	405	.readable_reg = rockchip_i2s_rd_reg,
406	.volatile_reg = rockchip_i2s_volatile_reg,	406	.volatile_reg = rockchip_i2s_volatile_reg,
407	.precious_reg = rockchip_i2s_precious_reg,	407	.precious_reg = rockchip_i2s_precious_reg,
408	.cache_type = REGCACHE_FLAT,	408	.cache_type = REGCACHE_FLAT,
409	};	409	};
410		410
411	static int rockchip_i2s_probe(struct platform_device *pdev)	411	static int rockchip_i2s_probe(struct platform_device *pdev)
412	{	412	{
413	struct rk_i2s_dev *i2s;	413	struct rk_i2s_dev *i2s;
414	struct resource *res;	414	struct resource *res;
415	void __iomem *regs;	415	void __iomem *regs;
416	int ret;	416	int ret;
417		417
418	i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);	418	i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
419	if (!i2s) {	419	if (!i2s) {
420	dev_err(&pdev->dev, "Can't allocate rk_i2s_dev\n");	420	dev_err(&pdev->dev, "Can't allocate rk_i2s_dev\n");
421	return -ENOMEM;	421	return -ENOMEM;
422	}	422	}
423		423
424	/* try to prepare related clocks */	424	/* try to prepare related clocks */
425	i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");	425	i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
426	if (IS_ERR(i2s->hclk)) {	426	if (IS_ERR(i2s->hclk)) {
427	dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");	427	dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
428	return PTR_ERR(i2s->hclk);	428	return PTR_ERR(i2s->hclk);
429	}	429	}
430	ret = clk_prepare_enable(i2s->hclk);	430	ret = clk_prepare_enable(i2s->hclk);
431	if (ret) {	431	if (ret) {
432	dev_err(i2s->dev, "hclock enable failed %d\n", ret);	432	dev_err(i2s->dev, "hclock enable failed %d\n", ret);
433	return ret;	433	return ret;
434	}	434	}
435		435
436	i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");	436	i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
437	if (IS_ERR(i2s->mclk)) {	437	if (IS_ERR(i2s->mclk)) {
438	dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");	438	dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
439	return PTR_ERR(i2s->mclk);	439	return PTR_ERR(i2s->mclk);
440	}	440	}
441		441
442	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);	442	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
443	regs = devm_ioremap_resource(&pdev->dev, res);	443	regs = devm_ioremap_resource(&pdev->dev, res);
444	if (IS_ERR(regs))	444	if (IS_ERR(regs))
445	return PTR_ERR(regs);	445	return PTR_ERR(regs);
446		446
447	i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,	447	i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
448	&rockchip_i2s_regmap_config);	448	&rockchip_i2s_regmap_config);
449	if (IS_ERR(i2s->regmap)) {	449	if (IS_ERR(i2s->regmap)) {
450	dev_err(&pdev->dev,	450	dev_err(&pdev->dev,
451	"Failed to initialise managed register map\n");	451	"Failed to initialise managed register map\n");
452	return PTR_ERR(i2s->regmap);	452	return PTR_ERR(i2s->regmap);
453	}	453	}
454		454
455	i2s->playback_dma_data.addr = res->start + I2S_TXDR;	455	i2s->playback_dma_data.addr = res->start + I2S_TXDR;
456	i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;	456	i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
457	i2s->playback_dma_data.maxburst = 16;	457	i2s->playback_dma_data.maxburst = 4;
458		458
459	i2s->capture_dma_data.addr = res->start + I2S_RXDR;	459	i2s->capture_dma_data.addr = res->start + I2S_RXDR;
460	i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;	460	i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
461	i2s->capture_dma_data.maxburst = 16;	461	i2s->capture_dma_data.maxburst = 4;
462		462
463	i2s->dev = &pdev->dev;	463	i2s->dev = &pdev->dev;
464	dev_set_drvdata(&pdev->dev, i2s);	464	dev_set_drvdata(&pdev->dev, i2s);
465		465
466	pm_runtime_enable(&pdev->dev);	466	pm_runtime_enable(&pdev->dev);
467	if (!pm_runtime_enabled(&pdev->dev)) {	467	if (!pm_runtime_enabled(&pdev->dev)) {
468	ret = i2s_runtime_resume(&pdev->dev);	468	ret = i2s_runtime_resume(&pdev->dev);
469	if (ret)	469	if (ret)
470	goto err_pm_disable;	470	goto err_pm_disable;
471	}	471	}
472		472
473	ret = devm_snd_soc_register_component(&pdev->dev,	473	ret = devm_snd_soc_register_component(&pdev->dev,
474	&rockchip_i2s_component,	474	&rockchip_i2s_component,
475	&rockchip_i2s_dai, 1);	475	&rockchip_i2s_dai, 1);
476	if (ret) {	476	if (ret) {
477	dev_err(&pdev->dev, "Could not register DAI\n");	477	dev_err(&pdev->dev, "Could not register DAI\n");
478	goto err_suspend;	478	goto err_suspend;
479	}	479	}
480		480
481	ret = snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);	481	ret = snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
482	if (ret) {	482	if (ret) {
483	dev_err(&pdev->dev, "Could not register PCM\n");	483	dev_err(&pdev->dev, "Could not register PCM\n");
484	goto err_pcm_register;	484	goto err_pcm_register;
485	}	485	}
486		486
487	return 0;	487	return 0;
488		488
489	err_pcm_register:	489	err_pcm_register:
490	snd_dmaengine_pcm_unregister(&pdev->dev);	490	snd_dmaengine_pcm_unregister(&pdev->dev);
491	err_suspend:	491	err_suspend:
492	if (!pm_runtime_status_suspended(&pdev->dev))	492	if (!pm_runtime_status_suspended(&pdev->dev))
493	i2s_runtime_suspend(&pdev->dev);	493	i2s_runtime_suspend(&pdev->dev);
494	err_pm_disable:	494	err_pm_disable:
495	pm_runtime_disable(&pdev->dev);	495	pm_runtime_disable(&pdev->dev);
496		496
497	return ret;	497	return ret;
498	}	498	}
499		499
500	static int rockchip_i2s_remove(struct platform_device *pdev)	500	static int rockchip_i2s_remove(struct platform_device *pdev)
501	{	501	{
502	struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);	502	struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
503		503
504	pm_runtime_disable(&pdev->dev);	504	pm_runtime_disable(&pdev->dev);
505	if (!pm_runtime_status_suspended(&pdev->dev))	505	if (!pm_runtime_status_suspended(&pdev->dev))
506	i2s_runtime_suspend(&pdev->dev);	506	i2s_runtime_suspend(&pdev->dev);
507		507
508	clk_disable_unprepare(i2s->mclk);	508	clk_disable_unprepare(i2s->mclk);
509	clk_disable_unprepare(i2s->hclk);	509	clk_disable_unprepare(i2s->hclk);
510	snd_dmaengine_pcm_unregister(&pdev->dev);	510	snd_dmaengine_pcm_unregister(&pdev->dev);
511	snd_soc_unregister_component(&pdev->dev);	511	snd_soc_unregister_component(&pdev->dev);
512		512
513	return 0;	513	return 0;
514	}	514	}
515		515
516	static const struct of_device_id rockchip_i2s_match[] = {	516	static const struct of_device_id rockchip_i2s_match[] = {
517	{ .compatible = "rockchip,rk3066-i2s", },	517	{ .compatible = "rockchip,rk3066-i2s", },
518	{},	518	{},
519	};	519	};
520		520
521	static const struct dev_pm_ops rockchip_i2s_pm_ops = {	521	static const struct dev_pm_ops rockchip_i2s_pm_ops = {
522	SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,	522	SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
523	NULL)	523	NULL)
524	};	524	};
525		525
526	static struct platform_driver rockchip_i2s_driver = {	526	static struct platform_driver rockchip_i2s_driver = {
527	.probe = rockchip_i2s_probe,	527	.probe = rockchip_i2s_probe,
528	.remove = rockchip_i2s_remove,	528	.remove = rockchip_i2s_remove,
529	.driver = {	529	.driver = {
530	.name = DRV_NAME,	530	.name = DRV_NAME,
531	.of_match_table = of_match_ptr(rockchip_i2s_match),	531	.of_match_table = of_match_ptr(rockchip_i2s_match),
532	.pm = &rockchip_i2s_pm_ops,	532	.pm = &rockchip_i2s_pm_ops,
533	},	533	},
534	};	534	};
535	module_platform_driver(rockchip_i2s_driver);	535	module_platform_driver(rockchip_i2s_driver);
536		536
537	MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");	537	MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
538	MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");	538	MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
539	MODULE_LICENSE("GPL v2");	539	MODULE_LICENSE("GPL v2");
540	MODULE_ALIAS("platform:" DRV_NAME);	540	MODULE_ALIAS("platform:" DRV_NAME);
541	MODULE_DEVICE_TABLE(of, rockchip_i2s_match);	541	MODULE_DEVICE_TABLE(of, rockchip_i2s_match);
542		542

sound/soc/rockchip/rockchip_i2s.h

Diff comments View file @ e83ce4a

sound/soc/soc-core.c

Diff comments View file @ e83ce4a

 /*
  * soc-core.c  --  ALSA SoC Audio Layer
  *
  * Copyright 2005 Wolfson Microelectronics PLC.
  * Copyright 2005 Openedhand Ltd.
  * Copyright (C) 2010 Slimlogic Ltd.
  * Copyright (C) 2010 Texas Instruments Inc.
  *
  * Author: Liam Girdwood <lrg@slimlogic.co.uk>
  *         with code, comments and ideas from :-
  *         Richard Purdie <richard@openedhand.com>
  *
  *  This program is free software; you can redistribute  it and/or modify it
  *  under  the terms of  the GNU General  Public License as published by the
  *  Free Software Foundation;  either version 2 of the  License, or (at your
  *  option) any later version.
  *
  *  TODO:
  *   o Add hw rules to enforce rates, etc.
  *   o More testing with other codecs/machines.
  *   o Add more codecs and platforms to ensure good API coverage.
  *   o Support TDM on PCM and I2S
  */
 #include <linux/module.h>
 #include <linux/moduleparam.h>
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/pm.h>
 #include <linux/bitops.h>
 #include <linux/debugfs.h>
 #include <linux/platform_device.h>
 #include <linux/pinctrl/consumer.h>
 #include <linux/ctype.h>
 #include <linux/slab.h>
 #include <linux/of.h>
 #include <sound/core.h>
 #include <sound/jack.h>
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
 #include <sound/soc-dpcm.h>
 #include <sound/initval.h>
 #define CREATE_TRACE_POINTS
 #include <trace/events/asoc.h>
 #define NAME_SIZE	32
 #ifdef CONFIG_DEBUG_FS
 struct dentry *snd_soc_debugfs_root;
 EXPORT_SYMBOL_GPL(snd_soc_debugfs_root);
 #endif
 static DEFINE_MUTEX(client_mutex);
 static LIST_HEAD(platform_list);
 static LIST_HEAD(codec_list);
 static LIST_HEAD(component_list);
 /*
  * This is a timeout to do a DAPM powerdown after a stream is closed().
  * It can be used to eliminate pops between different playback streams, e.g.
  * between two audio tracks.
  */
 static int pmdown_time = 5000;
 module_param(pmdown_time, int, 0);
 MODULE_PARM_DESC(pmdown_time, "DAPM stream powerdown time (msecs)");
 /* returns the minimum number of bytes needed to represent
  * a particular given value */
 static int min_bytes_needed(unsigned long val)
 {
 	int c = 0;
 	int i;
 	for (i = (sizeof val * 8) - 1; i >= 0; --i, ++c)
 		if (val & (1UL << i))
 			break;
 	c = (sizeof val * 8) - c;
 	if (!c || (c % 8))
 		c = (c + 8) / 8;
 	else
 		c /= 8;
 	return c;
 }
 /* fill buf which is 'len' bytes with a formatted
  * string of the form 'reg: value\n' */
 static int format_register_str(struct snd_soc_codec *codec,
 			       unsigned int reg, char *buf, size_t len)
 {
 	int wordsize = min_bytes_needed(codec->driver->reg_cache_size) * 2;
 	int regsize = codec->driver->reg_word_size * 2;
 	int ret;
 	char tmpbuf[len + 1];
 	char regbuf[regsize + 1];
 	/* since tmpbuf is allocated on the stack, warn the callers if they
 	 * try to abuse this function */
 	WARN_ON(len > 63);
 	/* +2 for ': ' and + 1 for '\n' */
 	if (wordsize + regsize + 2 + 1 != len)
 		return -EINVAL;
 	ret = snd_soc_read(codec, reg);
 	if (ret < 0) {
 		memset(regbuf, 'X', regsize);
 		regbuf[regsize] = '\0';
 	} else {
 		snprintf(regbuf, regsize + 1, "%.*x", regsize, ret);
 	}
 	/* prepare the buffer */
 	snprintf(tmpbuf, len + 1, "%.*x: %s\n", wordsize, reg, regbuf);
 	/* copy it back to the caller without the '\0' */
 	memcpy(buf, tmpbuf, len);
 	return 0;
 }
 /* codec register dump */
 static ssize_t soc_codec_reg_show(struct snd_soc_codec *codec, char *buf,
 				  size_t count, loff_t pos)
 {
 	int i, step = 1;
 	int wordsize, regsize;
 	int len;
 	size_t total = 0;
 	loff_t p = 0;
 	wordsize = min_bytes_needed(codec->driver->reg_cache_size) * 2;
 	regsize = codec->driver->reg_word_size * 2;
 	len = wordsize + regsize + 2 + 1;
 	if (!codec->driver->reg_cache_size)
 		return 0;
 	if (codec->driver->reg_cache_step)
 		step = codec->driver->reg_cache_step;
 	for (i = 0; i < codec->driver->reg_cache_size; i += step) {
 		/* only support larger than PAGE_SIZE bytes debugfs
 		 * entries for the default case */
 		if (p >= pos) {
 			if (total + len >= count - 1)
 				break;
 			format_register_str(codec, i, buf + total, len);
 			total += len;
 		}
 		p += len;
 	}
 	total = min(total, count - 1);
 	return total;
 }
 static ssize_t codec_reg_show(struct device *dev,
 	struct device_attribute *attr, char *buf)
 {
 	struct snd_soc_pcm_runtime *rtd = dev_get_drvdata(dev);
 	return soc_codec_reg_show(rtd->codec, buf, PAGE_SIZE, 0);
 }
 static DEVICE_ATTR(codec_reg, 0444, codec_reg_show, NULL);
 static ssize_t pmdown_time_show(struct device *dev,
 				struct device_attribute *attr, char *buf)
 {
 	struct snd_soc_pcm_runtime *rtd = dev_get_drvdata(dev);
 	return sprintf(buf, "%ld\n", rtd->pmdown_time);
 }
 static ssize_t pmdown_time_set(struct device *dev,
 			       struct device_attribute *attr,
 			       const char *buf, size_t count)
 {
 	struct snd_soc_pcm_runtime *rtd = dev_get_drvdata(dev);
 	int ret;
 	ret = kstrtol(buf, 10, &rtd->pmdown_time);
 	if (ret)
 		return ret;
 	return count;
 }
 static DEVICE_ATTR(pmdown_time, 0644, pmdown_time_show, pmdown_time_set);
 #ifdef CONFIG_DEBUG_FS
 static ssize_t codec_reg_read_file(struct file *file, char __user *user_buf,
 				   size_t count, loff_t *ppos)
 {
 	ssize_t ret;
 	struct snd_soc_codec *codec = file->private_data;
 	char *buf;
 	if (*ppos < 0 || !count)
 		return -EINVAL;
 	buf = kmalloc(count, GFP_KERNEL);
 	if (!buf)
 		return -ENOMEM;
 	ret = soc_codec_reg_show(codec, buf, count, *ppos);
 	if (ret >= 0) {
 		if (copy_to_user(user_buf, buf, ret)) {
 			kfree(buf);
 			return -EFAULT;
 		}
 		*ppos += ret;
 	}
 	kfree(buf);
 	return ret;
 }
 static ssize_t codec_reg_write_file(struct file *file,
 		const char __user *user_buf, size_t count, loff_t *ppos)
 {
 	char buf[32];
 	size_t buf_size;
 	char *start = buf;
 	unsigned long reg, value;
 	struct snd_soc_codec *codec = file->private_data;
 	int ret;
 	buf_size = min(count, (sizeof(buf)-1));
 	if (copy_from_user(buf, user_buf, buf_size))
 		return -EFAULT;
 	buf[buf_size] = 0;
 	while (*start == ' ')
 		start++;
 	reg = simple_strtoul(start, &start, 16);
 	while (*start == ' ')
 		start++;
 	ret = kstrtoul(start, 16, &value);
 	if (ret)
 		return ret;
 	/* Userspace has been fiddling around behind the kernel's back */
 	add_taint(TAINT_USER, LOCKDEP_NOW_UNRELIABLE);
 	snd_soc_write(codec, reg, value);
 	return buf_size;
 }
 static const struct file_operations codec_reg_fops = {
 	.open = simple_open,
 	.read = codec_reg_read_file,
 	.write = codec_reg_write_file,
 	.llseek = default_llseek,
 };
 static void soc_init_component_debugfs(struct snd_soc_component *component)
 {
 	if (component->debugfs_prefix) {
 		char *name;
 		name = kasprintf(GFP_KERNEL, "%s:%s",
 			component->debugfs_prefix, component->name);
 		if (name) {
 			component->debugfs_root = debugfs_create_dir(name,
 				component->card->debugfs_card_root);
 			kfree(name);
 		}
 	} else {
 		component->debugfs_root = debugfs_create_dir(component->name,
 				component->card->debugfs_card_root);
 	}
 	if (!component->debugfs_root) {
 		dev_warn(component->dev,
 			"ASoC: Failed to create component debugfs directory\n");
 		return;
 	}
 	snd_soc_dapm_debugfs_init(snd_soc_component_get_dapm(component),
 		component->debugfs_root);
 	if (component->init_debugfs)
 		component->init_debugfs(component);
 }
 static void soc_cleanup_component_debugfs(struct snd_soc_component *component)
 {
 	debugfs_remove_recursive(component->debugfs_root);
 }
 static void soc_init_codec_debugfs(struct snd_soc_component *component)
 {
 	struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
 	codec->debugfs_reg = debugfs_create_file("codec_reg", 0644,
 						 codec->component.debugfs_root,
 						 codec, &codec_reg_fops);
 	if (!codec->debugfs_reg)
 		dev_warn(codec->dev,
 			"ASoC: Failed to create codec register debugfs file\n");
 }
 static ssize_t codec_list_read_file(struct file *file, char __user *user_buf,
 				    size_t count, loff_t *ppos)
 {
 	char *buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
 	ssize_t len, ret = 0;
 	struct snd_soc_codec *codec;
 	if (!buf)
 		return -ENOMEM;
 	list_for_each_entry(codec, &codec_list, list) {
 		len = snprintf(buf + ret, PAGE_SIZE - ret, "%s\n",
 			       codec->component.name);
 		if (len >= 0)
 			ret += len;
 		if (ret > PAGE_SIZE) {
 			ret = PAGE_SIZE;
 			break;
 		}
 	}
 	if (ret >= 0)
 		ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
 	kfree(buf);
 	return ret;
 }
 static const struct file_operations codec_list_fops = {
 	.read = codec_list_read_file,
 	.llseek = default_llseek,/* read accesses f_pos */
 };
 static ssize_t dai_list_read_file(struct file *file, char __user *user_buf,
 				  size_t count, loff_t *ppos)
 {
 	char *buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
 	ssize_t len, ret = 0;
 	struct snd_soc_component *component;
 	struct snd_soc_dai *dai;
 	if (!buf)
 		return -ENOMEM;
 	list_for_each_entry(component, &component_list, list) {
 		list_for_each_entry(dai, &component->dai_list, list) {
 			len = snprintf(buf + ret, PAGE_SIZE - ret, "%s\n",
 				dai->name);
 			if (len >= 0)
 				ret += len;
 			if (ret > PAGE_SIZE) {
 				ret = PAGE_SIZE;
 				break;
 			}
 		}
 	}
 	ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
 	kfree(buf);
 	return ret;
 }
 static const struct file_operations dai_list_fops = {
 	.read = dai_list_read_file,
 	.llseek = default_llseek,/* read accesses f_pos */
 };
 static ssize_t platform_list_read_file(struct file *file,
 				       char __user *user_buf,
 				       size_t count, loff_t *ppos)
 {
 	char *buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
 	ssize_t len, ret = 0;
 	struct snd_soc_platform *platform;
 	if (!buf)
 		return -ENOMEM;
 	list_for_each_entry(platform, &platform_list, list) {
 		len = snprintf(buf + ret, PAGE_SIZE - ret, "%s\n",
 			       platform->component.name);
 		if (len >= 0)
 			ret += len;
 		if (ret > PAGE_SIZE) {
 			ret = PAGE_SIZE;
 			break;
 		}
 	}
 	ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
 	kfree(buf);
 	return ret;
 }
 static const struct file_operations platform_list_fops = {
 	.read = platform_list_read_file,
 	.llseek = default_llseek,/* read accesses f_pos */
 };
 static void soc_init_card_debugfs(struct snd_soc_card *card)
 {
 	card->debugfs_card_root = debugfs_create_dir(card->name,
 						     snd_soc_debugfs_root);
 	if (!card->debugfs_card_root) {
 		dev_warn(card->dev,
 			 "ASoC: Failed to create card debugfs directory\n");
 		return;
 	}
 	card->debugfs_pop_time = debugfs_create_u32("dapm_pop_time", 0644,
 						    card->debugfs_card_root,
 						    &card->pop_time);
 	if (!card->debugfs_pop_time)
 		dev_warn(card->dev,
 		       "ASoC: Failed to create pop time debugfs file\n");
 }
 static void soc_cleanup_card_debugfs(struct snd_soc_card *card)
 {
 	debugfs_remove_recursive(card->debugfs_card_root);
 }
 #else
 #define soc_init_codec_debugfs NULL
 static inline void soc_init_component_debugfs(
 	struct snd_soc_component *component)
 {
 }
 static inline void soc_cleanup_component_debugfs(
 	struct snd_soc_component *component)
 {
 }
 static inline void soc_init_card_debugfs(struct snd_soc_card *card)
 {
 }
 static inline void soc_cleanup_card_debugfs(struct snd_soc_card *card)
 {
 }
 #endif
 struct snd_pcm_substream *snd_soc_get_dai_substream(struct snd_soc_card *card,
 		const char *dai_link, int stream)
 {
 	int i;
 	for (i = 0; i < card->num_links; i++) {
 		if (card->rtd[i].dai_link->no_pcm &&
 			!strcmp(card->rtd[i].dai_link->name, dai_link))
 			return card->rtd[i].pcm->streams[stream].substream;
 	}
 	dev_dbg(card->dev, "ASoC: failed to find dai link %s\n", dai_link);
 	return NULL;
 }
 EXPORT_SYMBOL_GPL(snd_soc_get_dai_substream);
 struct snd_soc_pcm_runtime *snd_soc_get_pcm_runtime(struct snd_soc_card *card,
 		const char *dai_link)
 {
 	int i;
 	for (i = 0; i < card->num_links; i++) {
 		if (!strcmp(card->rtd[i].dai_link->name, dai_link))
 			return &card->rtd[i];
 	}
 	dev_dbg(card->dev, "ASoC: failed to find rtd %s\n", dai_link);
 	return NULL;
 }
 EXPORT_SYMBOL_GPL(snd_soc_get_pcm_runtime);
 static void codec2codec_close_delayed_work(struct work_struct *work)
 {
 	/* Currently nothing to do for c2c links
 	 * Since c2c links are internal nodes in the DAPM graph and
 	 * don't interface with the outside world or application layer
 	 * we don't have to do any special handling on close.
 	 */
 }
 #ifdef CONFIG_PM_SLEEP
 /* powers down audio subsystem for suspend */
 int snd_soc_suspend(struct device *dev)
 {
 	struct snd_soc_card *card = dev_get_drvdata(dev);
 	struct snd_soc_codec *codec;
 	int i, j;
 	/* If the card is not initialized yet there is nothing to do */
 	if (!card->instantiated)
 		return 0;
 	/* Due to the resume being scheduled into a workqueue we could
 	* suspend before that's finished - wait for it to complete.
 	 */
 	snd_power_lock(card->snd_card);
 	snd_power_wait(card->snd_card, SNDRV_CTL_POWER_D0);
 	snd_power_unlock(card->snd_card);
 	/* we're going to block userspace touching us until resume completes */
 	snd_power_change_state(card->snd_card, SNDRV_CTL_POWER_D3hot);
 	/* mute any active DACs */
 	for (i = 0; i < card->num_rtd; i++) {
 		if (card->rtd[i].dai_link->ignore_suspend)
 			continue;
 		for (j = 0; j < card->rtd[i].num_codecs; j++) {
 			struct snd_soc_dai *dai = card->rtd[i].codec_dais[j];
 			struct snd_soc_dai_driver *drv = dai->driver;
 			if (drv->ops->digital_mute && dai->playback_active)
 				drv->ops->digital_mute(dai, 1);
 		}
 	}
 	/* suspend all pcms */
 	for (i = 0; i < card->num_rtd; i++) {
 		if (card->rtd[i].dai_link->ignore_suspend)
 			continue;
 		snd_pcm_suspend_all(card->rtd[i].pcm);
 	}
 	if (card->suspend_pre)
 		card->suspend_pre(card);
 	for (i = 0; i < card->num_rtd; i++) {
 		struct snd_soc_dai *cpu_dai = card->rtd[i].cpu_dai;
 		if (card->rtd[i].dai_link->ignore_suspend)
 			continue;
 		if (cpu_dai->driver->suspend && !cpu_dai->driver->bus_control)
 			cpu_dai->driver->suspend(cpu_dai);
 	}
 	/* close any waiting streams and save state */
 	for (i = 0; i < card->num_rtd; i++) {
 		struct snd_soc_dai **codec_dais = card->rtd[i].codec_dais;
 		flush_delayed_work(&card->rtd[i].delayed_work);
 		for (j = 0; j < card->rtd[i].num_codecs; j++) {
 			codec_dais[j]->codec->dapm.suspend_bias_level =
 					codec_dais[j]->codec->dapm.bias_level;
 		}
 	}
 	for (i = 0; i < card->num_rtd; i++) {
 		if (card->rtd[i].dai_link->ignore_suspend)
 			continue;
 		snd_soc_dapm_stream_event(&card->rtd[i],
 					  SNDRV_PCM_STREAM_PLAYBACK,
 					  SND_SOC_DAPM_STREAM_SUSPEND);
 		snd_soc_dapm_stream_event(&card->rtd[i],
 					  SNDRV_PCM_STREAM_CAPTURE,
 					  SND_SOC_DAPM_STREAM_SUSPEND);
 	}
 	/* Recheck all endpoints too, their state is affected by suspend */
 	dapm_mark_endpoints_dirty(card);
 	snd_soc_dapm_sync(&card->dapm);
 	/* suspend all CODECs */
 	list_for_each_entry(codec, &card->codec_dev_list, card_list) {
 		/* If there are paths active then the CODEC will be held with
 		 * bias _ON and should not be suspended. */
 		if (!codec->suspended) {
 			switch (codec->dapm.bias_level) {
 			case SND_SOC_BIAS_STANDBY:
 				/*
 				 * If the CODEC is capable of idle
 				 * bias off then being in STANDBY
 				 * means it's doing something,
 				 * otherwise fall through.
 				 */
 				if (codec->dapm.idle_bias_off) {
 					dev_dbg(codec->dev,
 						"ASoC: idle_bias_off CODEC on over suspend\n");
 					break;
 				}
 			case SND_SOC_BIAS_OFF:
 				if (codec->driver->suspend)
 					codec->driver->suspend(codec);
 				codec->suspended = 1;
 				if (codec->component.regmap)
 					regcache_mark_dirty(codec->component.regmap);
 				/* deactivate pins to sleep state */
 				pinctrl_pm_select_sleep_state(codec->dev);
 				break;
 			default:
 				dev_dbg(codec->dev,
 					"ASoC: CODEC is on over suspend\n");
 				break;
 			}
 		}
 	}
 	for (i = 0; i < card->num_rtd; i++) {
 		struct snd_soc_dai *cpu_dai = card->rtd[i].cpu_dai;
 		if (card->rtd[i].dai_link->ignore_suspend)
 			continue;
 		if (cpu_dai->driver->suspend && cpu_dai->driver->bus_control)
 			cpu_dai->driver->suspend(cpu_dai);
 		/* deactivate pins to sleep state */
 		pinctrl_pm_select_sleep_state(cpu_dai->dev);
 	}
 	if (card->suspend_post)
 		card->suspend_post(card);
 	return 0;
 }
 EXPORT_SYMBOL_GPL(snd_soc_suspend);
 /* deferred resume work, so resume can complete before we finished
  * setting our codec back up, which can be very slow on I2C
  */
 static void soc_resume_deferred(struct work_struct *work)
 {
 	struct snd_soc_card *card =
 			container_of(work, struct snd_soc_card, deferred_resume_work);
 	struct snd_soc_codec *codec;
 	int i, j;
 	/* our power state is still SNDRV_CTL_POWER_D3hot from suspend time,
 	 * so userspace apps are blocked from touching us
 	 */
 	dev_dbg(card->dev, "ASoC: starting resume work\n");
 	/* Bring us up into D2 so that DAPM starts enabling things */
 	snd_power_change_state(card->snd_card, SNDRV_CTL_POWER_D2);
 	if (card->resume_pre)
 		card->resume_pre(card);
 	/* resume control bus DAIs */
 	for (i = 0; i < card->num_rtd; i++) {
 		struct snd_soc_dai *cpu_dai = card->rtd[i].cpu_dai;
 		if (card->rtd[i].dai_link->ignore_suspend)
 			continue;
 		if (cpu_dai->driver->resume && cpu_dai->driver->bus_control)
 			cpu_dai->driver->resume(cpu_dai);
 	}
 	list_for_each_entry(codec, &card->codec_dev_list, card_list) {
 		/* If the CODEC was idle over suspend then it will have been
 		 * left with bias OFF or STANDBY and suspended so we must now
 		 * resume.  Otherwise the suspend was suppressed.
 		 */
 		if (codec->suspended) {
 			switch (codec->dapm.bias_level) {
 			case SND_SOC_BIAS_STANDBY:
 			case SND_SOC_BIAS_OFF:
 				if (codec->driver->resume)
 					codec->driver->resume(codec);
 				codec->suspended = 0;
 				break;
 			default:
 				dev_dbg(codec->dev,
 					"ASoC: CODEC was on over suspend\n");
 				break;
 			}
 		}
 	}
 	for (i = 0; i < card->num_rtd; i++) {
 		if (card->rtd[i].dai_link->ignore_suspend)
 			continue;
 		snd_soc_dapm_stream_event(&card->rtd[i],
 					  SNDRV_PCM_STREAM_PLAYBACK,
 					  SND_SOC_DAPM_STREAM_RESUME);
 		snd_soc_dapm_stream_event(&card->rtd[i],
 					  SNDRV_PCM_STREAM_CAPTURE,
 					  SND_SOC_DAPM_STREAM_RESUME);
 	}
 	/* unmute any active DACs */
 	for (i = 0; i < card->num_rtd; i++) {
 		if (card->rtd[i].dai_link->ignore_suspend)
 			continue;
 		for (j = 0; j < card->rtd[i].num_codecs; j++) {
 			struct snd_soc_dai *dai = card->rtd[i].codec_dais[j];
 			struct snd_soc_dai_driver *drv = dai->driver;
 			if (drv->ops->digital_mute && dai->playback_active)
 				drv->ops->digital_mute(dai, 0);
 		}
 	}
 	for (i = 0; i < card->num_rtd; i++) {
 		struct snd_soc_dai *cpu_dai = card->rtd[i].cpu_dai;
 		if (card->rtd[i].dai_link->ignore_suspend)
 			continue;
 		if (cpu_dai->driver->resume && !cpu_dai->driver->bus_control)
 			cpu_dai->driver->resume(cpu_dai);
 	}
 	if (card->resume_post)
 		card->resume_post(card);
 	dev_dbg(card->dev, "ASoC: resume work completed\n");
 	/* userspace can access us now we are back as we were before */
 	snd_power_change_state(card->snd_card, SNDRV_CTL_POWER_D0);
 	/* Recheck all endpoints too, their state is affected by suspend */
 	dapm_mark_endpoints_dirty(card);
 	snd_soc_dapm_sync(&card->dapm);
 }
 /* powers up audio subsystem after a suspend */
 int snd_soc_resume(struct device *dev)
 {
 	struct snd_soc_card *card = dev_get_drvdata(dev);
 	bool bus_control = false;
 	int i;
 	/* If the card is not initialized yet there is nothing to do */
 	if (!card->instantiated)
 		return 0;
 	/* activate pins from sleep state */
 	for (i = 0; i < card->num_rtd; i++) {
 		struct snd_soc_pcm_runtime *rtd = &card->rtd[i];
 		struct snd_soc_dai **codec_dais = rtd->codec_dais;
 		struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
 		int j;
 		if (cpu_dai->active)
 			pinctrl_pm_select_default_state(cpu_dai->dev);
 		for (j = 0; j < rtd->num_codecs; j++) {
 			struct snd_soc_dai *codec_dai = codec_dais[j];
 			if (codec_dai->active)
 				pinctrl_pm_select_default_state(codec_dai->dev);
 		}
 	}
 	/*
 	 * DAIs that also act as the control bus master might have other drivers
 	 * hanging off them so need to resume immediately. Other drivers don't
 	 * have that problem and may take a substantial amount of time to resume
 	 * due to I/O costs and anti-pop so handle them out of line.
 	 */
 	for (i = 0; i < card->num_rtd; i++) {
 		struct snd_soc_dai *cpu_dai = card->rtd[i].cpu_dai;
 		bus_control |= cpu_dai->driver->bus_control;
 	}
 	if (bus_control) {
 		dev_dbg(dev, "ASoC: Resuming control bus master immediately\n");
 		soc_resume_deferred(&card->deferred_resume_work);
 	} else {
 		dev_dbg(dev, "ASoC: Scheduling resume work\n");
 		if (!schedule_work(&card->deferred_resume_work))
 			dev_err(dev, "ASoC: resume work item may be lost\n");
 	}
 	return 0;
 }
 EXPORT_SYMBOL_GPL(snd_soc_resume);
 #else
 #define snd_soc_suspend NULL
 #define snd_soc_resume NULL
 #endif
 static const struct snd_soc_dai_ops null_dai_ops = {
 };
 static struct snd_soc_component *soc_find_component(
 	const struct device_node *of_node, const char *name)
 {
 	struct snd_soc_component *component;
 	list_for_each_entry(component, &component_list, list) {
 		if (of_node) {
 			if (component->dev->of_node == of_node)
 				return component;
 		} else if (strcmp(component->name, name) == 0) {
 			return component;
 		}
 	}
 	return NULL;
 }
 static struct snd_soc_dai *snd_soc_find_dai(
 	const struct snd_soc_dai_link_component *dlc)
 {
 	struct snd_soc_component *component;
 	struct snd_soc_dai *dai;
 	/* Find CPU DAI from registered DAIs*/
 	list_for_each_entry(component, &component_list, list) {
 		if (dlc->of_node && component->dev->of_node != dlc->of_node)
 			continue;
 		if (dlc->name && strcmp(component->name, dlc->name))
 			continue;
 		list_for_each_entry(dai, &component->dai_list, list) {
 			if (dlc->dai_name && strcmp(dai->name, dlc->dai_name))
 				continue;
 			return dai;
 		}
 	}
 	return NULL;
 }
 static int soc_bind_dai_link(struct snd_soc_card *card, int num)
 {
 	struct snd_soc_dai_link *dai_link = &card->dai_link[num];
 	struct snd_soc_pcm_runtime *rtd = &card->rtd[num];
 	struct snd_soc_dai_link_component *codecs = dai_link->codecs;
 	struct snd_soc_dai_link_component cpu_dai_component;
 	struct snd_soc_dai **codec_dais = rtd->codec_dais;
 	struct snd_soc_platform *platform;
 	const char *platform_name;
 	int i;
 	dev_dbg(card->dev, "ASoC: binding %s at idx %d\n", dai_link->name, num);
 	cpu_dai_component.name = dai_link->cpu_name;
 	cpu_dai_component.of_node = dai_link->cpu_of_node;
 	cpu_dai_component.dai_name = dai_link->cpu_dai_name;
 	rtd->cpu_dai = snd_soc_find_dai(&cpu_dai_component);
 	if (!rtd->cpu_dai) {
 		dev_err(card->dev, "ASoC: CPU DAI %s not registered\n",
 			dai_link->cpu_dai_name);
 		return -EPROBE_DEFER;
 	}
 	rtd->num_codecs = dai_link->num_codecs;
 	/* Find CODEC from registered CODECs */
 	for (i = 0; i < rtd->num_codecs; i++) {
 		codec_dais[i] = snd_soc_find_dai(&codecs[i]);
 		if (!codec_dais[i]) {
 			dev_err(card->dev, "ASoC: CODEC DAI %s not registered\n",
 				codecs[i].dai_name);
 			return -EPROBE_DEFER;
 		}
 	}
 	/* Single codec links expect codec and codec_dai in runtime data */
 	rtd->codec_dai = codec_dais[0];
 	rtd->codec = rtd->codec_dai->codec;
 	/* if there's no platform we match on the empty platform */
 	platform_name = dai_link->platform_name;
 	if (!platform_name && !dai_link->platform_of_node)
 		platform_name = "snd-soc-dummy";
 	/* find one from the set of registered platforms */
 	list_for_each_entry(platform, &platform_list, list) {
 		if (dai_link->platform_of_node) {
 			if (platform->dev->of_node !=
 			    dai_link->platform_of_node)
 				continue;
 		} else {
 			if (strcmp(platform->component.name, platform_name))
 				continue;
 		}
 		rtd->platform = platform;
 	}
 	if (!rtd->platform) {
 		dev_err(card->dev, "ASoC: platform %s not registered\n",
 			dai_link->platform_name);
 		return -EPROBE_DEFER;
 	}
 	card->num_rtd++;
 	return 0;
 }
 static void soc_remove_component(struct snd_soc_component *component)
 {
 	if (!component->probed)
 		return;
 	/* This is a HACK and will be removed soon */
 	if (component->codec)
 		list_del(&component->codec->card_list);
 	if (component->remove)
 		component->remove(component);
 	snd_soc_dapm_free(snd_soc_component_get_dapm(component));
 	soc_cleanup_component_debugfs(component);
 	component->probed = 0;
 	module_put(component->dev->driver->owner);
 }
 static void soc_remove_dai(struct snd_soc_dai *dai, int order)
 {
 	int err;
 	if (dai && dai->probed &&
 			dai->driver->remove_order == order) {
 		if (dai->driver->remove) {
 			err = dai->driver->remove(dai);
 			if (err < 0)
 				dev_err(dai->dev,
 					"ASoC: failed to remove %s: %d\n",
 					dai->name, err);
 		}
 		dai->probed = 0;
 	}
 }
 static void soc_remove_link_dais(struct snd_soc_card *card, int num, int order)
 {
 	struct snd_soc_pcm_runtime *rtd = &card->rtd[num];
 	int i;
 	/* unregister the rtd device */
 	if (rtd->dev_registered) {
 		device_remove_file(rtd->dev, &dev_attr_pmdown_time);
 		device_remove_file(rtd->dev, &dev_attr_codec_reg);
 		device_unregister(rtd->dev);
 		rtd->dev_registered = 0;
 	}
 	/* remove the CODEC DAI */
 	for (i = 0; i < rtd->num_codecs; i++)
 		soc_remove_dai(rtd->codec_dais[i], order);
 	soc_remove_dai(rtd->cpu_dai, order);
 }
 static void soc_remove_link_components(struct snd_soc_card *card, int num,
 				       int order)
 {
 	struct snd_soc_pcm_runtime *rtd = &card->rtd[num];
 	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
 	struct snd_soc_platform *platform = rtd->platform;
 	struct snd_soc_component *component;
 	int i;
 	/* remove the platform */
 	if (platform && platform->component.driver->remove_order == order)
 		soc_remove_component(&platform->component);
 	/* remove the CODEC-side CODEC */
 	for (i = 0; i < rtd->num_codecs; i++) {
 		component = rtd->codec_dais[i]->component;
 		if (component->driver->remove_order == order)
 			soc_remove_component(component);
 	}
 	/* remove any CPU-side CODEC */
 	if (cpu_dai) {
 		if (cpu_dai->component->driver->remove_order == order)
 			soc_remove_component(cpu_dai->component);
 	}
 }
 static void soc_remove_dai_links(struct snd_soc_card *card)
 {
 	int dai, order;
 	for (order = SND_SOC_COMP_ORDER_FIRST; order <= SND_SOC_COMP_ORDER_LAST;
 			order++) {
 		for (dai = 0; dai < card->num_rtd; dai++)
 			soc_remove_link_dais(card, dai, order);
 	}
 	for (order = SND_SOC_COMP_ORDER_FIRST; order <= SND_SOC_COMP_ORDER_LAST;
 			order++) {
 		for (dai = 0; dai < card->num_rtd; dai++)
 			soc_remove_link_components(card, dai, order);
 	}
 	card->num_rtd = 0;
 }
 static void soc_set_name_prefix(struct snd_soc_card *card,
 				struct snd_soc_component *component)
 {
 	int i;
 	if (card->codec_conf == NULL)
 		return;
 	for (i = 0; i < card->num_configs; i++) {
 		struct snd_soc_codec_conf *map = &card->codec_conf[i];
 		if (map->of_node && component->dev->of_node != map->of_node)
 			continue;
 		if (map->dev_name && strcmp(component->name, map->dev_name))
 			continue;
 		component->name_prefix = map->name_prefix;
 		break;
 	}
 }
 static int soc_probe_component(struct snd_soc_card *card,
 	struct snd_soc_component *component)
 {
 	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
 	struct snd_soc_dai *dai;
 	int ret;
 	if (component->probed)
 		return 0;
 	component->card = card;
 	dapm->card = card;
 	soc_set_name_prefix(card, component);
 	if (!try_module_get(component->dev->driver->owner))
 		return -ENODEV;
 	soc_init_component_debugfs(component);
 	if (component->dapm_widgets) {
 		ret = snd_soc_dapm_new_controls(dapm, component->dapm_widgets,
 			component->num_dapm_widgets);
 		if (ret != 0) {
 			dev_err(component->dev,
 				"Failed to create new controls %d\n", ret);
 			goto err_probe;
 		}
 	}
 	list_for_each_entry(dai, &component->dai_list, list) {
 		ret = snd_soc_dapm_new_dai_widgets(dapm, dai);
 		if (ret != 0) {
 			dev_err(component->dev,
 				"Failed to create DAI widgets %d\n", ret);
 			goto err_probe;
 		}
 	}
 	if (component->probe) {
 		ret = component->probe(component);
 		if (ret < 0) {
 			dev_err(component->dev,
 				"ASoC: failed to probe component %d\n", ret);
 			goto err_probe;
 		}
 		WARN(dapm->idle_bias_off &&
 			dapm->bias_level != SND_SOC_BIAS_OFF,
 			"codec %s can not start from non-off bias with idle_bias_off==1\n",
 			component->name);
 	}
 	if (component->controls)
 		snd_soc_add_component_controls(component, component->controls,
 				     component->num_controls);
 	if (component->dapm_routes)
 		snd_soc_dapm_add_routes(dapm, component->dapm_routes,
 					component->num_dapm_routes);
 	component->probed = 1;
 	list_add(&dapm->list, &card->dapm_list);
 	/* This is a HACK and will be removed soon */
 	if (component->codec)
 		list_add(&component->codec->card_list, &card->codec_dev_list);
 	return 0;
 err_probe:
 	soc_cleanup_component_debugfs(component);
 	module_put(component->dev->driver->owner);
 	return ret;
 }
 static void rtd_release(struct device *dev)
 {
 	kfree(dev);
 }
 static int soc_post_component_init(struct snd_soc_pcm_runtime *rtd,
 	const char *name)
 {
 	int ret = 0;
 	/* register the rtd device */
 	rtd->dev = kzalloc(sizeof(struct device), GFP_KERNEL);
 	if (!rtd->dev)
 		return -ENOMEM;
 	device_initialize(rtd->dev);
 	rtd->dev->parent = rtd->card->dev;
 	rtd->dev->release = rtd_release;
 	dev_set_name(rtd->dev, "%s", name);
 	dev_set_drvdata(rtd->dev, rtd);
 	mutex_init(&rtd->pcm_mutex);
 	INIT_LIST_HEAD(&rtd->dpcm[SNDRV_PCM_STREAM_PLAYBACK].be_clients);
 	INIT_LIST_HEAD(&rtd->dpcm[SNDRV_PCM_STREAM_CAPTURE].be_clients);
 	INIT_LIST_HEAD(&rtd->dpcm[SNDRV_PCM_STREAM_PLAYBACK].fe_clients);
 	INIT_LIST_HEAD(&rtd->dpcm[SNDRV_PCM_STREAM_CAPTURE].fe_clients);
 	ret = device_add(rtd->dev);
 	if (ret < 0) {
 		/* calling put_device() here to free the rtd->dev */
 		put_device(rtd->dev);
 		dev_err(rtd->card->dev,
 			"ASoC: failed to register runtime device: %d\n", ret);
 		return ret;
 	}
 	rtd->dev_registered = 1;
 	if (rtd->codec) {
 		/* add DAPM sysfs entries for this codec */
 		ret = snd_soc_dapm_sys_add(rtd->dev);
 		if (ret < 0)
 			dev_err(rtd->dev,
 				"ASoC: failed to add codec dapm sysfs entries: %d\n",
 				ret);
 		/* add codec sysfs entries */
 		ret = device_create_file(rtd->dev, &dev_attr_codec_reg);
 		if (ret < 0)
 			dev_err(rtd->dev,
 				"ASoC: failed to add codec sysfs files: %d\n",
 				ret);
 	}
 	return 0;
 }
 static int soc_probe_link_components(struct snd_soc_card *card, int num,
 				     int order)
 {
 	struct snd_soc_pcm_runtime *rtd = &card->rtd[num];
 	struct snd_soc_platform *platform = rtd->platform;
 	struct snd_soc_component *component;
 	int i, ret;
 	/* probe the CPU-side component, if it is a CODEC */
 	component = rtd->cpu_dai->component;
 	if (component->driver->probe_order == order) {
 		ret = soc_probe_component(card, component);
 		if (ret < 0)
 			return ret;
 	}
 	/* probe the CODEC-side components */
 	for (i = 0; i < rtd->num_codecs; i++) {
 		component = rtd->codec_dais[i]->component;
 		if (component->driver->probe_order == order) {
 			ret = soc_probe_component(card, component);
 			if (ret < 0)
 				return ret;
 		}
 	}
 	/* probe the platform */
 	if (platform->component.driver->probe_order == order) {
 		ret = soc_probe_component(card, &platform->component);
 		if (ret < 0)
 			return ret;
 	}
 	return 0;
 }
 static int soc_probe_dai(struct snd_soc_dai *dai, int order)
 {
 	int ret;
 	if (!dai->probed && dai->driver->probe_order == order) {
 		if (dai->driver->probe) {
 			ret = dai->driver->probe(dai);
 			if (ret < 0) {
 				dev_err(dai->dev,
 					"ASoC: failed to probe DAI %s: %d\n",
 					dai->name, ret);
 				return ret;
 			}
 		}
 		dai->probed = 1;
 	}
 	return 0;
 }
 static int soc_link_dai_widgets(struct snd_soc_card *card,
 				struct snd_soc_dai_link *dai_link,
 				struct snd_soc_pcm_runtime *rtd)
 {
 	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
 	struct snd_soc_dai *codec_dai = rtd->codec_dai;
 	struct snd_soc_dapm_widget *play_w, *capture_w;
 	int ret;
 	if (rtd->num_codecs > 1)
 		dev_warn(card->dev, "ASoC: Multiple codecs not supported yet\n");
 	/* link the DAI widgets */
 	play_w = codec_dai->playback_widget;
 	capture_w = cpu_dai->capture_widget;
 	if (play_w && capture_w) {
 		ret = snd_soc_dapm_new_pcm(card, dai_link->params,
 					   capture_w, play_w);
 		if (ret != 0) {
 			dev_err(card->dev, "ASoC: Can't link %s to %s: %d\n",
 				play_w->name, capture_w->name, ret);
 			return ret;
 		}
 	}
 	play_w = cpu_dai->playback_widget;
 	capture_w = codec_dai->capture_widget;
 	if (play_w && capture_w) {
 		ret = snd_soc_dapm_new_pcm(card, dai_link->params,
 					   capture_w, play_w);
 		if (ret != 0) {
 			dev_err(card->dev, "ASoC: Can't link %s to %s: %d\n",
 				play_w->name, capture_w->name, ret);
 			return ret;
 		}
 	}
 	return 0;
 }
 static int soc_probe_link_dais(struct snd_soc_card *card, int num, int order)
 {
 	struct snd_soc_dai_link *dai_link = &card->dai_link[num];
 	struct snd_soc_pcm_runtime *rtd = &card->rtd[num];
 	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
 	int i, ret;
 	dev_dbg(card->dev, "ASoC: probe %s dai link %d late %d\n",
 			card->name, num, order);
 	/* set default power off timeout */
 	rtd->pmdown_time = pmdown_time;
 	ret = soc_probe_dai(cpu_dai, order);
 	if (ret)
 		return ret;
 	/* probe the CODEC DAI */
 	for (i = 0; i < rtd->num_codecs; i++) {
 		ret = soc_probe_dai(rtd->codec_dais[i], order);
 		if (ret)
 			return ret;
 	}
 	/* complete DAI probe during last probe */
 	if (order != SND_SOC_COMP_ORDER_LAST)
 		return 0;
 	/* do machine specific initialization */
 	if (dai_link->init) {
 		ret = dai_link->init(rtd);
 		if (ret < 0) {
 			dev_err(card->dev, "ASoC: failed to init %s: %d\n",
 				dai_link->name, ret);
 			return ret;
 		}
 	}
 	ret = soc_post_component_init(rtd, dai_link->name);
 	if (ret)
 		return ret;
 #ifdef CONFIG_DEBUG_FS
 	/* add DPCM sysfs entries */
 	if (dai_link->dynamic) {
 		ret = soc_dpcm_debugfs_add(rtd);
 		if (ret < 0) {
 			dev_err(rtd->dev,
 				"ASoC: failed to add dpcm sysfs entries: %d\n",
 				ret);
 			return ret;
 		}
 	}
 #endif
 	ret = device_create_file(rtd->dev, &dev_attr_pmdown_time);
 	if (ret < 0)
 		dev_warn(rtd->dev, "ASoC: failed to add pmdown_time sysfs: %d\n",
 			ret);
 	if (cpu_dai->driver->compress_dai) {
 		/*create compress_device"*/
 		ret = soc_new_compress(rtd, num);
 		if (ret < 0) {
 			dev_err(card->dev, "ASoC: can't create compress %s\n",
 					 dai_link->stream_name);
 			return ret;
 		}
 	} else {
 		if (!dai_link->params) {
 			/* create the pcm */
 			ret = soc_new_pcm(rtd, num);
 			if (ret < 0) {
 				dev_err(card->dev, "ASoC: can't create pcm %s :%d\n",
 				       dai_link->stream_name, ret);
 				return ret;
 			}
 		} else {
 			INIT_DELAYED_WORK(&rtd->delayed_work,
 						codec2codec_close_delayed_work);
 			/* link the DAI widgets */
 			ret = soc_link_dai_widgets(card, dai_link, rtd);
 			if (ret)
 				return ret;
 		}
 	}
 	return 0;
 }
 static int soc_bind_aux_dev(struct snd_soc_card *card, int num)
 {
 	struct snd_soc_pcm_runtime *rtd = &card->rtd_aux[num];
 	struct snd_soc_aux_dev *aux_dev = &card->aux_dev[num];
 	const char *name = aux_dev->codec_name;
 	rtd->component = soc_find_component(aux_dev->codec_of_node, name);
 	if (!rtd->component) {
 		if (aux_dev->codec_of_node)
 			name = of_node_full_name(aux_dev->codec_of_node);
 		dev_err(card->dev, "ASoC: %s not registered\n", name);
 		return -EPROBE_DEFER;
 	}
 	/*
 	 * Some places still reference rtd->codec, so we have to keep that
 	 * initialized if the component is a CODEC. Once all those references
 	 * have been removed, this code can be removed as well.
 	 */
 	 rtd->codec = rtd->component->codec;
 	return 0;
 }
 static int soc_probe_aux_dev(struct snd_soc_card *card, int num)
 {
 	struct snd_soc_pcm_runtime *rtd = &card->rtd_aux[num];
 	struct snd_soc_aux_dev *aux_dev = &card->aux_dev[num];
 	int ret;
 	ret = soc_probe_component(card, rtd->component);
 	if (ret < 0)
 		return ret;
 	/* do machine specific initialization */
 	if (aux_dev->init) {
 		ret = aux_dev->init(rtd->component);
 		if (ret < 0) {
 			dev_err(card->dev, "ASoC: failed to init %s: %d\n",
 				aux_dev->name, ret);
 			return ret;
 		}
 	}
 	return soc_post_component_init(rtd, aux_dev->name);
 }
 static void soc_remove_aux_dev(struct snd_soc_card *card, int num)
 {
 	struct snd_soc_pcm_runtime *rtd = &card->rtd_aux[num];
 	struct snd_soc_component *component = rtd->component;
 	/* unregister the rtd device */
 	if (rtd->dev_registered) {
 		device_remove_file(rtd->dev, &dev_attr_codec_reg);
 		device_unregister(rtd->dev);
 		rtd->dev_registered = 0;
 	}
 	if (component && component->probed)
 		soc_remove_component(component);
 }
 static int snd_soc_init_codec_cache(struct snd_soc_codec *codec)
 {
 	int ret;
 	if (codec->cache_init)
 		return 0;
 	ret = snd_soc_cache_init(codec);
 	if (ret < 0) {
 		dev_err(codec->dev,
 			"ASoC: Failed to set cache compression type: %d\n",
 			ret);
 		return ret;
 	}
 	codec->cache_init = 1;
 	return 0;
 }
 static int snd_soc_instantiate_card(struct snd_soc_card *card)
 {
 	struct snd_soc_codec *codec;
 	struct snd_soc_dai_link *dai_link;
 	int ret, i, order, dai_fmt;
 	mutex_lock_nested(&card->mutex, SND_SOC_CARD_CLASS_INIT);
 	/* bind DAIs */
 	for (i = 0; i < card->num_links; i++) {
 		ret = soc_bind_dai_link(card, i);
 		if (ret != 0)
 			goto base_error;
 	}
 	/* bind aux_devs too */
 	for (i = 0; i < card->num_aux_devs; i++) {
 		ret = soc_bind_aux_dev(card, i);
 		if (ret != 0)
 			goto base_error;
 	}
 	/* initialize the register cache for each available codec */
 	list_for_each_entry(codec, &codec_list, list) {
 		if (codec->cache_init)
 			continue;
 		ret = snd_soc_init_codec_cache(codec);
 		if (ret < 0)
 			goto base_error;
 	}
 	/* card bind complete so register a sound card */
 	ret = snd_card_new(card->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
 			card->owner, 0, &card->snd_card);
 	if (ret < 0) {
 		dev_err(card->dev,
 			"ASoC: can't create sound card for card %s: %d\n",
 			card->name, ret);
 		goto base_error;
 	}
 	card->dapm.bias_level = SND_SOC_BIAS_OFF;
 	card->dapm.dev = card->dev;
 	card->dapm.card = card;
 	list_add(&card->dapm.list, &card->dapm_list);
 #ifdef CONFIG_DEBUG_FS
 	snd_soc_dapm_debugfs_init(&card->dapm, card->debugfs_card_root);
 #endif
 #ifdef CONFIG_PM_SLEEP
 	/* deferred resume work */
 	INIT_WORK(&card->deferred_resume_work, soc_resume_deferred);
 #endif
 	if (card->dapm_widgets)
 		snd_soc_dapm_new_controls(&card->dapm, card->dapm_widgets,
 					  card->num_dapm_widgets);
 	/* initialise the sound card only once */
 	if (card->probe) {
 		ret = card->probe(card);
 		if (ret < 0)
 			goto card_probe_error;
 	}
 	/* probe all components used by DAI links on this card */
 	for (order = SND_SOC_COMP_ORDER_FIRST; order <= SND_SOC_COMP_ORDER_LAST;
 			order++) {
 		for (i = 0; i < card->num_links; i++) {
 			ret = soc_probe_link_components(card, i, order);
 			if (ret < 0) {
 				dev_err(card->dev,
 					"ASoC: failed to instantiate card %d\n",
 					ret);
 				goto probe_dai_err;
 			}
 		}
 	}
 	/* probe all DAI links on this card */
 	for (order = SND_SOC_COMP_ORDER_FIRST; order <= SND_SOC_COMP_ORDER_LAST;
 			order++) {
 		for (i = 0; i < card->num_links; i++) {
 			ret = soc_probe_link_dais(card, i, order);
 			if (ret < 0) {
 				dev_err(card->dev,
 					"ASoC: failed to instantiate card %d\n",
 					ret);
 				goto probe_dai_err;
 			}
 		}
 	}
 	for (i = 0; i < card->num_aux_devs; i++) {
 		ret = soc_probe_aux_dev(card, i);
 		if (ret < 0) {
 			dev_err(card->dev,
 				"ASoC: failed to add auxiliary devices %d\n",
 				ret);
 			goto probe_aux_dev_err;
 		}
 	}
 	snd_soc_dapm_link_dai_widgets(card);
 	snd_soc_dapm_connect_dai_link_widgets(card);
 	if (card->controls)
 		snd_soc_add_card_controls(card, card->controls, card->num_controls);
 	if (card->dapm_routes)
 		snd_soc_dapm_add_routes(&card->dapm, card->dapm_routes,
 					card->num_dapm_routes);
 	for (i = 0; i < card->num_links; i++) {
 		struct snd_soc_pcm_runtime *rtd = &card->rtd[i];
 		dai_link = &card->dai_link[i];
 		dai_fmt = dai_link->dai_fmt;
 		if (dai_fmt) {
 			struct snd_soc_dai **codec_dais = rtd->codec_dais;
 			int j;
 			for (j = 0; j < rtd->num_codecs; j++) {
 				struct snd_soc_dai *codec_dai = codec_dais[j];
 				ret = snd_soc_dai_set_fmt(codec_dai, dai_fmt);
 				if (ret != 0 && ret != -ENOTSUPP)
 					dev_warn(codec_dai->dev,
 						 "ASoC: Failed to set DAI format: %d\n",
 						 ret);
 			}
 		}
 		/* If this is a regular CPU link there will be a platform */
 		if (dai_fmt &&
 		    (dai_link->platform_name || dai_link->platform_of_node)) {
 			ret = snd_soc_dai_set_fmt(card->rtd[i].cpu_dai,
 						  dai_fmt);
 			if (ret != 0 && ret != -ENOTSUPP)
 				dev_warn(card->rtd[i].cpu_dai->dev,
 					 "ASoC: Failed to set DAI format: %d\n",
 					 ret);
 		} else if (dai_fmt) {
 			/* Flip the polarity for the "CPU" end */
 			dai_fmt &= ~SND_SOC_DAIFMT_MASTER_MASK;
 			switch (dai_link->dai_fmt &
 				SND_SOC_DAIFMT_MASTER_MASK) {
 			case SND_SOC_DAIFMT_CBM_CFM:
 				dai_fmt |= SND_SOC_DAIFMT_CBS_CFS;
 				break;
 			case SND_SOC_DAIFMT_CBM_CFS:
 				dai_fmt |= SND_SOC_DAIFMT_CBS_CFM;
 				break;
 			case SND_SOC_DAIFMT_CBS_CFM:
 				dai_fmt |= SND_SOC_DAIFMT_CBM_CFS;
 				break;
 			case SND_SOC_DAIFMT_CBS_CFS:
 				dai_fmt |= SND_SOC_DAIFMT_CBM_CFM;
 				break;
 			}
 			ret = snd_soc_dai_set_fmt(card->rtd[i].cpu_dai,
 						  dai_fmt);
 			if (ret != 0 && ret != -ENOTSUPP)
 				dev_warn(card->rtd[i].cpu_dai->dev,
 					 "ASoC: Failed to set DAI format: %d\n",
 					 ret);
 		}
 	}
 	snprintf(card->snd_card->shortname, sizeof(card->snd_card->shortname),
 		 "%s", card->name);
 	snprintf(card->snd_card->longname, sizeof(card->snd_card->longname),
 		 "%s", card->long_name ? card->long_name : card->name);
 	snprintf(card->snd_card->driver, sizeof(card->snd_card->driver),
 		 "%s", card->driver_name ? card->driver_name : card->name);
 	for (i = 0; i < ARRAY_SIZE(card->snd_card->driver); i++) {
 		switch (card->snd_card->driver[i]) {
 		case '_':
 		case '-':
 		case '\0':
 			break;
 		default:
 			if (!isalnum(card->snd_card->driver[i]))
 				card->snd_card->driver[i] = '_';
 			break;
 		}
 	}
 	if (card->late_probe) {
 		ret = card->late_probe(card);
 		if (ret < 0) {
 			dev_err(card->dev, "ASoC: %s late_probe() failed: %d\n",
 				card->name, ret);
 			goto probe_aux_dev_err;
 		}
 	}
 	if (card->fully_routed)
 		snd_soc_dapm_auto_nc_pins(card);
 	snd_soc_dapm_new_widgets(card);
 	ret = snd_card_register(card->snd_card);
 	if (ret < 0) {
 		dev_err(card->dev, "ASoC: failed to register soundcard %d\n",
 				ret);
 		goto probe_aux_dev_err;
 	}
 	card->instantiated = 1;
 	snd_soc_dapm_sync(&card->dapm);
 	mutex_unlock(&card->mutex);
 	return 0;
 probe_aux_dev_err:
 	for (i = 0; i < card->num_aux_devs; i++)
 		soc_remove_aux_dev(card, i);
 probe_dai_err:
 	soc_remove_dai_links(card);
 card_probe_error:
 	if (card->remove)
 		card->remove(card);
 	snd_card_free(card->snd_card);
 base_error:
 	mutex_unlock(&card->mutex);
 	return ret;
 }
 /* probes a new socdev */
 static int soc_probe(struct platform_device *pdev)
 {
 	struct snd_soc_card *card = platform_get_drvdata(pdev);
 	/*
 	 * no card, so machine driver should be registering card
 	 * we should not be here in that case so ret error
 	 */
 	if (!card)
 		return -EINVAL;
 	dev_warn(&pdev->dev,
 		 "ASoC: machine %s should use snd_soc_register_card()\n",
 		 card->name);
 	/* Bodge while we unpick instantiation */
 	card->dev = &pdev->dev;
 	return snd_soc_register_card(card);
 }
 static int soc_cleanup_card_resources(struct snd_soc_card *card)
 {
 	int i;
 	/* make sure any delayed work runs */
 	for (i = 0; i < card->num_rtd; i++) {
 		struct snd_soc_pcm_runtime *rtd = &card->rtd[i];
 		flush_delayed_work(&rtd->delayed_work);
 	}
 	/* remove auxiliary devices */
 	for (i = 0; i < card->num_aux_devs; i++)
 		soc_remove_aux_dev(card, i);
 	/* remove and free each DAI */
 	soc_remove_dai_links(card);
 	soc_cleanup_card_debugfs(card);
 	/* remove the card */
 	if (card->remove)
 		card->remove(card);
 	snd_soc_dapm_free(&card->dapm);
 	snd_card_free(card->snd_card);
 	return 0;
 }
 /* removes a socdev */
 static int soc_remove(struct platform_device *pdev)
 {
 	struct snd_soc_card *card = platform_get_drvdata(pdev);
 	snd_soc_unregister_card(card);
 	return 0;
 }
 int snd_soc_poweroff(struct device *dev)
 {
 	struct snd_soc_card *card = dev_get_drvdata(dev);
 	int i;
 	if (!card->instantiated)
 		return 0;
 	/* Flush out pmdown_time work - we actually do want to run it
 	 * now, we're shutting down so no imminent restart. */
 	for (i = 0; i < card->num_rtd; i++) {
 		struct snd_soc_pcm_runtime *rtd = &card->rtd[i];
 		flush_delayed_work(&rtd->delayed_work);
 	}
 	snd_soc_dapm_shutdown(card);
 	/* deactivate pins to sleep state */
 	for (i = 0; i < card->num_rtd; i++) {
 		struct snd_soc_pcm_runtime *rtd = &card->rtd[i];
 		struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
 		int j;
 		pinctrl_pm_select_sleep_state(cpu_dai->dev);
 		for (j = 0; j < rtd->num_codecs; j++) {
 			struct snd_soc_dai *codec_dai = rtd->codec_dais[j];
 			pinctrl_pm_select_sleep_state(codec_dai->dev);
 		}
 	}
 	return 0;
 }
 EXPORT_SYMBOL_GPL(snd_soc_poweroff);
 const struct dev_pm_ops snd_soc_pm_ops = {
 	.suspend = snd_soc_suspend,
 	.resume = snd_soc_resume,
 	.freeze = snd_soc_suspend,
 	.thaw = snd_soc_resume,
 	.poweroff = snd_soc_poweroff,
 	.restore = snd_soc_resume,
 };
 EXPORT_SYMBOL_GPL(snd_soc_pm_ops);
 /* ASoC platform driver */
 static struct platform_driver soc_driver = {
 	.driver		= {
 		.name		= "soc-audio",
 		.pm		= &snd_soc_pm_ops,
 	},
 	.probe		= soc_probe,
 	.remove		= soc_remove,
 };
 /**
  * snd_soc_cnew - create new control
  * @_template: control template
  * @data: control private data
  * @long_name: control long name
  * @prefix: control name prefix
  *
  * Create a new mixer control from a template control.
  *
  * Returns 0 for success, else error.
  */
 struct snd_kcontrol *snd_soc_cnew(const struct snd_kcontrol_new *_template,
 				  void *data, const char *long_name,
 				  const char *prefix)
 {
 	struct snd_kcontrol_new template;
 	struct snd_kcontrol *kcontrol;
 	char *name = NULL;
 	memcpy(&template, _template, sizeof(template));
 	template.index = 0;
 	if (!long_name)
 		long_name = template.name;
 	if (prefix) {
 		name = kasprintf(GFP_KERNEL, "%s %s", prefix, long_name);
 		if (!name)
 			return NULL;
 		template.name = name;
 	} else {
 		template.name = long_name;
 	}
 	kcontrol = snd_ctl_new1(&template, data);
 	kfree(name);
 	return kcontrol;
 }
 EXPORT_SYMBOL_GPL(snd_soc_cnew);
 static int snd_soc_add_controls(struct snd_card *card, struct device *dev,
 	const struct snd_kcontrol_new *controls, int num_controls,
 	const char *prefix, void *data)
 {
 	int err, i;
 	for (i = 0; i < num_controls; i++) {
 		const struct snd_kcontrol_new *control = &controls[i];
 		err = snd_ctl_add(card, snd_soc_cnew(control, data,
 						     control->name, prefix));
 		if (err < 0) {
 			dev_err(dev, "ASoC: Failed to add %s: %d\n",
 				control->name, err);
 			return err;
 		}
 	}
 	return 0;
 }
 struct snd_kcontrol *snd_soc_card_get_kcontrol(struct snd_soc_card *soc_card,
 					       const char *name)
 {
 	struct snd_card *card = soc_card->snd_card;
 	struct snd_kcontrol *kctl;
 	if (unlikely(!name))
 		return NULL;
 	list_for_each_entry(kctl, &card->controls, list)
 		if (!strncmp(kctl->id.name, name, sizeof(kctl->id.name)))
 			return kctl;
 	return NULL;
 }
 EXPORT_SYMBOL_GPL(snd_soc_card_get_kcontrol);
 /**
  * snd_soc_add_component_controls - Add an array of controls to a component.
  *
  * @component: Component to add controls to
  * @controls: Array of controls to add
  * @num_controls: Number of elements in the array
  *
  * Return: 0 for success, else error.
  */
 int snd_soc_add_component_controls(struct snd_soc_component *component,
 	const struct snd_kcontrol_new *controls, unsigned int num_controls)
 {
 	struct snd_card *card = component->card->snd_card;
 	return snd_soc_add_controls(card, component->dev, controls,
 			num_controls, component->name_prefix, component);
 }
 EXPORT_SYMBOL_GPL(snd_soc_add_component_controls);
 /**
  * snd_soc_add_codec_controls - add an array of controls to a codec.
  * Convenience function to add a list of controls. Many codecs were
  * duplicating this code.
  *
  * @codec: codec to add controls to
  * @controls: array of controls to add
  * @num_controls: number of elements in the array
  *
  * Return 0 for success, else error.
  */
 int snd_soc_add_codec_controls(struct snd_soc_codec *codec,
 	const struct snd_kcontrol_new *controls, unsigned int num_controls)
 {
 	return snd_soc_add_component_controls(&codec->component, controls,
 		num_controls);
 }
 EXPORT_SYMBOL_GPL(snd_soc_add_codec_controls);
 /**
  * snd_soc_add_platform_controls - add an array of controls to a platform.
  * Convenience function to add a list of controls.
  *
  * @platform: platform to add controls to
  * @controls: array of controls to add
  * @num_controls: number of elements in the array
  *
  * Return 0 for success, else error.
  */
 int snd_soc_add_platform_controls(struct snd_soc_platform *platform,
 	const struct snd_kcontrol_new *controls, unsigned int num_controls)
 {
 	return snd_soc_add_component_controls(&platform->component, controls,
 		num_controls);
 }
 EXPORT_SYMBOL_GPL(snd_soc_add_platform_controls);
 /**
  * snd_soc_add_card_controls - add an array of controls to a SoC card.
  * Convenience function to add a list of controls.
  *
  * @soc_card: SoC card to add controls to
  * @controls: array of controls to add
  * @num_controls: number of elements in the array
  *
  * Return 0 for success, else error.
  */
 int snd_soc_add_card_controls(struct snd_soc_card *soc_card,
 	const struct snd_kcontrol_new *controls, int num_controls)
 {
 	struct snd_card *card = soc_card->snd_card;
 	return snd_soc_add_controls(card, soc_card->dev, controls, num_controls,
 			NULL, soc_card);
 }
 EXPORT_SYMBOL_GPL(snd_soc_add_card_controls);
 /**
  * snd_soc_add_dai_controls - add an array of controls to a DAI.
  * Convienience function to add a list of controls.
  *
  * @dai: DAI to add controls to
  * @controls: array of controls to add
  * @num_controls: number of elements in the array
  *
  * Return 0 for success, else error.
  */
 int snd_soc_add_dai_controls(struct snd_soc_dai *dai,
 	const struct snd_kcontrol_new *controls, int num_controls)
 {
 	struct snd_card *card = dai->component->card->snd_card;
 	return snd_soc_add_controls(card, dai->dev, controls, num_controls,
 			NULL, dai);
 }
 EXPORT_SYMBOL_GPL(snd_soc_add_dai_controls);
 /**
  * snd_soc_dai_set_sysclk - configure DAI system or master clock.
  * @dai: DAI
  * @clk_id: DAI specific clock ID
  * @freq: new clock frequency in Hz
  * @dir: new clock direction - input/output.
  *
  * Configures the DAI master (MCLK) or system (SYSCLK) clocking.
  */
 int snd_soc_dai_set_sysclk(struct snd_soc_dai *dai, int clk_id,
 	unsigned int freq, int dir)
 {
 	if (dai->driver && dai->driver->ops->set_sysclk)
 		return dai->driver->ops->set_sysclk(dai, clk_id, freq, dir);
 	else if (dai->codec && dai->codec->driver->set_sysclk)
 		return dai->codec->driver->set_sysclk(dai->codec, clk_id, 0,
 						      freq, dir);
 	else
 		return -ENOTSUPP;
 }
 EXPORT_SYMBOL_GPL(snd_soc_dai_set_sysclk);
 /**
  * snd_soc_codec_set_sysclk - configure CODEC system or master clock.
  * @codec: CODEC
  * @clk_id: DAI specific clock ID
  * @source: Source for the clock
  * @freq: new clock frequency in Hz
  * @dir: new clock direction - input/output.
  *
  * Configures the CODEC master (MCLK) or system (SYSCLK) clocking.
  */
 int snd_soc_codec_set_sysclk(struct snd_soc_codec *codec, int clk_id,
 			     int source, unsigned int freq, int dir)
 {
 	if (codec->driver->set_sysclk)
 		return codec->driver->set_sysclk(codec, clk_id, source,
 						 freq, dir);
 	else
 		return -ENOTSUPP;
 }
 EXPORT_SYMBOL_GPL(snd_soc_codec_set_sysclk);
 /**
  * snd_soc_dai_set_clkdiv - configure DAI clock dividers.
  * @dai: DAI
  * @div_id: DAI specific clock divider ID
  * @div: new clock divisor.
  *
  * Configures the clock dividers. This is used to derive the best DAI bit and
  * frame clocks from the system or master clock. It's best to set the DAI bit
  * and frame clocks as low as possible to save system power.
  */
 int snd_soc_dai_set_clkdiv(struct snd_soc_dai *dai,
 	int div_id, int div)
 {
 	if (dai->driver && dai->driver->ops->set_clkdiv)
 		return dai->driver->ops->set_clkdiv(dai, div_id, div);
 	else
 		return -EINVAL;
 }
 EXPORT_SYMBOL_GPL(snd_soc_dai_set_clkdiv);
 /**
  * snd_soc_dai_set_pll - configure DAI PLL.
  * @dai: DAI
  * @pll_id: DAI specific PLL ID
  * @source: DAI specific source for the PLL
  * @freq_in: PLL input clock frequency in Hz
  * @freq_out: requested PLL output clock frequency in Hz
  *
  * Configures and enables PLL to generate output clock based on input clock.
  */
 int snd_soc_dai_set_pll(struct snd_soc_dai *dai, int pll_id, int source,
 	unsigned int freq_in, unsigned int freq_out)
 {
 	if (dai->driver && dai->driver->ops->set_pll)
 		return dai->driver->ops->set_pll(dai, pll_id, source,
 					 freq_in, freq_out);
 	else if (dai->codec && dai->codec->driver->set_pll)
 		return dai->codec->driver->set_pll(dai->codec, pll_id, source,
 						   freq_in, freq_out);
 	else
 		return -EINVAL;
 }
 EXPORT_SYMBOL_GPL(snd_soc_dai_set_pll);
 /*
  * snd_soc_codec_set_pll - configure codec PLL.
  * @codec: CODEC
  * @pll_id: DAI specific PLL ID
  * @source: DAI specific source for the PLL
  * @freq_in: PLL input clock frequency in Hz
  * @freq_out: requested PLL output clock frequency in Hz
  *
  * Configures and enables PLL to generate output clock based on input clock.
  */
 int snd_soc_codec_set_pll(struct snd_soc_codec *codec, int pll_id, int source,
 			  unsigned int freq_in, unsigned int freq_out)
 {
 	if (codec->driver->set_pll)
 		return codec->driver->set_pll(codec, pll_id, source,
 					      freq_in, freq_out);
 	else
 		return -EINVAL;
 }
 EXPORT_SYMBOL_GPL(snd_soc_codec_set_pll);
 /**
  * snd_soc_dai_set_bclk_ratio - configure BCLK to sample rate ratio.
  * @dai: DAI
  * @ratio Ratio of BCLK to Sample rate.
  *
  * Configures the DAI for a preset BCLK to sample rate ratio.
  */
 int snd_soc_dai_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
 {
 	if (dai->driver && dai->driver->ops->set_bclk_ratio)
 		return dai->driver->ops->set_bclk_ratio(dai, ratio);
 	else
 		return -EINVAL;
 }
 EXPORT_SYMBOL_GPL(snd_soc_dai_set_bclk_ratio);
 /**
  * snd_soc_dai_set_fmt - configure DAI hardware audio format.
  * @dai: DAI
  * @fmt: SND_SOC_DAIFMT_ format value.
  *
  * Configures the DAI hardware format and clocking.
  */
 int snd_soc_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 {
 	if (dai->driver == NULL)
 		return -EINVAL;
 	if (dai->driver->ops->set_fmt == NULL)
 		return -ENOTSUPP;
 	return dai->driver->ops->set_fmt(dai, fmt);
 }
 EXPORT_SYMBOL_GPL(snd_soc_dai_set_fmt);
 /**
  * snd_soc_xlate_tdm_slot - generate tx/rx slot mask.
  * @slots: Number of slots in use.
  * @tx_mask: bitmask representing active TX slots.
  * @rx_mask: bitmask representing active RX slots.
  *
  * Generates the TDM tx and rx slot default masks for DAI.
  */
 static int snd_soc_xlate_tdm_slot_mask(unsigned int slots,
 					  unsigned int *tx_mask,
 					  unsigned int *rx_mask)
 {
 	if (*tx_mask || *rx_mask)
 		return 0;
 	if (!slots)
 		return -EINVAL;
 	*tx_mask = (1 << slots) - 1;
 	*rx_mask = (1 << slots) - 1;
 	return 0;
 }
 /**
  * snd_soc_dai_set_tdm_slot - configure DAI TDM.
  * @dai: DAI
  * @tx_mask: bitmask representing active TX slots.
  * @rx_mask: bitmask representing active RX slots.
  * @slots: Number of slots in use.
  * @slot_width: Width in bits for each slot.
  *
  * Configures a DAI for TDM operation. Both mask and slots are codec and DAI
  * specific.
  */
 int snd_soc_dai_set_tdm_slot(struct snd_soc_dai *dai,
 	unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
 {
 	if (dai->driver && dai->driver->ops->xlate_tdm_slot_mask)
 		dai->driver->ops->xlate_tdm_slot_mask(slots,
 						&tx_mask, &rx_mask);
 	else
 		snd_soc_xlate_tdm_slot_mask(slots, &tx_mask, &rx_mask);
 	dai->tx_mask = tx_mask;
 	dai->rx_mask = rx_mask;
 	if (dai->driver && dai->driver->ops->set_tdm_slot)
 		return dai->driver->ops->set_tdm_slot(dai, tx_mask, rx_mask,
 				slots, slot_width);
 	else
 		return -ENOTSUPP;
 }
 EXPORT_SYMBOL_GPL(snd_soc_dai_set_tdm_slot);
 /**
  * snd_soc_dai_set_channel_map - configure DAI audio channel map
  * @dai: DAI
  * @tx_num: how many TX channels
  * @tx_slot: pointer to an array which imply the TX slot number channel
  *           0~num-1 uses
  * @rx_num: how many RX channels
  * @rx_slot: pointer to an array which imply the RX slot number channel
  *           0~num-1 uses
  *
  * configure the relationship between channel number and TDM slot number.
  */
 int snd_soc_dai_set_channel_map(struct snd_soc_dai *dai,
 	unsigned int tx_num, unsigned int *tx_slot,
 	unsigned int rx_num, unsigned int *rx_slot)
 {
 	if (dai->driver && dai->driver->ops->set_channel_map)
 		return dai->driver->ops->set_channel_map(dai, tx_num, tx_slot,
 			rx_num, rx_slot);
 	else
 		return -EINVAL;
 }
 EXPORT_SYMBOL_GPL(snd_soc_dai_set_channel_map);
 /**
  * snd_soc_dai_set_tristate - configure DAI system or master clock.
  * @dai: DAI
  * @tristate: tristate enable
  *
  * Tristates the DAI so that others can use it.
  */
 int snd_soc_dai_set_tristate(struct snd_soc_dai *dai, int tristate)
 {
 	if (dai->driver && dai->driver->ops->set_tristate)
 		return dai->driver->ops->set_tristate(dai, tristate);
 	else
 		return -EINVAL;
 }
 EXPORT_SYMBOL_GPL(snd_soc_dai_set_tristate);
 /**
  * snd_soc_dai_digital_mute - configure DAI system or master clock.
  * @dai: DAI
  * @mute: mute enable
  * @direction: stream to mute
  *
  * Mutes the DAI DAC.
  */
 int snd_soc_dai_digital_mute(struct snd_soc_dai *dai, int mute,
 			     int direction)
 {
 	if (!dai->driver)
 		return -ENOTSUPP;
 	if (dai->driver->ops->mute_stream)
 		return dai->driver->ops->mute_stream(dai, mute, direction);
 	else if (direction == SNDRV_PCM_STREAM_PLAYBACK &&
 		 dai->driver->ops->digital_mute)
 		return dai->driver->ops->digital_mute(dai, mute);
 	else
 		return -ENOTSUPP;
 }
 EXPORT_SYMBOL_GPL(snd_soc_dai_digital_mute);
 static int snd_soc_init_multicodec(struct snd_soc_card *card,
 				   struct snd_soc_dai_link *dai_link)
 {
 	/* Legacy codec/codec_dai link is a single entry in multicodec */
 	if (dai_link->codec_name || dai_link->codec_of_node ||
 	    dai_link->codec_dai_name) {
 		dai_link->num_codecs = 1;
 		dai_link->codecs = devm_kzalloc(card->dev,
 				sizeof(struct snd_soc_dai_link_component),
 				GFP_KERNEL);
 		if (!dai_link->codecs)
 			return -ENOMEM;
 		dai_link->codecs[0].name = dai_link->codec_name;
 		dai_link->codecs[0].of_node = dai_link->codec_of_node;
 		dai_link->codecs[0].dai_name = dai_link->codec_dai_name;
 	}
 	if (!dai_link->codecs) {
 		dev_err(card->dev, "ASoC: DAI link has no CODECs\n");
 		return -EINVAL;
 	}
 	return 0;
 }
 /**
  * snd_soc_register_card - Register a card with the ASoC core
  *
  * @card: Card to register
  *
  */
 int snd_soc_register_card(struct snd_soc_card *card)
 {
 	int i, j, ret;
 	if (!card->name || !card->dev)
 		return -EINVAL;
 	for (i = 0; i < card->num_links; i++) {
 		struct snd_soc_dai_link *link = &card->dai_link[i];
 		ret = snd_soc_init_multicodec(card, link);
 		if (ret) {
 			dev_err(card->dev, "ASoC: failed to init multicodec\n");
 			return ret;
 		}
 		for (j = 0; j < link->num_codecs; j++) {
 			/*
 			 * Codec must be specified by 1 of name or OF node,
 			 * not both or neither.
 			 */
 			if (!!link->codecs[j].name ==
 			    !!link->codecs[j].of_node) {
 				dev_err(card->dev, "ASoC: Neither/both codec name/of_node are set for %s\n",
 					link->name);
 				return -EINVAL;
 			}
 			/* Codec DAI name must be specified */
 			if (!link->codecs[j].dai_name) {
 				dev_err(card->dev, "ASoC: codec_dai_name not set for %s\n",
 					link->name);
 				return -EINVAL;
 			}
 		}
 		/*
 		 * Platform may be specified by either name or OF node, but
 		 * can be left unspecified, and a dummy platform will be used.
 		 */
 		if (link->platform_name && link->platform_of_node) {
 			dev_err(card->dev,
 				"ASoC: Both platform name/of_node are set for %s\n",
 				link->name);
 			return -EINVAL;
 		}
 		/*
 		 * CPU device may be specified by either name or OF node, but
 		 * can be left unspecified, and will be matched based on DAI
 		 * name alone..
 		 */
 		if (link->cpu_name && link->cpu_of_node) {
 			dev_err(card->dev,
 				"ASoC: Neither/both cpu name/of_node are set for %s\n",
 				link->name);
 			return -EINVAL;
 		}
 		/*
 		 * At least one of CPU DAI name or CPU device name/node must be
 		 * specified
 		 */
 		if (!link->cpu_dai_name &&
 		    !(link->cpu_name || link->cpu_of_node)) {
 			dev_err(card->dev,
 				"ASoC: Neither cpu_dai_name nor cpu_name/of_node are set for %s\n",
 				link->name);
 			return -EINVAL;
 		}
 	}
 	dev_set_drvdata(card->dev, card);
 	snd_soc_initialize_card_lists(card);
 	soc_init_card_debugfs(card);
 	card->rtd = devm_kzalloc(card->dev,
 				 sizeof(struct snd_soc_pcm_runtime) *
 				 (card->num_links + card->num_aux_devs),
 				 GFP_KERNEL);
 	if (card->rtd == NULL)
 		return -ENOMEM;
 	card->num_rtd = 0;
 	card->rtd_aux = &card->rtd[card->num_links];
 	for (i = 0; i < card->num_links; i++) {
 		card->rtd[i].card = card;
 		card->rtd[i].dai_link = &card->dai_link[i];
 		card->rtd[i].codec_dais = devm_kzalloc(card->dev,
 					sizeof(struct snd_soc_dai *) *
 					(card->rtd[i].dai_link->num_codecs),
 					GFP_KERNEL);
 		if (card->rtd[i].codec_dais == NULL)
 			return -ENOMEM;
 	}
 	for (i = 0; i < card->num_aux_devs; i++)
 		card->rtd_aux[i].card = card;
 	INIT_LIST_HEAD(&card->dapm_dirty);
 	card->instantiated = 0;
 	mutex_init(&card->mutex);
 	mutex_init(&card->dapm_mutex);
 	ret = snd_soc_instantiate_card(card);
 	if (ret != 0)
 		soc_cleanup_card_debugfs(card);
 	/* deactivate pins to sleep state */
 	for (i = 0; i < card->num_rtd; i++) {
 		struct snd_soc_pcm_runtime *rtd = &card->rtd[i];
 		struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
 		int j;
 		for (j = 0; j < rtd->num_codecs; j++) {
 			struct snd_soc_dai *codec_dai = rtd->codec_dais[j];
 			if (!codec_dai->active)
 				pinctrl_pm_select_sleep_state(codec_dai->dev);
 		}
 		if (!cpu_dai->active)
 			pinctrl_pm_select_sleep_state(cpu_dai->dev);
 	}
 	return ret;
 }
 EXPORT_SYMBOL_GPL(snd_soc_register_card);
 /**
  * snd_soc_unregister_card - Unregister a card with the ASoC core
  *
  * @card: Card to unregister
  *
  */
 int snd_soc_unregister_card(struct snd_soc_card *card)
 {
 	if (card->instantiated) {
 		card->instantiated = false;
 		snd_soc_dapm_shutdown(card);
 		soc_cleanup_card_resources(card);
 	}
 	dev_dbg(card->dev, "ASoC: Unregistered card '%s'\n", card->name);
 	return 0;
 }
 EXPORT_SYMBOL_GPL(snd_soc_unregister_card);
 /*
  * Simplify DAI link configuration by removing ".-1" from device names
  * and sanitizing names.
  */
 static char *fmt_single_name(struct device *dev, int *id)
 {
 	char *found, name[NAME_SIZE];
 	int id1, id2;
 	if (dev_name(dev) == NULL)
 		return NULL;
 	strlcpy(name, dev_name(dev), NAME_SIZE);
 	/* are we a "%s.%d" name (platform and SPI components) */
 	found = strstr(name, dev->driver->name);
 	if (found) {
 		/* get ID */
 		if (sscanf(&found[strlen(dev->driver->name)], ".%d", id) == 1) {
 			/* discard ID from name if ID == -1 */
 			if (*id == -1)
 				found[strlen(dev->driver->name)] = '\0';
 		}
 	} else {
 		/* I2C component devices are named "bus-addr"  */
 		if (sscanf(name, "%x-%x", &id1, &id2) == 2) {
 			char tmp[NAME_SIZE];
 			/* create unique ID number from I2C addr and bus */
 			*id = ((id1 & 0xffff) << 16) + id2;
 			/* sanitize component name for DAI link creation */
 			snprintf(tmp, NAME_SIZE, "%s.%s", dev->driver->name, name);
 			strlcpy(name, tmp, NAME_SIZE);
 		} else
 			*id = 0;
 	}
 	return kstrdup(name, GFP_KERNEL);
 }
 /*
  * Simplify DAI link naming for single devices with multiple DAIs by removing
  * any ".-1" and using the DAI name (instead of device name).
  */
 static inline char *fmt_multiple_name(struct device *dev,
 		struct snd_soc_dai_driver *dai_drv)
 {
 	if (dai_drv->name == NULL) {
 		dev_err(dev,
 			"ASoC: error - multiple DAI %s registered with no name\n",
 			dev_name(dev));
 		return NULL;
 	}
 	return kstrdup(dai_drv->name, GFP_KERNEL);
 }
 /**
  * snd_soc_unregister_dai - Unregister DAIs from the ASoC core
  *
  * @component: The component for which the DAIs should be unregistered
  */
 static void snd_soc_unregister_dais(struct snd_soc_component *component)
 {
 	struct snd_soc_dai *dai, *_dai;
 	list_for_each_entry_safe(dai, _dai, &component->dai_list, list) {
 		dev_dbg(component->dev, "ASoC: Unregistered DAI '%s'\n",
 			dai->name);
 		list_del(&dai->list);
 		kfree(dai->name);
 		kfree(dai);
 	}
 }
 /**
  * snd_soc_register_dais - Register a DAI with the ASoC core
  *
  * @component: The component the DAIs are registered for
  * @dai_drv: DAI driver to use for the DAIs
  * @count: Number of DAIs
  * @legacy_dai_naming: Use the legacy naming scheme and let the DAI inherit the
  *                     parent's name.
  */
 static int snd_soc_register_dais(struct snd_soc_component *component,
 	struct snd_soc_dai_driver *dai_drv, size_t count,
 	bool legacy_dai_naming)
 {
 	struct device *dev = component->dev;
 	struct snd_soc_dai *dai;
 	unsigned int i;
 	int ret;
 	dev_dbg(dev, "ASoC: dai register %s #%Zu\n", dev_name(dev), count);
 	component->dai_drv = dai_drv;
 	component->num_dai = count;
 	for (i = 0; i < count; i++) {
 		dai = kzalloc(sizeof(struct snd_soc_dai), GFP_KERNEL);
 		if (dai == NULL) {
 			ret = -ENOMEM;
 			goto err;
 		}
 		/*
 		 * Back in the old days when we still had component-less DAIs,
 		 * instead of having a static name, component-less DAIs would
 		 * inherit the name of the parent device so it is possible to
 		 * register multiple instances of the DAI. We still need to keep
 		 * the same naming style even though those DAIs are not
 		 * component-less anymore.
 		 */
 		if (count == 1 && legacy_dai_naming) {
 			dai->name = fmt_single_name(dev, &dai->id);
 		} else {
 			dai->name = fmt_multiple_name(dev, &dai_drv[i]);
 			if (dai_drv[i].id)
 				dai->id = dai_drv[i].id;
 			else
 				dai->id = i;
 		}
 		if (dai->name == NULL) {
 			kfree(dai);
 			ret = -ENOMEM;
 			goto err;
 		}
 		dai->component = component;
 		dai->dev = dev;
 		dai->driver = &dai_drv[i];
 		if (!dai->driver->ops)
 			dai->driver->ops = &null_dai_ops;
 		list_add(&dai->list, &component->dai_list);
 		dev_dbg(dev, "ASoC: Registered DAI '%s'\n", dai->name);
 	}
 	return 0;
 err:
 	snd_soc_unregister_dais(component);
 	return ret;
 }
 static void snd_soc_component_seq_notifier(struct snd_soc_dapm_context *dapm,
 	enum snd_soc_dapm_type type, int subseq)
 {
 	struct snd_soc_component *component = dapm->component;
 	component->driver->seq_notifier(component, type, subseq);
 }
 static int snd_soc_component_stream_event(struct snd_soc_dapm_context *dapm,
 	int event)
 {
 	struct snd_soc_component *component = dapm->component;
 	return component->driver->stream_event(component, event);
 }
 static int snd_soc_component_initialize(struct snd_soc_component *component,
 	const struct snd_soc_component_driver *driver, struct device *dev)
 {
 	struct snd_soc_dapm_context *dapm;
 	component->name = fmt_single_name(dev, &component->id);
 	if (!component->name) {
 		dev_err(dev, "ASoC: Failed to allocate name\n");
 		return -ENOMEM;
 	}
 	component->dev = dev;
 	component->driver = driver;
 	component->probe = component->driver->probe;
 	component->remove = component->driver->remove;
 	if (!component->dapm_ptr)
 		component->dapm_ptr = &component->dapm;
 	dapm = component->dapm_ptr;
 	dapm->dev = dev;
 	dapm->component = component;
 	dapm->bias_level = SND_SOC_BIAS_OFF;
 	dapm->idle_bias_off = true;
 	if (driver->seq_notifier)
 		dapm->seq_notifier = snd_soc_component_seq_notifier;
 	if (driver->stream_event)
 		dapm->stream_event = snd_soc_component_stream_event;
 	component->controls = driver->controls;
 	component->num_controls = driver->num_controls;
 	component->dapm_widgets = driver->dapm_widgets;
 	component->num_dapm_widgets = driver->num_dapm_widgets;
 	component->dapm_routes = driver->dapm_routes;
 	component->num_dapm_routes = driver->num_dapm_routes;
 	INIT_LIST_HEAD(&component->dai_list);
 	mutex_init(&component->io_mutex);
 	return 0;
 }
 static void snd_soc_component_setup_regmap(struct snd_soc_component *component)
 {
 	int val_bytes = regmap_get_val_bytes(component->regmap);
 	/* Errors are legitimate for non-integer byte multiples */
 	if (val_bytes > 0)
 		component->val_bytes = val_bytes;
 }
 #ifdef CONFIG_REGMAP
 /**
  * snd_soc_component_init_regmap() - Initialize regmap instance for the component
  * @component: The component for which to initialize the regmap instance
  * @regmap: The regmap instance that should be used by the component
  *
  * This function allows deferred assignment of the regmap instance that is
  * associated with the component. Only use this if the regmap instance is not
  * yet ready when the component is registered. The function must also be called
  * before the first IO attempt of the component.
  */
 void snd_soc_component_init_regmap(struct snd_soc_component *component,
 	struct regmap *regmap)
 {
 	component->regmap = regmap;
 	snd_soc_component_setup_regmap(component);
 }
 EXPORT_SYMBOL_GPL(snd_soc_component_init_regmap);
 /**
  * snd_soc_component_exit_regmap() - De-initialize regmap instance for the component
  * @component: The component for which to de-initialize the regmap instance
  *
  * Calls regmap_exit() on the regmap instance associated to the component and
  * removes the regmap instance from the component.
  *
  * This function should only be used if snd_soc_component_init_regmap() was used
  * to initialize the regmap instance.
  */
 void snd_soc_component_exit_regmap(struct snd_soc_component *component)
 {
 	regmap_exit(component->regmap);
 	component->regmap = NULL;
 }
 EXPORT_SYMBOL_GPL(snd_soc_component_exit_regmap);
 #endif
 static void snd_soc_component_add_unlocked(struct snd_soc_component *component)
 {
 	if (!component->write && !component->read) {
 		if (!component->regmap)
 			component->regmap = dev_get_regmap(component->dev, NULL);
 		if (component->regmap)
 			snd_soc_component_setup_regmap(component);
 	}
 	list_add(&component->list, &component_list);
 }
 static void snd_soc_component_add(struct snd_soc_component *component)
 {
 	mutex_lock(&client_mutex);
 	snd_soc_component_add_unlocked(component);
 	mutex_unlock(&client_mutex);
 }
 static void snd_soc_component_cleanup(struct snd_soc_component *component)
 {
 	snd_soc_unregister_dais(component);
 	kfree(component->name);
 }
 static void snd_soc_component_del_unlocked(struct snd_soc_component *component)
 {
 	list_del(&component->list);
 }
 static void snd_soc_component_del(struct snd_soc_component *component)
 {
 	mutex_lock(&client_mutex);
 	snd_soc_component_del_unlocked(component);
 	mutex_unlock(&client_mutex);
 }
 int snd_soc_register_component(struct device *dev,
 			       const struct snd_soc_component_driver *cmpnt_drv,
 			       struct snd_soc_dai_driver *dai_drv,
 			       int num_dai)
 {
 	struct snd_soc_component *cmpnt;
 	int ret;
 	cmpnt = kzalloc(sizeof(*cmpnt), GFP_KERNEL);
 	if (!cmpnt) {
 		dev_err(dev, "ASoC: Failed to allocate memory\n");
 		return -ENOMEM;
 	}
 	ret = snd_soc_component_initialize(cmpnt, cmpnt_drv, dev);
 	if (ret)
 		goto err_free;
 	cmpnt->ignore_pmdown_time = true;
 	cmpnt->registered_as_component = true;
 	ret = snd_soc_register_dais(cmpnt, dai_drv, num_dai, true);
 	if (ret < 0) {
 		dev_err(dev, "ASoC: Failed to regster DAIs: %d\n", ret);
 		goto err_cleanup;
 	}
 	snd_soc_component_add(cmpnt);
 	return 0;
 err_cleanup:
 	snd_soc_component_cleanup(cmpnt);
 err_free:
 	kfree(cmpnt);
 	return ret;
 }
 EXPORT_SYMBOL_GPL(snd_soc_register_component);
 /**
  * snd_soc_unregister_component - Unregister a component from the ASoC core
  *
  */
 void snd_soc_unregister_component(struct device *dev)
 {
 	struct snd_soc_component *cmpnt;
 	list_for_each_entry(cmpnt, &component_list, list) {
 		if (dev == cmpnt->dev && cmpnt->registered_as_component)
 			goto found;
 	}
 	return;
 found:
 	snd_soc_component_del(cmpnt);
 	snd_soc_component_cleanup(cmpnt);
 	kfree(cmpnt);
 }
 EXPORT_SYMBOL_GPL(snd_soc_unregister_component);
 static int snd_soc_platform_drv_probe(struct snd_soc_component *component)
 {
 	struct snd_soc_platform *platform = snd_soc_component_to_platform(component);
 	return platform->driver->probe(platform);
 }
 static void snd_soc_platform_drv_remove(struct snd_soc_component *component)
 {
 	struct snd_soc_platform *platform = snd_soc_component_to_platform(component);
 	platform->driver->remove(platform);
 }
 /**
  * snd_soc_add_platform - Add a platform to the ASoC core
  * @dev: The parent device for the platform
  * @platform: The platform to add
  * @platform_driver: The driver for the platform
  */
 int snd_soc_add_platform(struct device *dev, struct snd_soc_platform *platform,
 		const struct snd_soc_platform_driver *platform_drv)
 {
 	int ret;
 	ret = snd_soc_component_initialize(&platform->component,
 			&platform_drv->component_driver, dev);
 	if (ret)
 		return ret;
 	platform->dev = dev;
 	platform->driver = platform_drv;
 	if (platform_drv->probe)
 		platform->component.probe = snd_soc_platform_drv_probe;
 	if (platform_drv->remove)
 		platform->component.remove = snd_soc_platform_drv_remove;
 #ifdef CONFIG_DEBUG_FS
 	platform->component.debugfs_prefix = "platform";
 #endif
 	mutex_lock(&client_mutex);
 	snd_soc_component_add_unlocked(&platform->component);
 	list_add(&platform->list, &platform_list);
 	mutex_unlock(&client_mutex);
 	dev_dbg(dev, "ASoC: Registered platform '%s'\n",
 		platform->component.name);
 	return 0;
 }
 EXPORT_SYMBOL_GPL(snd_soc_add_platform);
 /**
  * snd_soc_register_platform - Register a platform with the ASoC core
  *
  * @platform: platform to register
  */
 int snd_soc_register_platform(struct device *dev,
 		const struct snd_soc_platform_driver *platform_drv)
 {
 	struct snd_soc_platform *platform;
 	int ret;
 	dev_dbg(dev, "ASoC: platform register %s\n", dev_name(dev));
 	platform = kzalloc(sizeof(struct snd_soc_platform), GFP_KERNEL);
 	if (platform == NULL)
 		return -ENOMEM;
 	ret = snd_soc_add_platform(dev, platform, platform_drv);
 	if (ret)
 		kfree(platform);
 	return ret;
 }
 EXPORT_SYMBOL_GPL(snd_soc_register_platform);
 /**
  * snd_soc_remove_platform - Remove a platform from the ASoC core
  * @platform: the platform to remove
  */
 void snd_soc_remove_platform(struct snd_soc_platform *platform)
 {
 	mutex_lock(&client_mutex);
 	list_del(&platform->list);
 	snd_soc_component_del_unlocked(&platform->component);
 	mutex_unlock(&client_mutex);
 	dev_dbg(platform->dev, "ASoC: Unregistered platform '%s'\n",
 		platform->component.name);
 	snd_soc_component_cleanup(&platform->component);
 }
 EXPORT_SYMBOL_GPL(snd_soc_remove_platform);
 struct snd_soc_platform *snd_soc_lookup_platform(struct device *dev)
 {
 	struct snd_soc_platform *platform;
 	list_for_each_entry(platform, &platform_list, list) {
 		if (dev == platform->dev)
 			return platform;
 	}
 	return NULL;
 }
 EXPORT_SYMBOL_GPL(snd_soc_lookup_platform);
 /**
  * snd_soc_unregister_platform - Unregister a platform from the ASoC core
  *
  * @platform: platform to unregister
  */
 void snd_soc_unregister_platform(struct device *dev)
 {
 	struct snd_soc_platform *platform;
 	platform = snd_soc_lookup_platform(dev);
 	if (!platform)
 		return;
 	snd_soc_remove_platform(platform);
 	kfree(platform);
 }
 EXPORT_SYMBOL_GPL(snd_soc_unregister_platform);
 static u64 codec_format_map[] = {
 	SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE,
 	SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE,
 	SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE,
 	SNDRV_PCM_FMTBIT_U24_LE | SNDRV_PCM_FMTBIT_U24_BE,
 	SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE,
 	SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_U32_BE,
 	SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_U24_3BE,
 	SNDRV_PCM_FMTBIT_U24_3LE | SNDRV_PCM_FMTBIT_U24_3BE,
 	SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S20_3BE,
 	SNDRV_PCM_FMTBIT_U20_3LE | SNDRV_PCM_FMTBIT_U20_3BE,
 	SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S18_3BE,
 	SNDRV_PCM_FMTBIT_U18_3LE | SNDRV_PCM_FMTBIT_U18_3BE,
 	SNDRV_PCM_FMTBIT_FLOAT_LE | SNDRV_PCM_FMTBIT_FLOAT_BE,
 	SNDRV_PCM_FMTBIT_FLOAT64_LE | SNDRV_PCM_FMTBIT_FLOAT64_BE,
 	SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE
 	| SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_BE,
 };
 /* Fix up the DAI formats for endianness: codecs don't actually see
  * the endianness of the data but we're using the CPU format
  * definitions which do need to include endianness so we ensure that
  * codec DAIs always have both big and little endian variants set.
  */
 static void fixup_codec_formats(struct snd_soc_pcm_stream *stream)
 {
 	int i;
 	for (i = 0; i < ARRAY_SIZE(codec_format_map); i++)
 		if (stream->formats & codec_format_map[i])
 			stream->formats |= codec_format_map[i];
 }
 static int snd_soc_codec_drv_probe(struct snd_soc_component *component)
 {
 	struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
 	return codec->driver->probe(codec);
 }
 static void snd_soc_codec_drv_remove(struct snd_soc_component *component)
 {
 	struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
 	codec->driver->remove(codec);
 }
 static int snd_soc_codec_drv_write(struct snd_soc_component *component,
 	unsigned int reg, unsigned int val)
 {
 	struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
 	return codec->driver->write(codec, reg, val);
 }
 static int snd_soc_codec_drv_read(struct snd_soc_component *component,
 	unsigned int reg, unsigned int *val)
 {
 	struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
 	*val = codec->driver->read(codec, reg);
 	return 0;
 }
 static int snd_soc_codec_set_bias_level(struct snd_soc_dapm_context *dapm,
 	enum snd_soc_bias_level level)
 {
 	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(dapm);
 	return codec->driver->set_bias_level(codec, level);
 }
 /**
  * snd_soc_register_codec - Register a codec with the ASoC core
  *
  * @codec: codec to register
  */
 int snd_soc_register_codec(struct device *dev,
 			   const struct snd_soc_codec_driver *codec_drv,
 			   struct snd_soc_dai_driver *dai_drv,
 			   int num_dai)
 {
 	struct snd_soc_codec *codec;
 	struct snd_soc_dai *dai;
 	int ret, i;
 	dev_dbg(dev, "codec register %s\n", dev_name(dev));
 	codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
 	if (codec == NULL)
 		return -ENOMEM;
 	codec->component.dapm_ptr = &codec->dapm;
 	codec->component.codec = codec;
 	ret = snd_soc_component_initialize(&codec->component,
 			&codec_drv->component_driver, dev);
 	if (ret)
 		goto err_free;
 	if (codec_drv->controls) {
 		codec->component.controls = codec_drv->controls;
 		codec->component.num_controls = codec_drv->num_controls;
 	}
 	if (codec_drv->dapm_widgets) {
 		codec->component.dapm_widgets = codec_drv->dapm_widgets;
 		codec->component.num_dapm_widgets = codec_drv->num_dapm_widgets;
 	}
 	if (codec_drv->dapm_routes) {
 		codec->component.dapm_routes = codec_drv->dapm_routes;
 		codec->component.num_dapm_routes = codec_drv->num_dapm_routes;
 	}
 	if (codec_drv->probe)
 		codec->component.probe = snd_soc_codec_drv_probe;
 	if (codec_drv->remove)
 		codec->component.remove = snd_soc_codec_drv_remove;
 	if (codec_drv->write)
 		codec->component.write = snd_soc_codec_drv_write;
 	if (codec_drv->read)
 		codec->component.read = snd_soc_codec_drv_read;
 	codec->component.ignore_pmdown_time = codec_drv->ignore_pmdown_time;
 	codec->dapm.idle_bias_off = codec_drv->idle_bias_off;
 	codec->dapm.suspend_bias_off = codec_drv->suspend_bias_off;
 	if (codec_drv->seq_notifier)
 		codec->dapm.seq_notifier = codec_drv->seq_notifier;
 	if (codec_drv->set_bias_level)
 		codec->dapm.set_bias_level = snd_soc_codec_set_bias_level;
 	codec->dev = dev;
 	codec->driver = codec_drv;
 	codec->component.val_bytes = codec_drv->reg_word_size;
 #ifdef CONFIG_DEBUG_FS
 	codec->component.init_debugfs = soc_init_codec_debugfs;
 	codec->component.debugfs_prefix = "codec";
 #endif
 	if (codec_drv->get_regmap)
 		codec->component.regmap = codec_drv->get_regmap(dev);
 	for (i = 0; i < num_dai; i++) {
 		fixup_codec_formats(&dai_drv[i].playback);
 		fixup_codec_formats(&dai_drv[i].capture);
 	}
 	ret = snd_soc_register_dais(&codec->component, dai_drv, num_dai, false);
 	if (ret < 0) {
 		dev_err(dev, "ASoC: Failed to regster DAIs: %d\n", ret);
 		goto err_cleanup;
 	}
 	list_for_each_entry(dai, &codec->component.dai_list, list)
 		dai->codec = codec;
 	mutex_lock(&client_mutex);
 	snd_soc_component_add_unlocked(&codec->component);
 	list_add(&codec->list, &codec_list);
 	mutex_unlock(&client_mutex);
 	dev_dbg(codec->dev, "ASoC: Registered codec '%s'\n",
 		codec->component.name);
 	return 0;
 err_cleanup:
 	snd_soc_component_cleanup(&codec->component);
 err_free:
 	kfree(codec);
 	return ret;
 }
 EXPORT_SYMBOL_GPL(snd_soc_register_codec);
 /**
  * snd_soc_unregister_codec - Unregister a codec from the ASoC core
  *
  * @codec: codec to unregister
  */
 void snd_soc_unregister_codec(struct device *dev)
 {
 	struct snd_soc_codec *codec;
 	list_for_each_entry(codec, &codec_list, list) {
 		if (dev == codec->dev)
 			goto found;
 	}
 	return;
 found:
 	mutex_lock(&client_mutex);
 	list_del(&codec->list);
 	snd_soc_component_del_unlocked(&codec->component);
 	mutex_unlock(&client_mutex);
 	dev_dbg(codec->dev, "ASoC: Unregistered codec '%s'\n",
 			codec->component.name);
 	snd_soc_component_cleanup(&codec->component);
 	snd_soc_cache_exit(codec);
 	kfree(codec);
 }
 EXPORT_SYMBOL_GPL(snd_soc_unregister_codec);
 /* Retrieve a card's name from device tree */
 int snd_soc_of_parse_card_name(struct snd_soc_card *card,
 			       const char *propname)
 {
 	struct device_node *np;
 	int ret;
 	if (!card->dev) {
 		pr_err("card->dev is not set before calling %s\n", __func__);
 		return -EINVAL;
 	}
 	np = card->dev->of_node;
 	ret = of_property_read_string_index(np, propname, 0, &card->name);
 	/*
 	 * EINVAL means the property does not exist. This is fine providing
 	 * card->name was previously set, which is checked later in
 	 * snd_soc_register_card.
 	 */
 	if (ret < 0 && ret != -EINVAL) {
 		dev_err(card->dev,
 			"ASoC: Property '%s' could not be read: %d\n",
 			propname, ret);
 		return ret;
 	}
 	return 0;
 }
 EXPORT_SYMBOL_GPL(snd_soc_of_parse_card_name);
 static const struct snd_soc_dapm_widget simple_widgets[] = {
 	SND_SOC_DAPM_MIC("Microphone", NULL),
 	SND_SOC_DAPM_LINE("Line", NULL),
 	SND_SOC_DAPM_HP("Headphone", NULL),
 	SND_SOC_DAPM_SPK("Speaker", NULL),
 };
 int snd_soc_of_parse_audio_simple_widgets(struct snd_soc_card *card,
 					  const char *propname)
 {
 	struct device_node *np = card->dev->of_node;
 	struct snd_soc_dapm_widget *widgets;
 	const char *template, *wname;
 	int i, j, num_widgets, ret;
 	num_widgets = of_property_count_strings(np, propname);
 	if (num_widgets < 0) {
 		dev_err(card->dev,
 			"ASoC: Property '%s' does not exist\n",	propname);
 		return -EINVAL;
 	}
 	if (num_widgets & 1) {
 		dev_err(card->dev,
 			"ASoC: Property '%s' length is not even\n", propname);
 		return -EINVAL;
 	}
 	num_widgets /= 2;
 	if (!num_widgets) {
 		dev_err(card->dev, "ASoC: Property '%s's length is zero\n",
 			propname);
 		return -EINVAL;
 	}
 	widgets = devm_kcalloc(card->dev, num_widgets, sizeof(*widgets),
 			       GFP_KERNEL);
 	if (!widgets) {
 		dev_err(card->dev,
 			"ASoC: Could not allocate memory for widgets\n");
 		return -ENOMEM;
 	}
 	for (i = 0; i < num_widgets; i++) {
 		ret = of_property_read_string_index(np, propname,
 			2 * i, &template);
 		if (ret) {
 			dev_err(card->dev,
 				"ASoC: Property '%s' index %d read error:%d\n",
 				propname, 2 * i, ret);
 			return -EINVAL;
 		}
 		for (j = 0; j < ARRAY_SIZE(simple_widgets); j++) {
 			if (!strncmp(template, simple_widgets[j].name,
 				     strlen(simple_widgets[j].name))) {
 				widgets[i] = simple_widgets[j];
 				break;
 			}
 		}
 		if (j >= ARRAY_SIZE(simple_widgets)) {
 			dev_err(card->dev,
 				"ASoC: DAPM widget '%s' is not supported\n",
 				template);
 			return -EINVAL;
 		}
 		ret = of_property_read_string_index(np, propname,
 						    (2 * i) + 1,
 						    &wname);
 		if (ret) {
 			dev_err(card->dev,
 				"ASoC: Property '%s' index %d read error:%d\n",
 				propname, (2 * i) + 1, ret);
 			return -EINVAL;
 		}
 		widgets[i].name = wname;
 	}
 	card->dapm_widgets = widgets;
 	card->num_dapm_widgets = num_widgets;
 	return 0;
 }
 EXPORT_SYMBOL_GPL(snd_soc_of_parse_audio_simple_widgets);
 int snd_soc_of_parse_tdm_slot(struct device_node *np,
 			      unsigned int *slots,
 			      unsigned int *slot_width)
 {
 	u32 val;
 	int ret;
 	if (of_property_read_bool(np, "dai-tdm-slot-num")) {
 		ret = of_property_read_u32(np, "dai-tdm-slot-num", &val);
 		if (ret)
 			return ret;
 		if (slots)
 			*slots = val;
 	}
 	if (of_property_read_bool(np, "dai-tdm-slot-width")) {
 		ret = of_property_read_u32(np, "dai-tdm-slot-width", &val);
 		if (ret)
 			return ret;
 		if (slot_width)
 			*slot_width = val;
 	}
 	return 0;
 }
 EXPORT_SYMBOL_GPL(snd_soc_of_parse_tdm_slot);
 int snd_soc_of_parse_audio_routing(struct snd_soc_card *card,
 				   const char *propname)
 {
 	struct device_node *np = card->dev->of_node;
-	int num_routes, old_routes;
+	int num_routes;
 	struct snd_soc_dapm_route *routes;
 	int i, ret;
 	num_routes = of_property_count_strings(np, propname);
 	if (num_routes < 0 || num_routes & 1) {
 		dev_err(card->dev,
 			"ASoC: Property '%s' does not exist or its length is not even\n",
 			propname);
 		return -EINVAL;
 	}
 	num_routes /= 2;
 	if (!num_routes) {
 		dev_err(card->dev, "ASoC: Property '%s's length is zero\n",
 			propname);
 		return -EINVAL;
 	}
-	old_routes = card->num_dapm_routes;
+	routes = devm_kzalloc(card->dev, num_routes * sizeof(*routes),
-	routes = devm_kzalloc(card->dev,
-			      (old_routes + num_routes) * sizeof(*routes),
 			      GFP_KERNEL);
 	if (!routes) {
 		dev_err(card->dev,
 			"ASoC: Could not allocate DAPM route table\n");
 		return -EINVAL;
 	}
-	memcpy(routes, card->dapm_routes, old_routes * sizeof(*routes));
 	for (i = 0; i < num_routes; i++) {
 		ret = of_property_read_string_index(np, propname,
-			2 * i, &routes[old_routes + i].sink);
+			2 * i, &routes[i].sink);
 		if (ret) {
 			dev_err(card->dev,
 				"ASoC: Property '%s' index %d could not be read: %d\n",
 				propname, 2 * i, ret);
 			return -EINVAL;
 		}
 		ret = of_property_read_string_index(np, propname,
-			(2 * i) + 1, &routes[old_routes + i].source);
+			(2 * i) + 1, &routes[i].source);
 		if (ret) {
 			dev_err(card->dev,
 				"ASoC: Property '%s' index %d could not be read: %d\n",
 				propname, (2 * i) + 1, ret);
 			return -EINVAL;
 		}
 	}
-	card->num_dapm_routes += num_routes;
+	card->num_dapm_routes = num_routes;
 	card->dapm_routes = routes;
 	return 0;
 }
 EXPORT_SYMBOL_GPL(snd_soc_of_parse_audio_routing);
 unsigned int snd_soc_of_parse_daifmt(struct device_node *np,
 				     const char *prefix,
 				     struct device_node **bitclkmaster,
 				     struct device_node **framemaster)
 {
 	int ret, i;
 	char prop[128];
 	unsigned int format = 0;
 	int bit, frame;
 	const char *str;
 	struct {
 		char *name;
 		unsigned int val;
 	} of_fmt_table[] = {
 		{ "i2s",	SND_SOC_DAIFMT_I2S },
 		{ "right_j",	SND_SOC_DAIFMT_RIGHT_J },
 		{ "left_j",	SND_SOC_DAIFMT_LEFT_J },
 		{ "dsp_a",	SND_SOC_DAIFMT_DSP_A },
 		{ "dsp_b",	SND_SOC_DAIFMT_DSP_B },
 		{ "ac97",	SND_SOC_DAIFMT_AC97 },
 		{ "pdm",	SND_SOC_DAIFMT_PDM},
 		{ "msb",	SND_SOC_DAIFMT_MSB },
 		{ "lsb",	SND_SOC_DAIFMT_LSB },
 	};
 	if (!prefix)
 		prefix = "";
 	/*
 	 * check "[prefix]format = xxx"
 	 * SND_SOC_DAIFMT_FORMAT_MASK area
 	 */
 	snprintf(prop, sizeof(prop), "%sformat", prefix);
 	ret = of_property_read_string(np, prop, &str);
 	if (ret == 0) {
 		for (i = 0; i < ARRAY_SIZE(of_fmt_table); i++) {
 			if (strcmp(str, of_fmt_table[i].name) == 0) {
 				format |= of_fmt_table[i].val;
 				break;
 			}
 		}
 	}
 	/*
 	 * check "[prefix]continuous-clock"
 	 * SND_SOC_DAIFMT_CLOCK_MASK area
 	 */
 	snprintf(prop, sizeof(prop), "%scontinuous-clock", prefix);
 	if (of_get_property(np, prop, NULL))
 		format |= SND_SOC_DAIFMT_CONT;
 	else
 		format |= SND_SOC_DAIFMT_GATED;
 	/*
 	 * check "[prefix]bitclock-inversion"
 	 * check "[prefix]frame-inversion"
 	 * SND_SOC_DAIFMT_INV_MASK area
 	 */
 	snprintf(prop, sizeof(prop), "%sbitclock-inversion", prefix);
 	bit = !!of_get_property(np, prop, NULL);
 	snprintf(prop, sizeof(prop), "%sframe-inversion", prefix);
 	frame = !!of_get_property(np, prop, NULL);
 	switch ((bit << 4) + frame) {
 	case 0x11:
 		format |= SND_SOC_DAIFMT_IB_IF;
 		break;
 	case 0x10:
 		format |= SND_SOC_DAIFMT_IB_NF;
 		break;
 	case 0x01:
 		format |= SND_SOC_DAIFMT_NB_IF;
 		break;
 	default:
 		/* SND_SOC_DAIFMT_NB_NF is default */
 		break;
 	}
 	/*
 	 * check "[prefix]bitclock-master"
 	 * check "[prefix]frame-master"
 	 * SND_SOC_DAIFMT_MASTER_MASK area
 	 */
 	snprintf(prop, sizeof(prop), "%sbitclock-master", prefix);
 	bit = !!of_get_property(np, prop, NULL);
 	if (bit && bitclkmaster)
 		*bitclkmaster = of_parse_phandle(np, prop, 0);
 	snprintf(prop, sizeof(prop), "%sframe-master", prefix);
 	frame = !!of_get_property(np, prop, NULL);
 	if (frame && framemaster)
 		*framemaster = of_parse_phandle(np, prop, 0);
 	switch ((bit << 4) + frame) {
 	case 0x11:
 		format |= SND_SOC_DAIFMT_CBM_CFM;
 		break;
 	case 0x10:
 		format |= SND_SOC_DAIFMT_CBM_CFS;
 		break;
 	case 0x01:
 		format |= SND_SOC_DAIFMT_CBS_CFM;
 		break;
 	default:
 		format |= SND_SOC_DAIFMT_CBS_CFS;
 		break;
 	}
 	return format;
 }
 EXPORT_SYMBOL_GPL(snd_soc_of_parse_daifmt);
 static int snd_soc_get_dai_name(struct of_phandle_args *args,
 				const char **dai_name)
 {
 	struct snd_soc_component *pos;
 	int ret = -EPROBE_DEFER;
 	mutex_lock(&client_mutex);
 	list_for_each_entry(pos, &component_list, list) {
 		if (pos->dev->of_node != args->np)
 			continue;
 		if (pos->driver->of_xlate_dai_name) {
 			ret = pos->driver->of_xlate_dai_name(pos,
 							     args,
 							     dai_name);
 		} else {
 			int id = -1;
 			switch (args->args_count) {
 			case 0:
 				id = 0; /* same as dai_drv[0] */
 				break;
 			case 1:
 				id = args->args[0];
 				break;
 			default:
 				/* not supported */
 				break;
 			}
 			if (id < 0 || id >= pos->num_dai) {
 				ret = -EINVAL;
 				continue;
 			}
 			ret = 0;
 			*dai_name = pos->dai_drv[id].name;
 			if (!*dai_name)
 				*dai_name = pos->name;
 		}
 		break;
 	}
 	mutex_unlock(&client_mutex);
 	return ret;
 }
 int snd_soc_of_get_dai_name(struct device_node *of_node,
 			    const char **dai_name)
 {
 	struct of_phandle_args args;
 	int ret;
 	ret = of_parse_phandle_with_args(of_node, "sound-dai",
 					 "#sound-dai-cells", 0, &args);
 	if (ret)
 		return ret;
 	ret = snd_soc_get_dai_name(&args, dai_name);
 	of_node_put(args.np);
 	return ret;
 }
 EXPORT_SYMBOL_GPL(snd_soc_of_get_dai_name);
 /*
  * snd_soc_of_get_dai_link_codecs - Parse a list of CODECs in the devicetree
  * @dev: Card device
  * @of_node: Device node
  * @dai_link: DAI link
  *
  * Builds an array of CODEC DAI components from the DAI link property
  * 'sound-dai'.
  * The array is set in the DAI link and the number of DAIs is set accordingly.
  * The device nodes in the array (of_node) must be dereferenced by the caller.
  *
  * Returns 0 for success
  */
 int snd_soc_of_get_dai_link_codecs(struct device *dev,
 				   struct device_node *of_node,
 				   struct snd_soc_dai_link *dai_link)
 {
 	struct of_phandle_args args;
 	struct snd_soc_dai_link_component *component;
 	char *name;
 	int index, num_codecs, ret;
 	/* Count the number of CODECs */
 	name = "sound-dai";
 	num_codecs = of_count_phandle_with_args(of_node, name,
 						"#sound-dai-cells");
 	if (num_codecs <= 0) {
 		if (num_codecs == -ENOENT)
 			dev_err(dev, "No 'sound-dai' property\n");
 		else
 			dev_err(dev, "Bad phandle in 'sound-dai'\n");
 		return num_codecs;
 	}
 	component = devm_kzalloc(dev,
 				 sizeof *component * num_codecs,
 				 GFP_KERNEL);
 	if (!component)
 		return -ENOMEM;
 	dai_link->codecs = component;
 	dai_link->num_codecs = num_codecs;
 	/* Parse the list */
 	for (index = 0, component = dai_link->codecs;
 	     index < dai_link->num_codecs;
 	     index++, component++) {
 		ret = of_parse_phandle_with_args(of_node, name,
 						 "#sound-dai-cells",
 						  index, &args);
 		if (ret)
 			goto err;
 		component->of_node = args.np;
 		ret = snd_soc_get_dai_name(&args, &component->dai_name);
 		if (ret < 0)
 			goto err;
 	}
 	return 0;
 err:
 	for (index = 0, component = dai_link->codecs;
 	     index < dai_link->num_codecs;
 	     index++, component++) {
 		if (!component->of_node)
 			break;
 		of_node_put(component->of_node);
 		component->of_node = NULL;
 	}
 	dai_link->codecs = NULL;
 	dai_link->num_codecs = 0;
 	return ret;
 }
 EXPORT_SYMBOL_GPL(snd_soc_of_get_dai_link_codecs);
 static int __init snd_soc_init(void)
 {
 #ifdef CONFIG_DEBUG_FS
 	snd_soc_debugfs_root = debugfs_create_dir("asoc", NULL);
 	if (IS_ERR(snd_soc_debugfs_root) || !snd_soc_debugfs_root) {
 		pr_warn("ASoC: Failed to create debugfs directory\n");
 		snd_soc_debugfs_root = NULL;
 	}
 	if (!debugfs_create_file("codecs", 0444, snd_soc_debugfs_root, NULL,
 				 &codec_list_fops))
 		pr_warn("ASoC: Failed to create CODEC list debugfs file\n");
 	if (!debugfs_create_file("dais", 0444, snd_soc_debugfs_root, NULL,
 				 &dai_list_fops))
 		pr_warn("ASoC: Failed to create DAI list debugfs file\n");
 	if (!debugfs_create_file("platforms", 0444, snd_soc_debugfs_root, NULL,
 				 &platform_list_fops))
 		pr_warn("ASoC: Failed to create platform list debugfs file\n");
 #endif
 	snd_soc_util_init();
 	return platform_driver_register(&soc_driver);
 }
 module_init(snd_soc_init);
 static void __exit snd_soc_exit(void)
 {
 	snd_soc_util_exit();
 #ifdef CONFIG_DEBUG_FS
 	debugfs_remove_recursive(snd_soc_debugfs_root);
 #endif
 	platform_driver_unregister(&soc_driver);
 }
 module_exit(snd_soc_exit);
 /* Module information */
 MODULE_AUTHOR("Liam Girdwood, lrg@slimlogic.co.uk");
 MODULE_DESCRIPTION("ALSA SoC Core");
 MODULE_LICENSE("GPL");
 MODULE_ALIAS("platform:soc-audio");

1	/*	1	/*
2	* sound/soc/rockchip/rockchip_i2s.h	2	* sound/soc/rockchip/rockchip_i2s.h
3	*	3	*
4	* ALSA SoC Audio Layer - Rockchip I2S Controller driver	4	* ALSA SoC Audio Layer - Rockchip I2S Controller driver
5	*	5	*
6	* Copyright (c) 2014 Rockchip Electronics Co. Ltd.	6	* Copyright (c) 2014 Rockchip Electronics Co. Ltd.
7	* Author: Jianqun xu <jay.xu@rock-chips.com>	7	* Author: Jianqun xu <jay.xu@rock-chips.com>
8	*	8	*
9	* This program is free software; you can redistribute it and/or modify	9	* This program is free software; you can redistribute it and/or modify
10	* it under the terms of the GNU General Public License version 2 as	10	* it under the terms of the GNU General Public License version 2 as
11	* published by the Free Software Foundation.	11	* published by the Free Software Foundation.
12	*/	12	*/
13		13
14	#ifndef _ROCKCHIP_IIS_H	14	#ifndef _ROCKCHIP_IIS_H
15	#define _ROCKCHIP_IIS_H	15	#define _ROCKCHIP_IIS_H
16		16
17	/*	17	/*
18	* TXCR	18	* TXCR
19	* transmit operation control register	19	* transmit operation control register
20	*/	20	*/
21	#define I2S_TXCR_RCNT_SHIFT 17	21	#define I2S_TXCR_RCNT_SHIFT 17
22	#define I2S_TXCR_RCNT_MASK (0x3f << I2S_TXCR_RCNT_SHIFT)	22	#define I2S_TXCR_RCNT_MASK (0x3f << I2S_TXCR_RCNT_SHIFT)
23	#define I2S_TXCR_CSR_SHIFT 15	23	#define I2S_TXCR_CSR_SHIFT 15
24	#define I2S_TXCR_CSR(x) (x << I2S_TXCR_CSR_SHIFT)	24	#define I2S_TXCR_CSR(x) (x << I2S_TXCR_CSR_SHIFT)
25	#define I2S_TXCR_CSR_MASK (3 << I2S_TXCR_CSR_SHIFT)	25	#define I2S_TXCR_CSR_MASK (3 << I2S_TXCR_CSR_SHIFT)
26	#define I2S_TXCR_HWT BIT(14)	26	#define I2S_TXCR_HWT BIT(14)
27	#define I2S_TXCR_SJM_SHIFT 12	27	#define I2S_TXCR_SJM_SHIFT 12
28	#define I2S_TXCR_SJM_R (0 << I2S_TXCR_SJM_SHIFT)	28	#define I2S_TXCR_SJM_R (0 << I2S_TXCR_SJM_SHIFT)
29	#define I2S_TXCR_SJM_L (1 << I2S_TXCR_SJM_SHIFT)	29	#define I2S_TXCR_SJM_L (1 << I2S_TXCR_SJM_SHIFT)
30	#define I2S_TXCR_FBM_SHIFT 11	30	#define I2S_TXCR_FBM_SHIFT 11
31	#define I2S_TXCR_FBM_MSB (0 << I2S_TXCR_FBM_SHIFT)	31	#define I2S_TXCR_FBM_MSB (0 << I2S_TXCR_FBM_SHIFT)
32	#define I2S_TXCR_FBM_LSB (1 << I2S_TXCR_FBM_SHIFT)	32	#define I2S_TXCR_FBM_LSB (1 << I2S_TXCR_FBM_SHIFT)
33	#define I2S_TXCR_IBM_SHIFT 9	33	#define I2S_TXCR_IBM_SHIFT 9
34	#define I2S_TXCR_IBM_NORMAL (0 << I2S_TXCR_IBM_SHIFT)	34	#define I2S_TXCR_IBM_NORMAL (0 << I2S_TXCR_IBM_SHIFT)
35	#define I2S_TXCR_IBM_LSJM (1 << I2S_TXCR_IBM_SHIFT)	35	#define I2S_TXCR_IBM_LSJM (1 << I2S_TXCR_IBM_SHIFT)
36	#define I2S_TXCR_IBM_RSJM (2 << I2S_TXCR_IBM_SHIFT)	36	#define I2S_TXCR_IBM_RSJM (2 << I2S_TXCR_IBM_SHIFT)
37	#define I2S_TXCR_IBM_MASK (3 << I2S_TXCR_IBM_SHIFT)	37	#define I2S_TXCR_IBM_MASK (3 << I2S_TXCR_IBM_SHIFT)
38	#define I2S_TXCR_PBM_SHIFT 7	38	#define I2S_TXCR_PBM_SHIFT 7
39	#define I2S_TXCR_PBM_MODE(x) (x << I2S_TXCR_PBM_SHIFT)	39	#define I2S_TXCR_PBM_MODE(x) (x << I2S_TXCR_PBM_SHIFT)
40	#define I2S_TXCR_PBM_MASK (3 << I2S_TXCR_PBM_SHIFT)	40	#define I2S_TXCR_PBM_MASK (3 << I2S_TXCR_PBM_SHIFT)
41	#define I2S_TXCR_TFS_SHIFT 5	41	#define I2S_TXCR_TFS_SHIFT 5
42	#define I2S_TXCR_TFS_I2S (0 << I2S_TXCR_TFS_SHIFT)	42	#define I2S_TXCR_TFS_I2S (0 << I2S_TXCR_TFS_SHIFT)
43	#define I2S_TXCR_TFS_PCM (1 << I2S_TXCR_TFS_SHIFT)	43	#define I2S_TXCR_TFS_PCM (1 << I2S_TXCR_TFS_SHIFT)
44	#define I2S_TXCR_VDW_SHIFT 0	44	#define I2S_TXCR_VDW_SHIFT 0
45	#define I2S_TXCR_VDW(x) ((x - 1) << I2S_TXCR_VDW_SHIFT)	45	#define I2S_TXCR_VDW(x) ((x - 1) << I2S_TXCR_VDW_SHIFT)
46	#define I2S_TXCR_VDW_MASK (0x1f << I2S_TXCR_VDW_SHIFT)	46	#define I2S_TXCR_VDW_MASK (0x1f << I2S_TXCR_VDW_SHIFT)
47		47
48	/*	48	/*
49	* RXCR	49	* RXCR
50	* receive operation control register	50	* receive operation control register
51	*/	51	*/
52	#define I2S_RXCR_HWT BIT(14)	52	#define I2S_RXCR_HWT BIT(14)
53	#define I2S_RXCR_SJM_SHIFT 12	53	#define I2S_RXCR_SJM_SHIFT 12
54	#define I2S_RXCR_SJM_R (0 << I2S_RXCR_SJM_SHIFT)	54	#define I2S_RXCR_SJM_R (0 << I2S_RXCR_SJM_SHIFT)
55	#define I2S_RXCR_SJM_L (1 << I2S_RXCR_SJM_SHIFT)	55	#define I2S_RXCR_SJM_L (1 << I2S_RXCR_SJM_SHIFT)
56	#define I2S_RXCR_FBM_SHIFT 11	56	#define I2S_RXCR_FBM_SHIFT 11
57	#define I2S_RXCR_FBM_MSB (0 << I2S_RXCR_FBM_SHIFT)	57	#define I2S_RXCR_FBM_MSB (0 << I2S_RXCR_FBM_SHIFT)
58	#define I2S_RXCR_FBM_LSB (1 << I2S_RXCR_FBM_SHIFT)	58	#define I2S_RXCR_FBM_LSB (1 << I2S_RXCR_FBM_SHIFT)
59	#define I2S_RXCR_IBM_SHIFT 9	59	#define I2S_RXCR_IBM_SHIFT 9
60	#define I2S_RXCR_IBM_NORMAL (0 << I2S_RXCR_IBM_SHIFT)	60	#define I2S_RXCR_IBM_NORMAL (0 << I2S_RXCR_IBM_SHIFT)
61	#define I2S_RXCR_IBM_LSJM (1 << I2S_RXCR_IBM_SHIFT)	61	#define I2S_RXCR_IBM_LSJM (1 << I2S_RXCR_IBM_SHIFT)
62	#define I2S_RXCR_IBM_RSJM (2 << I2S_RXCR_IBM_SHIFT)	62	#define I2S_RXCR_IBM_RSJM (2 << I2S_RXCR_IBM_SHIFT)
63	#define I2S_RXCR_IBM_MASK (3 << I2S_RXCR_IBM_SHIFT)	63	#define I2S_RXCR_IBM_MASK (3 << I2S_RXCR_IBM_SHIFT)
64	#define I2S_RXCR_PBM_SHIFT 7	64	#define I2S_RXCR_PBM_SHIFT 7
65	#define I2S_RXCR_PBM_MODE(x) (x << I2S_RXCR_PBM_SHIFT)	65	#define I2S_RXCR_PBM_MODE(x) (x << I2S_RXCR_PBM_SHIFT)
66	#define I2S_RXCR_PBM_MASK (3 << I2S_RXCR_PBM_SHIFT)	66	#define I2S_RXCR_PBM_MASK (3 << I2S_RXCR_PBM_SHIFT)
67	#define I2S_RXCR_TFS_SHIFT 5	67	#define I2S_RXCR_TFS_SHIFT 5
68	#define I2S_RXCR_TFS_I2S (0 << I2S_RXCR_TFS_SHIFT)	68	#define I2S_RXCR_TFS_I2S (0 << I2S_RXCR_TFS_SHIFT)
69	#define I2S_RXCR_TFS_PCM (1 << I2S_RXCR_TFS_SHIFT)	69	#define I2S_RXCR_TFS_PCM (1 << I2S_RXCR_TFS_SHIFT)
70	#define I2S_RXCR_VDW_SHIFT 0	70	#define I2S_RXCR_VDW_SHIFT 0
71	#define I2S_RXCR_VDW(x) ((x - 1) << I2S_RXCR_VDW_SHIFT)	71	#define I2S_RXCR_VDW(x) ((x - 1) << I2S_RXCR_VDW_SHIFT)
72	#define I2S_RXCR_VDW_MASK (0x1f << I2S_RXCR_VDW_SHIFT)	72	#define I2S_RXCR_VDW_MASK (0x1f << I2S_RXCR_VDW_SHIFT)
73		73
74	/*	74	/*
75	* CKR	75	* CKR
76	* clock generation register	76	* clock generation register
77	*/	77	*/
78	#define I2S_CKR_MSS_SHIFT 27	78	#define I2S_CKR_MSS_SHIFT 27
79	#define I2S_CKR_MSS_MASTER (0 << I2S_CKR_MSS_SHIFT)	79	#define I2S_CKR_MSS_MASTER (0 << I2S_CKR_MSS_SHIFT)
80	#define I2S_CKR_MSS_SLAVE (1 << I2S_CKR_MSS_SHIFT)	80	#define I2S_CKR_MSS_SLAVE (1 << I2S_CKR_MSS_SHIFT)
81	#define I2S_CKR_MSS_MASK (1 << I2S_CKR_MSS_SHIFT)	81	#define I2S_CKR_MSS_MASK (1 << I2S_CKR_MSS_SHIFT)
82	#define I2S_CKR_CKP_SHIFT 26	82	#define I2S_CKR_CKP_SHIFT 26
83	#define I2S_CKR_CKP_NEG (0 << I2S_CKR_CKP_SHIFT)	83	#define I2S_CKR_CKP_NEG (0 << I2S_CKR_CKP_SHIFT)
84	#define I2S_CKR_CKP_POS (1 << I2S_CKR_CKP_SHIFT)	84	#define I2S_CKR_CKP_POS (1 << I2S_CKR_CKP_SHIFT)
85	#define I2S_CKR_RLP_SHIFT 25	85	#define I2S_CKR_RLP_SHIFT 25
86	#define I2S_CKR_RLP_NORMAL (0 << I2S_CKR_RLP_SHIFT)	86	#define I2S_CKR_RLP_NORMAL (0 << I2S_CKR_RLP_SHIFT)
87	#define I2S_CKR_RLP_OPPSITE (1 << I2S_CKR_RLP_SHIFT)	87	#define I2S_CKR_RLP_OPPSITE (1 << I2S_CKR_RLP_SHIFT)
88	#define I2S_CKR_TLP_SHIFT 24	88	#define I2S_CKR_TLP_SHIFT 24
89	#define I2S_CKR_TLP_NORMAL (0 << I2S_CKR_TLP_SHIFT)	89	#define I2S_CKR_TLP_NORMAL (0 << I2S_CKR_TLP_SHIFT)
90	#define I2S_CKR_TLP_OPPSITE (1 << I2S_CKR_TLP_SHIFT)	90	#define I2S_CKR_TLP_OPPSITE (1 << I2S_CKR_TLP_SHIFT)
91	#define I2S_CKR_MDIV_SHIFT 16	91	#define I2S_CKR_MDIV_SHIFT 16
92	#define I2S_CKR_MDIV(x) ((x - 1) << I2S_CKR_MDIV_SHIFT)	92	#define I2S_CKR_MDIV(x) ((x - 1) << I2S_CKR_MDIV_SHIFT)
93	#define I2S_CKR_MDIV_MASK (0xff << I2S_CKR_MDIV_SHIFT)	93	#define I2S_CKR_MDIV_MASK (0xff << I2S_CKR_MDIV_SHIFT)
94	#define I2S_CKR_RSD_SHIFT 8	94	#define I2S_CKR_RSD_SHIFT 8
95	#define I2S_CKR_RSD(x) ((x - 1) << I2S_CKR_RSD_SHIFT)	95	#define I2S_CKR_RSD(x) ((x - 1) << I2S_CKR_RSD_SHIFT)
96	#define I2S_CKR_RSD_MASK (0xff << I2S_CKR_RSD_SHIFT)	96	#define I2S_CKR_RSD_MASK (0xff << I2S_CKR_RSD_SHIFT)
97	#define I2S_CKR_TSD_SHIFT 0	97	#define I2S_CKR_TSD_SHIFT 0
98	#define I2S_CKR_TSD(x) ((x - 1) << I2S_CKR_TSD_SHIFT)	98	#define I2S_CKR_TSD(x) ((x - 1) << I2S_CKR_TSD_SHIFT)
99	#define I2S_CKR_TSD_MASK (0xff << I2S_CKR_TSD_SHIFT)	99	#define I2S_CKR_TSD_MASK (0xff << I2S_CKR_TSD_SHIFT)
100		100
101	/*	101	/*
102	* FIFOLR	102	* FIFOLR
103	* FIFO level register	103	* FIFO level register
104	*/	104	*/
105	#define I2S_FIFOLR_RFL_SHIFT 24	105	#define I2S_FIFOLR_RFL_SHIFT 24
106	#define I2S_FIFOLR_RFL_MASK (0x3f << I2S_FIFOLR_RFL_SHIFT)	106	#define I2S_FIFOLR_RFL_MASK (0x3f << I2S_FIFOLR_RFL_SHIFT)
107	#define I2S_FIFOLR_TFL3_SHIFT 18	107	#define I2S_FIFOLR_TFL3_SHIFT 18
108	#define I2S_FIFOLR_TFL3_MASK (0x3f << I2S_FIFOLR_TFL3_SHIFT)	108	#define I2S_FIFOLR_TFL3_MASK (0x3f << I2S_FIFOLR_TFL3_SHIFT)
109	#define I2S_FIFOLR_TFL2_SHIFT 12	109	#define I2S_FIFOLR_TFL2_SHIFT 12
110	#define I2S_FIFOLR_TFL2_MASK (0x3f << I2S_FIFOLR_TFL2_SHIFT)	110	#define I2S_FIFOLR_TFL2_MASK (0x3f << I2S_FIFOLR_TFL2_SHIFT)
111	#define I2S_FIFOLR_TFL1_SHIFT 6	111	#define I2S_FIFOLR_TFL1_SHIFT 6
112	#define I2S_FIFOLR_TFL1_MASK (0x3f << I2S_FIFOLR_TFL1_SHIFT)	112	#define I2S_FIFOLR_TFL1_MASK (0x3f << I2S_FIFOLR_TFL1_SHIFT)
113	#define I2S_FIFOLR_TFL0_SHIFT 0	113	#define I2S_FIFOLR_TFL0_SHIFT 0
114	#define I2S_FIFOLR_TFL0_MASK (0x3f << I2S_FIFOLR_TFL0_SHIFT)	114	#define I2S_FIFOLR_TFL0_MASK (0x3f << I2S_FIFOLR_TFL0_SHIFT)
115		115
116	/*	116	/*
117	* DMACR	117	* DMACR
118	* DMA control register	118	* DMA control register
119	*/	119	*/
120	#define I2S_DMACR_RDE_SHIFT 24	120	#define I2S_DMACR_RDE_SHIFT 24
121	#define I2S_DMACR_RDE_DISABLE (0 << I2S_DMACR_RDE_SHIFT)	121	#define I2S_DMACR_RDE_DISABLE (0 << I2S_DMACR_RDE_SHIFT)
122	#define I2S_DMACR_RDE_ENABLE (1 << I2S_DMACR_RDE_SHIFT)	122	#define I2S_DMACR_RDE_ENABLE (1 << I2S_DMACR_RDE_SHIFT)
123	#define I2S_DMACR_RDL_SHIFT 16	123	#define I2S_DMACR_RDL_SHIFT 16
124	#define I2S_DMACR_RDL(x) ((x - 1) << I2S_DMACR_RDL_SHIFT)	124	#define I2S_DMACR_RDL(x) ((x - 1) << I2S_DMACR_RDL_SHIFT)
125	#define I2S_DMACR_RDL_MASK (0x1f << I2S_DMACR_RDL_SHIFT)	125	#define I2S_DMACR_RDL_MASK (0x1f << I2S_DMACR_RDL_SHIFT)
126	#define I2S_DMACR_TDE_SHIFT 8	126	#define I2S_DMACR_TDE_SHIFT 8
127	#define I2S_DMACR_TDE_DISABLE (0 << I2S_DMACR_TDE_SHIFT)	127	#define I2S_DMACR_TDE_DISABLE (0 << I2S_DMACR_TDE_SHIFT)
128	#define I2S_DMACR_TDE_ENABLE (1 << I2S_DMACR_TDE_SHIFT)	128	#define I2S_DMACR_TDE_ENABLE (1 << I2S_DMACR_TDE_SHIFT)
129	#define I2S_DMACR_TDL_SHIFT 0	129	#define I2S_DMACR_TDL_SHIFT 0
130	#define I2S_DMACR_TDL(x) ((x - 1) << I2S_DMACR_TDL_SHIFT)	130	#define I2S_DMACR_TDL(x) ((x) << I2S_DMACR_TDL_SHIFT)
131	#define I2S_DMACR_TDL_MASK (0x1f << I2S_DMACR_TDL_SHIFT)	131	#define I2S_DMACR_TDL_MASK (0x1f << I2S_DMACR_TDL_SHIFT)
132		132
133	/*	133	/*
134	* INTCR	134	* INTCR
135	* interrupt control register	135	* interrupt control register
136	*/	136	*/
137	#define I2S_INTCR_RFT_SHIFT 20	137	#define I2S_INTCR_RFT_SHIFT 20
138	#define I2S_INTCR_RFT(x) ((x - 1) << I2S_INTCR_RFT_SHIFT)	138	#define I2S_INTCR_RFT(x) ((x - 1) << I2S_INTCR_RFT_SHIFT)
139	#define I2S_INTCR_RXOIC BIT(18)	139	#define I2S_INTCR_RXOIC BIT(18)
140	#define I2S_INTCR_RXOIE_SHIFT 17	140	#define I2S_INTCR_RXOIE_SHIFT 17
141	#define I2S_INTCR_RXOIE_DISABLE (0 << I2S_INTCR_RXOIE_SHIFT)	141	#define I2S_INTCR_RXOIE_DISABLE (0 << I2S_INTCR_RXOIE_SHIFT)
142	#define I2S_INTCR_RXOIE_ENABLE (1 << I2S_INTCR_RXOIE_SHIFT)	142	#define I2S_INTCR_RXOIE_ENABLE (1 << I2S_INTCR_RXOIE_SHIFT)
143	#define I2S_INTCR_RXFIE_SHIFT 16	143	#define I2S_INTCR_RXFIE_SHIFT 16
144	#define I2S_INTCR_RXFIE_DISABLE (0 << I2S_INTCR_RXFIE_SHIFT)	144	#define I2S_INTCR_RXFIE_DISABLE (0 << I2S_INTCR_RXFIE_SHIFT)
145	#define I2S_INTCR_RXFIE_ENABLE (1 << I2S_INTCR_RXFIE_SHIFT)	145	#define I2S_INTCR_RXFIE_ENABLE (1 << I2S_INTCR_RXFIE_SHIFT)
146	#define I2S_INTCR_TFT_SHIFT 4	146	#define I2S_INTCR_TFT_SHIFT 4
147	#define I2S_INTCR_TFT(x) ((x - 1) << I2S_INTCR_TFT_SHIFT)	147	#define I2S_INTCR_TFT(x) ((x - 1) << I2S_INTCR_TFT_SHIFT)
148	#define I2S_INTCR_TFT_MASK (0x1f << I2S_INTCR_TFT_SHIFT)	148	#define I2S_INTCR_TFT_MASK (0x1f << I2S_INTCR_TFT_SHIFT)
149	#define I2S_INTCR_TXUIC BIT(2)	149	#define I2S_INTCR_TXUIC BIT(2)
150	#define I2S_INTCR_TXUIE_SHIFT 1	150	#define I2S_INTCR_TXUIE_SHIFT 1
151	#define I2S_INTCR_TXUIE_DISABLE (0 << I2S_INTCR_TXUIE_SHIFT)	151	#define I2S_INTCR_TXUIE_DISABLE (0 << I2S_INTCR_TXUIE_SHIFT)
152	#define I2S_INTCR_TXUIE_ENABLE (1 << I2S_INTCR_TXUIE_SHIFT)	152	#define I2S_INTCR_TXUIE_ENABLE (1 << I2S_INTCR_TXUIE_SHIFT)
153		153
154	/*	154	/*
155	* INTSR	155	* INTSR
156	* interrupt status register	156	* interrupt status register
157	*/	157	*/
158	#define I2S_INTSR_TXEIE_SHIFT 0	158	#define I2S_INTSR_TXEIE_SHIFT 0
159	#define I2S_INTSR_TXEIE_DISABLE (0 << I2S_INTSR_TXEIE_SHIFT)	159	#define I2S_INTSR_TXEIE_DISABLE (0 << I2S_INTSR_TXEIE_SHIFT)
160	#define I2S_INTSR_TXEIE_ENABLE (1 << I2S_INTSR_TXEIE_SHIFT)	160	#define I2S_INTSR_TXEIE_ENABLE (1 << I2S_INTSR_TXEIE_SHIFT)
161	#define I2S_INTSR_RXOI_SHIFT 17	161	#define I2S_INTSR_RXOI_SHIFT 17
162	#define I2S_INTSR_RXOI_INA (0 << I2S_INTSR_RXOI_SHIFT)	162	#define I2S_INTSR_RXOI_INA (0 << I2S_INTSR_RXOI_SHIFT)
163	#define I2S_INTSR_RXOI_ACT (1 << I2S_INTSR_RXOI_SHIFT)	163	#define I2S_INTSR_RXOI_ACT (1 << I2S_INTSR_RXOI_SHIFT)
164	#define I2S_INTSR_RXFI_SHIFT 16	164	#define I2S_INTSR_RXFI_SHIFT 16
165	#define I2S_INTSR_RXFI_INA (0 << I2S_INTSR_RXFI_SHIFT)	165	#define I2S_INTSR_RXFI_INA (0 << I2S_INTSR_RXFI_SHIFT)
166	#define I2S_INTSR_RXFI_ACT (1 << I2S_INTSR_RXFI_SHIFT)	166	#define I2S_INTSR_RXFI_ACT (1 << I2S_INTSR_RXFI_SHIFT)
167	#define I2S_INTSR_TXUI_SHIFT 1	167	#define I2S_INTSR_TXUI_SHIFT 1
168	#define I2S_INTSR_TXUI_INA (0 << I2S_INTSR_TXUI_SHIFT)	168	#define I2S_INTSR_TXUI_INA (0 << I2S_INTSR_TXUI_SHIFT)
169	#define I2S_INTSR_TXUI_ACT (1 << I2S_INTSR_TXUI_SHIFT)	169	#define I2S_INTSR_TXUI_ACT (1 << I2S_INTSR_TXUI_SHIFT)
170	#define I2S_INTSR_TXEI_SHIFT 0	170	#define I2S_INTSR_TXEI_SHIFT 0
171	#define I2S_INTSR_TXEI_INA (0 << I2S_INTSR_TXEI_SHIFT)	171	#define I2S_INTSR_TXEI_INA (0 << I2S_INTSR_TXEI_SHIFT)
172	#define I2S_INTSR_TXEI_ACT (1 << I2S_INTSR_TXEI_SHIFT)	172	#define I2S_INTSR_TXEI_ACT (1 << I2S_INTSR_TXEI_SHIFT)
173		173
174	/*	174	/*
175	* XFER	175	* XFER
176	* Transfer start register	176	* Transfer start register
177	*/	177	*/
178	#define I2S_XFER_RXS_SHIFT 1	178	#define I2S_XFER_RXS_SHIFT 1
179	#define I2S_XFER_RXS_STOP (0 << I2S_XFER_RXS_SHIFT)	179	#define I2S_XFER_RXS_STOP (0 << I2S_XFER_RXS_SHIFT)
180	#define I2S_XFER_RXS_START (1 << I2S_XFER_RXS_SHIFT)	180	#define I2S_XFER_RXS_START (1 << I2S_XFER_RXS_SHIFT)
181	#define I2S_XFER_TXS_SHIFT 0	181	#define I2S_XFER_TXS_SHIFT 0
182	#define I2S_XFER_TXS_STOP (0 << I2S_XFER_TXS_SHIFT)	182	#define I2S_XFER_TXS_STOP (0 << I2S_XFER_TXS_SHIFT)
183	#define I2S_XFER_TXS_START (1 << I2S_XFER_TXS_SHIFT)	183	#define I2S_XFER_TXS_START (1 << I2S_XFER_TXS_SHIFT)
184		184
185	/*	185	/*
186	* CLR	186	* CLR
187	* clear SCLK domain logic register	187	* clear SCLK domain logic register
188	*/	188	*/
189	#define I2S_CLR_RXC BIT(1)	189	#define I2S_CLR_RXC BIT(1)
190	#define I2S_CLR_TXC BIT(0)	190	#define I2S_CLR_TXC BIT(0)
191		191
192	/*	192	/*
193	* TXDR	193	* TXDR
194	* Transimt FIFO data register, write only.	194	* Transimt FIFO data register, write only.
195	*/	195	*/
196	#define I2S_TXDR_MASK (0xff)	196	#define I2S_TXDR_MASK (0xff)
197		197
198	/*	198	/*
199	* RXDR	199	* RXDR
200	* Receive FIFO data register, write only.	200	* Receive FIFO data register, write only.
201	*/	201	*/
202	#define I2S_RXDR_MASK (0xff)	202	#define I2S_RXDR_MASK (0xff)
203		203
204	/* Clock divider id */	204	/* Clock divider id */
205	enum {	205	enum {
206	ROCKCHIP_DIV_MCLK = 0,	206	ROCKCHIP_DIV_MCLK = 0,
207	ROCKCHIP_DIV_BCLK,	207	ROCKCHIP_DIV_BCLK,
208	};	208	};
209		209
210	/* I2S REGS */	210	/* I2S REGS */
211	#define I2S_TXCR (0x0000)	211	#define I2S_TXCR (0x0000)
212	#define I2S_RXCR (0x0004)	212	#define I2S_RXCR (0x0004)
213	#define I2S_CKR (0x0008)	213	#define I2S_CKR (0x0008)
214	#define I2S_FIFOLR (0x000c)	214	#define I2S_FIFOLR (0x000c)
215	#define I2S_DMACR (0x0010)	215	#define I2S_DMACR (0x0010)
216	#define I2S_INTCR (0x0014)	216	#define I2S_INTCR (0x0014)
217	#define I2S_INTSR (0x0018)	217	#define I2S_INTSR (0x0018)
218	#define I2S_XFER (0x001c)	218	#define I2S_XFER (0x001c)
219	#define I2S_CLR (0x0020)	219	#define I2S_CLR (0x0020)
220	#define I2S_TXDR (0x0024)	220	#define I2S_TXDR (0x0024)
221	#define I2S_RXDR (0x0028)	221	#define I2S_RXDR (0x0028)
222		222
223	#endif /* _ROCKCHIP_IIS_H */	223	#endif /* _ROCKCHIP_IIS_H */
224		224