Merge remote-tracking branches 'asoc/fix/dwc', 'asoc/fix/intel', 'asoc/fix/rockc…

…hip' and 'asoc/fix/rt5677' into asoc-linus

Merge remote-tracking branches 'asoc/fix/dwc', 'asoc/fix/intel', 'asoc/fix/rockc…
…hip' and 'asoc/fix/rt5677' into asoc-linus
Mark Brown
5 parents c533b8e60a db2c1f9e38 25f97549b5 27fd36ab13 6087fcab7b
Showing 8 changed files Side-by-side Diff
sound/soc/codecs/rt5677.c
sound/soc/dwc/designware_i2s.c
sound/soc/intel/Kconfig
sound/soc/intel/bytcr_dpcm_rt5640.c
sound/soc/intel/sst-firmware.c
sound/soc/intel/sst/sst_acpi.c
sound/soc/rockchip/rockchip_i2s.c
sound/soc/rockchip/rockchip_i2s.h
@@ -784,8 +784,8 @@
 static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
 		struct snd_ctl_elem_value *ucontrol)
 {
-	struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
-	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
+	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+	struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
  
 	ucontrol->value.integer.value[0] = rt5677->dsp_vad_en;
  
@@ -795,8 +795,9 @@
 static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
 		struct snd_ctl_elem_value *ucontrol)
 {
-	struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
-	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
+	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+	struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
+	struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
  
 	rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0];
  
@@ -209,16 +209,9 @@
  
 	switch (config->chan_nr) {
 	case EIGHT_CHANNEL_SUPPORT:
-		ch_reg = 3;
-		break;
 	case SIX_CHANNEL_SUPPORT:
-		ch_reg = 2;
-		break;
 	case FOUR_CHANNEL_SUPPORT:
-		ch_reg = 1;
-		break;
 	case TWO_CHANNEL_SUPPORT:
-		ch_reg = 0;
 		break;
 	default:
 		dev_err(dev->dev, "channel not supported\n");
@@ -227,18 +220,22 @@
  
 	i2s_disable_channels(dev, substream->stream);
  
-	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
-		i2s_write_reg(dev->i2s_base, TCR(ch_reg), xfer_resolution);
-		i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02);
-		irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
-		i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30);
-		i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);
-	} else {
-		i2s_write_reg(dev->i2s_base, RCR(ch_reg), xfer_resolution);
-		i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07);
-		irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
-		i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x03);
-		i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);
+	for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) {
+		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+			i2s_write_reg(dev->i2s_base, TCR(ch_reg),
+				      xfer_resolution);
+			i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02);
+			irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
+			i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30);
+			i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);
+		} else {
+			i2s_write_reg(dev->i2s_base, RCR(ch_reg),
+				      xfer_resolution);
+			i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07);
+			irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
+			i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x03);
+			i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);
+		}
 	}
  
 	i2s_write_reg(dev->i2s_base, CCR, ccr);
@@ -263,6 +260,19 @@
 	snd_soc_dai_set_dma_data(dai, substream, NULL);
 }
  
+static int dw_i2s_prepare(struct snd_pcm_substream *substream,
+			  struct snd_soc_dai *dai)
+{
+	struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
+
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		i2s_write_reg(dev->i2s_base, TXFFR, 1);
+	else
+		i2s_write_reg(dev->i2s_base, RXFFR, 1);
+
+	return 0;
+}
+
 static int dw_i2s_trigger(struct snd_pcm_substream *substream,
 		int cmd, struct snd_soc_dai *dai)
 {
@@ -294,6 +304,7 @@
 	.startup	= dw_i2s_startup,
 	.shutdown	= dw_i2s_shutdown,
 	.hw_params	= dw_i2s_hw_params,
+	.prepare	= dw_i2s_prepare,
 	.trigger	= dw_i2s_trigger,
 };
  
@@ -89,7 +89,7 @@
  
 config SND_SOC_INTEL_BYTCR_RT5640_MACH
 	tristate "ASoC Audio DSP Support for MID BYT Platform"
-	depends on X86
+	depends on X86 && I2C
 	select SND_SOC_RT5640
 	select SND_SST_MFLD_PLATFORM
 	select SND_SST_IPC_ACPI
@@ -101,7 +101,7 @@
  
 config SND_SOC_INTEL_CHT_BSW_RT5672_MACH
         tristate "ASoC Audio driver for Intel Cherrytrail & Braswell with RT5672 codec"
-        depends on X86_INTEL_LPSS
+        depends on X86_INTEL_LPSS && I2C
         select SND_SOC_RT5670
         select SND_SST_MFLD_PLATFORM
         select SND_SST_IPC_ACPI
@@ -227,5 +227,5 @@
 MODULE_DESCRIPTION("ASoC Intel(R) Baytrail CR Machine driver");
 MODULE_AUTHOR("Subhransu S. Prusty <subhransu.s.prusty@intel.com>");
 MODULE_LICENSE("GPL v2");
-MODULE_ALIAS("platform:bytrt5640-audio");
+MODULE_ALIAS("platform:bytt100_rt5640");
@@ -763,8 +763,12 @@
 		/* does block span more than 1 section */
 		if (ba->offset >= block->offset && ba->offset < block_end) {
  
+			/* add block */
+			list_move(&block->list, &dsp->used_block_list);
+			list_add(&block->module_list, block_list);
 			/* align ba to block boundary */
-			ba->offset = block->offset;
+			ba->size -= block_end - ba->offset;
+			ba->offset = block_end;
  
 			err = block_alloc_contiguous(dsp, ba, block_list);
 			if (err < 0)
@@ -343,7 +343,7 @@
 }
  
 static struct sst_machines sst_acpi_bytcr[] = {
-	{"10EC5640", "T100", "bytt100_rt5640", NULL, "fw_sst_0f28.bin",
+	{"10EC5640", "T100", "bytt100_rt5640", NULL, "intel/fw_sst_0f28.bin",
 						&byt_rvp_platform_data },
 	{},
 };
@@ -454,11 +454,11 @@
  
 	i2s->playback_dma_data.addr = res->start + I2S_TXDR;
 	i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
-	i2s->playback_dma_data.maxburst = 16;
+	i2s->playback_dma_data.maxburst = 4;
  
 	i2s->capture_dma_data.addr = res->start + I2S_RXDR;
 	i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
-	i2s->capture_dma_data.maxburst = 16;
+	i2s->capture_dma_data.maxburst = 4;
  
 	i2s->dev = &pdev->dev;
 	dev_set_drvdata(&pdev->dev, i2s);
@@ -127,7 +127,7 @@
 #define I2S_DMACR_TDE_DISABLE	(0 << I2S_DMACR_TDE_SHIFT)
 #define I2S_DMACR_TDE_ENABLE	(1 << I2S_DMACR_TDE_SHIFT)
 #define I2S_DMACR_TDL_SHIFT	0
-#define I2S_DMACR_TDL(x)	((x - 1) << I2S_DMACR_TDL_SHIFT)
+#define I2S_DMACR_TDL(x)	((x) << I2S_DMACR_TDL_SHIFT)
 #define I2S_DMACR_TDL_MASK	(0x1f << I2S_DMACR_TDL_SHIFT)
  
 /*
...	...	@@ -784,8 +784,8 @@
784	784	static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
785	785	struct snd_ctl_elem_value *ucontrol)
786	786	{
787		- struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
788		- struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
	787	+ struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
	788	+ struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
789	789
790	790	ucontrol->value.integer.value[0] = rt5677->dsp_vad_en;
791	791
...	...	@@ -795,8 +795,9 @@
795	795	static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
796	796	struct snd_ctl_elem_value *ucontrol)
797	797	{
798		- struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
799		- struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
	798	+ struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
	799	+ struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
	800	+ struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
800	801
801	802	rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0];
802	803
...	...	@@ -209,16 +209,9 @@
209	209
210	210	switch (config->chan_nr) {
211	211	case EIGHT_CHANNEL_SUPPORT:
212		- ch_reg = 3;
213		- break;
214	212	case SIX_CHANNEL_SUPPORT:
215		- ch_reg = 2;
216		- break;
217	213	case FOUR_CHANNEL_SUPPORT:
218		- ch_reg = 1;
219		- break;
220	214	case TWO_CHANNEL_SUPPORT:
221		- ch_reg = 0;
222	215	break;
223	216	default:
224	217	dev_err(dev->dev, "channel not supported\n");
...	...	@@ -227,18 +220,22 @@
227	220
228	221	i2s_disable_channels(dev, substream->stream);
229	222
230		- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
231		- i2s_write_reg(dev->i2s_base, TCR(ch_reg), xfer_resolution);
232		- i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02);
233		- irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
234		- i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30);
235		- i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);
236		- } else {
237		- i2s_write_reg(dev->i2s_base, RCR(ch_reg), xfer_resolution);
238		- i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07);
239		- irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
240		- i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x03);
241		- i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);
	223	+ for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) {
	224	+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	225	+ i2s_write_reg(dev->i2s_base, TCR(ch_reg),
	226	+ xfer_resolution);
	227	+ i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02);
	228	+ irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
	229	+ i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30);
	230	+ i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);
	231	+ } else {
	232	+ i2s_write_reg(dev->i2s_base, RCR(ch_reg),
	233	+ xfer_resolution);
	234	+ i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07);
	235	+ irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
	236	+ i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x03);
	237	+ i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);
	238	+ }
242	239	}
243	240
244	241	i2s_write_reg(dev->i2s_base, CCR, ccr);
...	...	@@ -263,6 +260,19 @@
263	260	snd_soc_dai_set_dma_data(dai, substream, NULL);
264	261	}
265	262
	263	+static int dw_i2s_prepare(struct snd_pcm_substream *substream,
	264	+ struct snd_soc_dai *dai)
	265	+{
	266	+ struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
	267	+
	268	+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	269	+ i2s_write_reg(dev->i2s_base, TXFFR, 1);
	270	+ else
	271	+ i2s_write_reg(dev->i2s_base, RXFFR, 1);
	272	+
	273	+ return 0;
	274	+}
	275	+
266	276	static int dw_i2s_trigger(struct snd_pcm_substream *substream,
267	277	int cmd, struct snd_soc_dai *dai)
268	278	{
...	...	@@ -294,6 +304,7 @@
294	304	.startup = dw_i2s_startup,
295	305	.shutdown = dw_i2s_shutdown,
296	306	.hw_params = dw_i2s_hw_params,
	307	+ .prepare = dw_i2s_prepare,
297	308	.trigger = dw_i2s_trigger,
298	309	};
299	310
...	...	@@ -89,7 +89,7 @@
89	89
90	90	config SND_SOC_INTEL_BYTCR_RT5640_MACH
91	91	tristate "ASoC Audio DSP Support for MID BYT Platform"
92		- depends on X86
	92	+ depends on X86 && I2C
93	93	select SND_SOC_RT5640
94	94	select SND_SST_MFLD_PLATFORM
95	95	select SND_SST_IPC_ACPI
...	...	@@ -101,7 +101,7 @@
101	101
102	102	config SND_SOC_INTEL_CHT_BSW_RT5672_MACH
103	103	tristate "ASoC Audio driver for Intel Cherrytrail & Braswell with RT5672 codec"
104		- depends on X86_INTEL_LPSS
	104	+ depends on X86_INTEL_LPSS && I2C
105	105	select SND_SOC_RT5670
106	106	select SND_SST_MFLD_PLATFORM
107	107	select SND_SST_IPC_ACPI
...	...	@@ -227,5 +227,5 @@
227	227	MODULE_DESCRIPTION("ASoC Intel(R) Baytrail CR Machine driver");
228	228	MODULE_AUTHOR("Subhransu S. Prusty <subhransu.s.prusty@intel.com>");
229	229	MODULE_LICENSE("GPL v2");
230		-MODULE_ALIAS("platform:bytrt5640-audio");
	230	+MODULE_ALIAS("platform:bytt100_rt5640");
...	...	@@ -763,8 +763,12 @@
763	763	/* does block span more than 1 section */
764	764	if (ba->offset >= block->offset && ba->offset < block_end) {
765	765
	766	+ /* add block */
	767	+ list_move(&block->list, &dsp->used_block_list);
	768	+ list_add(&block->module_list, block_list);
766	769	/* align ba to block boundary */
767		- ba->offset = block->offset;
	770	+ ba->size -= block_end - ba->offset;
	771	+ ba->offset = block_end;
768	772
769	773	err = block_alloc_contiguous(dsp, ba, block_list);
770	774	if (err < 0)
...	...	@@ -343,7 +343,7 @@
343	343	}
344	344
345	345	static struct sst_machines sst_acpi_bytcr[] = {
346		- {"10EC5640", "T100", "bytt100_rt5640", NULL, "fw_sst_0f28.bin",
	346	+ {"10EC5640", "T100", "bytt100_rt5640", NULL, "intel/fw_sst_0f28.bin",
347	347	&byt_rvp_platform_data },
348	348	{},
349	349	};
...	...	@@ -454,11 +454,11 @@
454	454
455	455	i2s->playback_dma_data.addr = res->start + I2S_TXDR;
456	456	i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
457		- i2s->playback_dma_data.maxburst = 16;
	457	+ i2s->playback_dma_data.maxburst = 4;
458	458
459	459	i2s->capture_dma_data.addr = res->start + I2S_RXDR;
460	460	i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
461		- i2s->capture_dma_data.maxburst = 16;
	461	+ i2s->capture_dma_data.maxburst = 4;
462	462
463	463	i2s->dev = &pdev->dev;
464	464	dev_set_drvdata(&pdev->dev, i2s);
...	...	@@ -127,7 +127,7 @@
127	127	#define I2S_DMACR_TDE_DISABLE (0 << I2S_DMACR_TDE_SHIFT)
128	128	#define I2S_DMACR_TDE_ENABLE (1 << I2S_DMACR_TDE_SHIFT)
129	129	#define I2S_DMACR_TDL_SHIFT 0
130		-#define I2S_DMACR_TDL(x) ((x - 1) << I2S_DMACR_TDL_SHIFT)
	130	+#define I2S_DMACR_TDL(x) ((x) << I2S_DMACR_TDL_SHIFT)
131	131	#define I2S_DMACR_TDL_MASK (0x1f << I2S_DMACR_TDL_SHIFT)
132	132
133	133	/*