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Commit ea2fdf842365066c82ab941086c6a1741ced4f2a

Authored by Bartlomiej Zolnierkiewicz
Committed by Felipe Balbi
1 parent 1c3c052887
Exists in ti-lsk-linux-4.1.y and in 10 other branches dlt-processor-sdk-linux-03.00.00.04, processor-sdk-linux-02.00.01, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04

usb: phy: samsung: remove old common USB PHY code 

drivers/usb/phy/phy-samsung-usb[2,3] drivers got replaced by
drivers/phy/phy-samsung-usb[2,3] ones and the old common Samsung
USB PHY code is no longer used.

Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Vivek Gautam <gautam.vivek@samsung.com>
Reviewed-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Kamil Debski <k.debski@samsung.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

Showing 3 changed files with 0 additions and 585 deletions Side-by-side Diff

drivers/usb/phy/phy-samsung-usb.c
View file @ ea2fdf8
1   -/* linux/drivers/usb/phy/phy-samsung-usb.c
2   - *
3   - * Copyright (c) 2012 Samsung Electronics Co., Ltd.
4   - * http://www.samsung.com
5   - *
6   - * Author: Praveen Paneri <p.paneri@samsung.com>
7   - *
8   - * Samsung USB-PHY helper driver with common function calls;
9   - * interacts with Samsung USB 2.0 PHY controller driver and later
10   - * with Samsung USB 3.0 PHY driver.
11   - *
12   - * This program is free software; you can redistribute it and/or modify
13   - * it under the terms of the GNU General Public License version 2 as
14   - * published by the Free Software Foundation.
15   - *
16   - * This program is distributed in the hope that it will be useful,
17   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
18   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19   - * GNU General Public License for more details.
20   - */
21   -
22   -#include <linux/module.h>
23   -#include <linux/platform_device.h>
24   -#include <linux/clk.h>
25   -#include <linux/device.h>
26   -#include <linux/err.h>
27   -#include <linux/io.h>
28   -#include <linux/of.h>
29   -#include <linux/of_address.h>
30   -#include <linux/usb/samsung_usb_phy.h>
31   -
32   -#include "phy-samsung-usb.h"
33   -
34   -int samsung_usbphy_parse_dt(struct samsung_usbphy *sphy)
35   -{
36   - struct device_node *usbphy_sys;
37   -
38   - /* Getting node for system controller interface for usb-phy */
39   - usbphy_sys = of_get_child_by_name(sphy->dev->of_node, "usbphy-sys");
40   - if (!usbphy_sys) {
41   - dev_err(sphy->dev, "No sys-controller interface for usb-phy\n");
42   - return -ENODEV;
43   - }
44   -
45   - sphy->pmuregs = of_iomap(usbphy_sys, 0);
46   -
47   - if (sphy->pmuregs == NULL) {
48   - dev_err(sphy->dev, "Can't get usb-phy pmu control register\n");
49   - goto err0;
50   - }
51   -
52   - sphy->sysreg = of_iomap(usbphy_sys, 1);
53   -
54   - /*
55   - * Not returning error code here, since this situation is not fatal.
56   - * Few SoCs may not have this switch available
57   - */
58   - if (sphy->sysreg == NULL)
59   - dev_warn(sphy->dev, "Can't get usb-phy sysreg cfg register\n");
60   -
61   - of_node_put(usbphy_sys);
62   -
63   - return 0;
64   -
65   -err0:
66   - of_node_put(usbphy_sys);
67   - return -ENXIO;
68   -}
69   -EXPORT_SYMBOL_GPL(samsung_usbphy_parse_dt);
70   -
71   -/*
72   - * Set isolation here for phy.
73   - * Here 'on = true' would mean USB PHY block is isolated, hence
74   - * de-activated and vice-versa.
75   - */
76   -void samsung_usbphy_set_isolation_4210(struct samsung_usbphy *sphy, bool on)
77   -{
78   - void __iomem *reg = NULL;
79   - u32 reg_val;
80   - u32 en_mask = 0;
81   -
82   - if (!sphy->pmuregs) {
83   - dev_warn(sphy->dev, "Can't set pmu isolation\n");
84   - return;
85   - }
86   -
87   - if (sphy->phy_type == USB_PHY_TYPE_DEVICE) {
88   - reg = sphy->pmuregs + sphy->drv_data->devphy_reg_offset;
89   - en_mask = sphy->drv_data->devphy_en_mask;
90   - } else if (sphy->phy_type == USB_PHY_TYPE_HOST) {
91   - reg = sphy->pmuregs + sphy->drv_data->hostphy_reg_offset;
92   - en_mask = sphy->drv_data->hostphy_en_mask;
93   - }
94   -
95   - reg_val = readl(reg);
96   -
97   - if (on)
98   - reg_val &= ~en_mask;
99   - else
100   - reg_val |= en_mask;
101   -
102   - writel(reg_val, reg);
103   -
104   - if (sphy->drv_data->cpu_type == TYPE_EXYNOS4X12) {
105   - writel(reg_val, sphy->pmuregs + EXYNOS4X12_PHY_HSIC_CTRL0);
106   - writel(reg_val, sphy->pmuregs + EXYNOS4X12_PHY_HSIC_CTRL1);
107   - }
108   -}
109   -EXPORT_SYMBOL_GPL(samsung_usbphy_set_isolation_4210);
110   -
111   -/*
112   - * Configure the mode of working of usb-phy here: HOST/DEVICE.
113   - */
114   -void samsung_usbphy_cfg_sel(struct samsung_usbphy *sphy)
115   -{
116   - u32 reg;
117   -
118   - if (!sphy->sysreg) {
119   - dev_warn(sphy->dev, "Can't configure specified phy mode\n");
120   - return;
121   - }
122   -
123   - reg = readl(sphy->sysreg);
124   -
125   - if (sphy->phy_type == USB_PHY_TYPE_DEVICE)
126   - reg &= ~EXYNOS_USB20PHY_CFG_HOST_LINK;
127   - else if (sphy->phy_type == USB_PHY_TYPE_HOST)
128   - reg |= EXYNOS_USB20PHY_CFG_HOST_LINK;
129   -
130   - writel(reg, sphy->sysreg);
131   -}
132   -EXPORT_SYMBOL_GPL(samsung_usbphy_cfg_sel);
133   -
134   -/*
135   - * PHYs are different for USB Device and USB Host.
136   - * This make sure that correct PHY type is selected before
137   - * any operation on PHY.
138   - */
139   -int samsung_usbphy_set_type(struct usb_phy *phy,
140   - enum samsung_usb_phy_type phy_type)
141   -{
142   - struct samsung_usbphy *sphy = phy_to_sphy(phy);
143   -
144   - sphy->phy_type = phy_type;
145   -
146   - return 0;
147   -}
148   -EXPORT_SYMBOL_GPL(samsung_usbphy_set_type);
149   -
150   -int samsung_usbphy_rate_to_clksel_64xx(struct samsung_usbphy *sphy,
151   - unsigned long rate)
152   -{
153   - unsigned int clksel;
154   -
155   - switch (rate) {
156   - case 12 * MHZ:
157   - clksel = PHYCLK_CLKSEL_12M;
158   - break;
159   - case 24 * MHZ:
160   - clksel = PHYCLK_CLKSEL_24M;
161   - break;
162   - case 48 * MHZ:
163   - clksel = PHYCLK_CLKSEL_48M;
164   - break;
165   - default:
166   - dev_err(sphy->dev,
167   - "Invalid reference clock frequency: %lu\n", rate);
168   - return -EINVAL;
169   - }
170   -
171   - return clksel;
172   -}
173   -EXPORT_SYMBOL_GPL(samsung_usbphy_rate_to_clksel_64xx);
174   -
175   -int samsung_usbphy_rate_to_clksel_4x12(struct samsung_usbphy *sphy,
176   - unsigned long rate)
177   -{
178   - unsigned int clksel;
179   -
180   - switch (rate) {
181   - case 9600 * KHZ:
182   - clksel = FSEL_CLKSEL_9600K;
183   - break;
184   - case 10 * MHZ:
185   - clksel = FSEL_CLKSEL_10M;
186   - break;
187   - case 12 * MHZ:
188   - clksel = FSEL_CLKSEL_12M;
189   - break;
190   - case 19200 * KHZ:
191   - clksel = FSEL_CLKSEL_19200K;
192   - break;
193   - case 20 * MHZ:
194   - clksel = FSEL_CLKSEL_20M;
195   - break;
196   - case 24 * MHZ:
197   - clksel = FSEL_CLKSEL_24M;
198   - break;
199   - case 50 * MHZ:
200   - clksel = FSEL_CLKSEL_50M;
201   - break;
202   - default:
203   - dev_err(sphy->dev,
204   - "Invalid reference clock frequency: %lu\n", rate);
205   - return -EINVAL;
206   - }
207   -
208   - return clksel;
209   -}
210   -EXPORT_SYMBOL_GPL(samsung_usbphy_rate_to_clksel_4x12);
211   -
212   -/*
213   - * Returns reference clock frequency selection value
214   - */
215   -int samsung_usbphy_get_refclk_freq(struct samsung_usbphy *sphy)
216   -{
217   - struct clk *ref_clk;
218   - unsigned long rate;
219   - int refclk_freq;
220   -
221   - /*
222   - * In exynos5250 USB host and device PHY use
223   - * external crystal clock XXTI
224   - */
225   - if (sphy->drv_data->cpu_type == TYPE_EXYNOS5250)
226   - ref_clk = clk_get(sphy->dev, "ext_xtal");
227   - else
228   - ref_clk = clk_get(sphy->dev, "xusbxti");
229   - if (IS_ERR(ref_clk)) {
230   - dev_err(sphy->dev, "Failed to get reference clock\n");
231   - return PTR_ERR(ref_clk);
232   - }
233   -
234   - rate = clk_get_rate(ref_clk);
235   - refclk_freq = sphy->drv_data->rate_to_clksel(sphy, rate);
236   -
237   - clk_put(ref_clk);
238   -
239   - return refclk_freq;
240   -}
241   -EXPORT_SYMBOL_GPL(samsung_usbphy_get_refclk_freq);
drivers/usb/phy/phy-samsung-usb.h
View file @ ea2fdf8
1   -/* linux/drivers/usb/phy/phy-samsung-usb.h
2   - *
3   - * Copyright (c) 2012 Samsung Electronics Co., Ltd.
4   - * http://www.samsung.com
5   - *
6   - * Samsung USB-PHY transceiver; talks to S3C HS OTG controller, EHCI-S5P and
7   - * OHCI-EXYNOS controllers.
8   - *
9   - * This program is free software; you can redistribute it and/or modify
10   - * it under the terms of the GNU General Public License version 2 as
11   - * published by the Free Software Foundation.
12   - *
13   - * This program is distributed in the hope that it will be useful,
14   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
15   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   - * GNU General Public License for more details.
17   - */
18   -
19   -#include <linux/usb/phy.h>
20   -
21   -/* Register definitions */
22   -
23   -#define SAMSUNG_PHYPWR (0x00)
24   -#define PHYPWR_NORMAL_MASK (0x19 << 0)
25   -#define PHYPWR_OTG_DISABLE (0x1 << 4)
26   -#define PHYPWR_ANALOG_POWERDOWN (0x1 << 3)
27   -#define PHYPWR_FORCE_SUSPEND (0x1 << 1)
28   -/* For Exynos4 */
29   -#define PHYPWR_NORMAL_MASK_PHY0 (0x39 << 0)
30   -#define PHYPWR_SLEEP_PHY0 (0x1 << 5)
31   -
32   -#define SAMSUNG_PHYCLK (0x04)
33   -#define PHYCLK_MODE_USB11 (0x1 << 6)
34   -#define PHYCLK_EXT_OSC (0x1 << 5)
35   -#define PHYCLK_COMMON_ON_N (0x1 << 4)
36   -#define PHYCLK_ID_PULL (0x1 << 2)
37   -#define PHYCLK_CLKSEL_MASK (0x3 << 0)
38   -#define PHYCLK_CLKSEL_48M (0x0 << 0)
39   -#define PHYCLK_CLKSEL_12M (0x2 << 0)
40   -#define PHYCLK_CLKSEL_24M (0x3 << 0)
41   -
42   -#define SAMSUNG_RSTCON (0x08)
43   -#define RSTCON_PHYLINK_SWRST (0x1 << 2)
44   -#define RSTCON_HLINK_SWRST (0x1 << 1)
45   -#define RSTCON_SWRST (0x1 << 0)
46   -
47   -/* EXYNOS4X12 */
48   -#define EXYNOS4X12_PHY_HSIC_CTRL0 (0x04)
49   -#define EXYNOS4X12_PHY_HSIC_CTRL1 (0x08)
50   -#define PHYPWR_NORMAL_MASK_HSIC1 (0x7 << 12)
51   -#define PHYPWR_NORMAL_MASK_HSIC0 (0x7 << 9)
52   -#define PHYPWR_NORMAL_MASK_PHY1 (0x7 << 6)
53   -#define RSTCON_HOSTPHY_SWRST (0xf << 3)
54   -
55   -/* EXYNOS5 */
56   -#define EXYNOS5_PHY_HOST_CTRL0 (0x00)
57   -#define HOST_CTRL0_PHYSWRSTALL (0x1 << 31)
58   -#define HOST_CTRL0_REFCLKSEL_MASK (0x3 << 19)
59   -#define HOST_CTRL0_REFCLKSEL_XTAL (0x0 << 19)
60   -#define HOST_CTRL0_REFCLKSEL_EXTL (0x1 << 19)
61   -#define HOST_CTRL0_REFCLKSEL_CLKCORE (0x2 << 19)
62   -#define HOST_CTRL0_FSEL_MASK (0x7 << 16)
63   -#define HOST_CTRL0_FSEL(_x) ((_x) << 16)
64   -#define FSEL_CLKSEL_50M (0x7)
65   -#define FSEL_CLKSEL_24M (0x5)
66   -#define FSEL_CLKSEL_20M (0x4)
67   -#define FSEL_CLKSEL_19200K (0x3)
68   -#define FSEL_CLKSEL_12M (0x2)
69   -#define FSEL_CLKSEL_10M (0x1)
70   -#define FSEL_CLKSEL_9600K (0x0)
71   -#define HOST_CTRL0_TESTBURNIN (0x1 << 11)
72   -#define HOST_CTRL0_RETENABLE (0x1 << 10)
73   -#define HOST_CTRL0_COMMONON_N (0x1 << 9)
74   -#define HOST_CTRL0_SIDDQ (0x1 << 6)
75   -#define HOST_CTRL0_FORCESLEEP (0x1 << 5)
76   -#define HOST_CTRL0_FORCESUSPEND (0x1 << 4)
77   -#define HOST_CTRL0_WORDINTERFACE (0x1 << 3)
78   -#define HOST_CTRL0_UTMISWRST (0x1 << 2)
79   -#define HOST_CTRL0_LINKSWRST (0x1 << 1)
80   -#define HOST_CTRL0_PHYSWRST (0x1 << 0)
81   -
82   -#define EXYNOS5_PHY_HOST_TUNE0 (0x04)
83   -
84   -#define EXYNOS5_PHY_HSIC_CTRL1 (0x10)
85   -
86   -#define EXYNOS5_PHY_HSIC_TUNE1 (0x14)
87   -
88   -#define EXYNOS5_PHY_HSIC_CTRL2 (0x20)
89   -
90   -#define EXYNOS5_PHY_HSIC_TUNE2 (0x24)
91   -#define HSIC_CTRL_REFCLKSEL_MASK (0x3 << 23)
92   -#define HSIC_CTRL_REFCLKSEL (0x2 << 23)
93   -#define HSIC_CTRL_REFCLKDIV_MASK (0x7f << 16)
94   -#define HSIC_CTRL_REFCLKDIV(_x) ((_x) << 16)
95   -#define HSIC_CTRL_REFCLKDIV_12 (0x24 << 16)
96   -#define HSIC_CTRL_REFCLKDIV_15 (0x1c << 16)
97   -#define HSIC_CTRL_REFCLKDIV_16 (0x1a << 16)
98   -#define HSIC_CTRL_REFCLKDIV_19_2 (0x15 << 16)
99   -#define HSIC_CTRL_REFCLKDIV_20 (0x14 << 16)
100   -#define HSIC_CTRL_SIDDQ (0x1 << 6)
101   -#define HSIC_CTRL_FORCESLEEP (0x1 << 5)
102   -#define HSIC_CTRL_FORCESUSPEND (0x1 << 4)
103   -#define HSIC_CTRL_WORDINTERFACE (0x1 << 3)
104   -#define HSIC_CTRL_UTMISWRST (0x1 << 2)
105   -#define HSIC_CTRL_PHYSWRST (0x1 << 0)
106   -
107   -#define EXYNOS5_PHY_HOST_EHCICTRL (0x30)
108   -#define HOST_EHCICTRL_ENAINCRXALIGN (0x1 << 29)
109   -#define HOST_EHCICTRL_ENAINCR4 (0x1 << 28)
110   -#define HOST_EHCICTRL_ENAINCR8 (0x1 << 27)
111   -#define HOST_EHCICTRL_ENAINCR16 (0x1 << 26)
112   -
113   -#define EXYNOS5_PHY_HOST_OHCICTRL (0x34)
114   -#define HOST_OHCICTRL_SUSPLGCY (0x1 << 3)
115   -#define HOST_OHCICTRL_APPSTARTCLK (0x1 << 2)
116   -#define HOST_OHCICTRL_CNTSEL (0x1 << 1)
117   -#define HOST_OHCICTRL_CLKCKTRST (0x1 << 0)
118   -
119   -#define EXYNOS5_PHY_OTG_SYS (0x38)
120   -#define OTG_SYS_PHYLINK_SWRESET (0x1 << 14)
121   -#define OTG_SYS_LINKSWRST_UOTG (0x1 << 13)
122   -#define OTG_SYS_PHY0_SWRST (0x1 << 12)
123   -#define OTG_SYS_REFCLKSEL_MASK (0x3 << 9)
124   -#define OTG_SYS_REFCLKSEL_XTAL (0x0 << 9)
125   -#define OTG_SYS_REFCLKSEL_EXTL (0x1 << 9)
126   -#define OTG_SYS_REFCLKSEL_CLKCORE (0x2 << 9)
127   -#define OTG_SYS_IDPULLUP_UOTG (0x1 << 8)
128   -#define OTG_SYS_COMMON_ON (0x1 << 7)
129   -#define OTG_SYS_FSEL_MASK (0x7 << 4)
130   -#define OTG_SYS_FSEL(_x) ((_x) << 4)
131   -#define OTG_SYS_FORCESLEEP (0x1 << 3)
132   -#define OTG_SYS_OTGDISABLE (0x1 << 2)
133   -#define OTG_SYS_SIDDQ_UOTG (0x1 << 1)
134   -#define OTG_SYS_FORCESUSPEND (0x1 << 0)
135   -
136   -#define EXYNOS5_PHY_OTG_TUNE (0x40)
137   -
138   -/* EXYNOS5: USB 3.0 DRD */
139   -#define EXYNOS5_DRD_LINKSYSTEM (0x04)
140   -#define LINKSYSTEM_FLADJ_MASK (0x3f << 1)
141   -#define LINKSYSTEM_FLADJ(_x) ((_x) << 1)
142   -#define LINKSYSTEM_XHCI_VERSION_CONTROL (0x1 << 27)
143   -
144   -#define EXYNOS5_DRD_PHYUTMI (0x08)
145   -#define PHYUTMI_OTGDISABLE (0x1 << 6)
146   -#define PHYUTMI_FORCESUSPEND (0x1 << 1)
147   -#define PHYUTMI_FORCESLEEP (0x1 << 0)
148   -
149   -#define EXYNOS5_DRD_PHYPIPE (0x0c)
150   -
151   -#define EXYNOS5_DRD_PHYCLKRST (0x10)
152   -#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23)
153   -#define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23)
154   -#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)
155   -#define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21)
156   -#define PHYCLKRST_SSC_EN (0x1 << 20)
157   -#define PHYCLKRST_REF_SSP_EN (0x1 << 19)
158   -#define PHYCLKRST_REF_CLKDIV2 (0x1 << 18)
159   -#define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11)
160   -#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11)
161   -#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x02 << 11)
162   -#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11)
163   -#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11)
164   -#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11)
165   -#define PHYCLKRST_FSEL_MASK (0x3f << 5)
166   -#define PHYCLKRST_FSEL(_x) ((_x) << 5)
167   -#define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5)
168   -#define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5)
169   -#define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5)
170   -#define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5)
171   -#define PHYCLKRST_RETENABLEN (0x1 << 4)
172   -#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)
173   -#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2)
174   -#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2)
175   -#define PHYCLKRST_PORTRESET (0x1 << 1)
176   -#define PHYCLKRST_COMMONONN (0x1 << 0)
177   -
178   -#define EXYNOS5_DRD_PHYREG0 (0x14)
179   -
180   -#define EXYNOS5_DRD_PHYREG1 (0x18)
181   -
182   -#define EXYNOS5_DRD_PHYPARAM0 (0x1c)
183   -#define PHYPARAM0_REF_USE_PAD (0x1 << 31)
184   -#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26)
185   -#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)
186   -
187   -#define EXYNOS5_DRD_PHYPARAM1 (0x20)
188   -#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)
189   -#define PHYPARAM1_PCS_TXDEEMPH (0x1c)
190   -
191   -#define EXYNOS5_DRD_PHYTERM (0x24)
192   -
193   -#define EXYNOS5_DRD_PHYTEST (0x28)
194   -#define PHYTEST_POWERDOWN_SSP (0x1 << 3)
195   -#define PHYTEST_POWERDOWN_HSP (0x1 << 2)
196   -
197   -#define EXYNOS5_DRD_PHYADP (0x2c)
198   -
199   -#define EXYNOS5_DRD_PHYBATCHG (0x30)
200   -#define PHYBATCHG_UTMI_CLKSEL (0x1 << 2)
201   -
202   -#define EXYNOS5_DRD_PHYRESUME (0x34)
203   -
204   -#define EXYNOS5_DRD_LINKPORT (0x44)
205   -
206   -#ifndef MHZ
207   -#define MHZ (1000*1000)
208   -#endif
209   -
210   -#ifndef KHZ
211   -#define KHZ (1000)
212   -#endif
213   -
214   -#define EXYNOS_USBHOST_PHY_CTRL_OFFSET (0x4)
215   -#define S3C64XX_USBPHY_ENABLE (0x1 << 16)
216   -#define EXYNOS_USBPHY_ENABLE (0x1 << 0)
217   -#define EXYNOS_USB20PHY_CFG_HOST_LINK (0x1 << 0)
218   -
219   -enum samsung_cpu_type {
220   - TYPE_S3C64XX,
221   - TYPE_EXYNOS4210,
222   - TYPE_EXYNOS4X12,
223   - TYPE_EXYNOS5250,
224   -};
225   -
226   -struct samsung_usbphy;
227   -
228   -/*
229   - * struct samsung_usbphy_drvdata - driver data for various SoC variants
230   - * @cpu_type: machine identifier
231   - * @devphy_en_mask: device phy enable mask for PHY CONTROL register
232   - * @hostphy_en_mask: host phy enable mask for PHY CONTROL register
233   - * @devphy_reg_offset: offset to DEVICE PHY CONTROL register from
234   - * mapped address of system controller.
235   - * @hostphy_reg_offset: offset to HOST PHY CONTROL register from
236   - * mapped address of system controller.
237   - *
238   - * Here we have a separate mask for device type phy.
239   - * Having different masks for host and device type phy helps
240   - * in setting independent masks in case of SoCs like S5PV210,
241   - * in which PHY0 and PHY1 enable bits belong to same register
242   - * placed at position 0 and 1 respectively.
243   - * Although for newer SoCs like exynos these bits belong to
244   - * different registers altogether placed at position 0.
245   - */
246   -struct samsung_usbphy_drvdata {
247   - int cpu_type;
248   - int devphy_en_mask;
249   - int hostphy_en_mask;
250   - u32 devphy_reg_offset;
251   - u32 hostphy_reg_offset;
252   - int (*rate_to_clksel)(struct samsung_usbphy *, unsigned long);
253   - void (*set_isolation)(struct samsung_usbphy *, bool);
254   - void (*phy_enable)(struct samsung_usbphy *);
255   - void (*phy_disable)(struct samsung_usbphy *);
256   -};
257   -
258   -/*
259   - * struct samsung_usbphy - transceiver driver state
260   - * @phy: transceiver structure
261   - * @plat: platform data
262   - * @dev: The parent device supplied to the probe function
263   - * @clk: usb phy clock
264   - * @regs: usb phy controller registers memory base
265   - * @pmuregs: USB device PHY_CONTROL register memory base
266   - * @sysreg: USB2.0 PHY_CFG register memory base
267   - * @ref_clk_freq: reference clock frequency selection
268   - * @drv_data: driver data available for different SoCs
269   - * @phy_type: Samsung SoCs specific phy types: #HOST
270   - * #DEVICE
271   - * @phy_usage: usage count for phy
272   - * @lock: lock for phy operations
273   - */
274   -struct samsung_usbphy {
275   - struct usb_phy phy;
276   - struct samsung_usbphy_data *plat;
277   - struct device *dev;
278   - struct clk *clk;
279   - void __iomem *regs;
280   - void __iomem *pmuregs;
281   - void __iomem *sysreg;
282   - int ref_clk_freq;
283   - const struct samsung_usbphy_drvdata *drv_data;
284   - enum samsung_usb_phy_type phy_type;
285   - atomic_t phy_usage;
286   - spinlock_t lock;
287   -};
288   -
289   -#define phy_to_sphy(x) container_of((x), struct samsung_usbphy, phy)
290   -
291   -static const struct of_device_id samsung_usbphy_dt_match[];
292   -
293   -static inline const struct samsung_usbphy_drvdata
294   -*samsung_usbphy_get_driver_data(struct platform_device *pdev)
295   -{
296   - if (pdev->dev.of_node) {
297   - const struct of_device_id *match;
298   - match = of_match_node(samsung_usbphy_dt_match,
299   - pdev->dev.of_node);
300   - return match->data;
301   - }
302   -
303   - return (struct samsung_usbphy_drvdata *)
304   - platform_get_device_id(pdev)->driver_data;
305   -}
306   -
307   -extern int samsung_usbphy_parse_dt(struct samsung_usbphy *sphy);
308   -extern void samsung_usbphy_set_isolation_4210(struct samsung_usbphy *sphy,
309   - bool on);
310   -extern void samsung_usbphy_cfg_sel(struct samsung_usbphy *sphy);
311   -extern int samsung_usbphy_set_type(struct usb_phy *phy,
312   - enum samsung_usb_phy_type phy_type);
313   -extern int samsung_usbphy_get_refclk_freq(struct samsung_usbphy *sphy);
314   -extern int samsung_usbphy_rate_to_clksel_64xx(struct samsung_usbphy *sphy,
315   - unsigned long rate);
316   -extern int samsung_usbphy_rate_to_clksel_4x12(struct samsung_usbphy *sphy,
317   - unsigned long rate);
include/linux/platform_data/samsung-usbphy.h
View file @ ea2fdf8
1   -/*
2   - * Copyright (C) 2012 Samsung Electronics Co.Ltd
3   - * http://www.samsung.com/
4   - * Author: Praveen Paneri <p.paneri@samsung.com>
5   - *
6   - * Defines platform data for samsung usb phy driver.
7   - *
8   - * This program is free software; you can redistribute it and/or modify it
9   - * under the terms of the GNU General Public License as published by the
10   - * Free Software Foundation; either version 2 of the License, or (at your
11   - * option) any later version.
12   - */
13   -
14   -#ifndef __SAMSUNG_USBPHY_PLATFORM_H
15   -#define __SAMSUNG_USBPHY_PLATFORM_H
16   -
17   -/**
18   - * samsung_usbphy_data - Platform data for USB PHY driver.
19   - * @pmu_isolation: Function to control usb phy isolation in PMU.
20   - */
21   -struct samsung_usbphy_data {
22   - void (*pmu_isolation)(int on);
23   -};
24   -
25   -extern void samsung_usbphy_set_pdata(struct samsung_usbphy_data *pd);
26   -
27   -#endif /* __SAMSUNG_USBPHY_PLATFORM_H */