drm/i915: Turn get_aux_clock_divider() into per-platform vfuncs

A tiny clean-up to allow better code separation between platforms. v2: Fix comment placement (put in in i9xx_get_aux_clock_divider()) and nuke the outdated PCH eDP comment (Jani Nikula) Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

drm/i915: Turn get_aux_clock_divider() into per-platform vfuncs
A tiny clean-up to allow better code separation between platforms. v2: Fix comment placement (put in in i9xx_get_aux_clock_divider()) and nuke the outdated PCH eDP comment (Jani Nikula) Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Damien Lespiau · Daniel Vetter
1 parent 0f540c3a7c
Showing 2 changed files with 54 additions and 22 deletions Side-by-side Diff
drivers/gpu/drm/i915/intel_dp.c
drivers/gpu/drm/i915/intel_drv.h
@@ -358,31 +358,46 @@
 	return status;
 }
  
-static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
-				      int index)
+static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 {
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = intel_dig_port->base.base.dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
  
-	/* The clock divider is based off the hrawclk,
-	 * and would like to run at 2MHz. So, take the
-	 * hrawclk value and divide by 2 and use that
-	 *
-	 * Note that PCH attached eDP panels should use a 125MHz input
-	 * clock divider.
+	/*
+	 * The clock divider is based off the hrawclk, and would like to run at
+	 * 2MHz.  So, take the hrawclk value and divide by 2 and use that
 	 */
-	if (IS_VALLEYVIEW(dev)) {
-		return index ? 0 : 100;
-	} else if (intel_dig_port->port == PORT_A) {
-		if (index)
-			return 0;
-		if (HAS_DDI(dev))
-			return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
-		else if (IS_GEN6(dev) || IS_GEN7(dev))
+	return index ? 0 : intel_hrawclk(dev) / 2;
+}
+
+static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = intel_dig_port->base.base.dev;
+
+	if (index)
+		return 0;
+
+	if (intel_dig_port->port == PORT_A) {
+		if (IS_GEN6(dev) || IS_GEN7(dev))
 			return 200; /* SNB & IVB eDP input clock at 400Mhz */
 		else
 			return 225; /* eDP input clock at 450Mhz */
+	} else {
+		return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
+	}
+}
+
+static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = intel_dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	if (intel_dig_port->port == PORT_A) {
+		if (index)
+			return 0;
+		return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
 	} else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 		/* Workaround for non-ULT HSW */
 		switch (index) {
  
  
@@ -390,13 +405,16 @@
 		case 1: return 72;
 		default: return 0;
 		}
-	} else if (HAS_PCH_SPLIT(dev)) {
+	} else  {
 		return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
-	} else {
-		return index ? 0 :intel_hrawclk(dev) / 2;
 	}
 }
  
+static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
+{
+	return index ? 0 : 100;
+}
+
 static int
 intel_dp_aux_ch(struct intel_dp *intel_dp,
 		uint8_t *send, int send_bytes,
@@ -455,7 +473,7 @@
 		goto out;
 	}
  
-	while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
+	while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
 		/* Must try at least 3 times according to DP spec */
 		for (try = 0; try < 5; try++) {
 			/* Load the send data into the aux channel data registers */
  
@@ -1619,10 +1637,12 @@
 {
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
+	uint32_t aux_clock_divider;
 	int precharge = 0x3;
 	int msg_size = 5;       /* Header(4) + Message(1) */
  
+	aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
+
 	/* Enable PSR in sink */
 	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
 		intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
@@ -3678,6 +3698,16 @@
 	struct edp_power_seq power_seq = { 0 };
 	const char *name = NULL;
 	int type, error;
+
+	/* intel_dp vfuncs */
+	if (IS_VALLEYVIEW(dev))
+		intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
+	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+		intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
+	else if (HAS_PCH_SPLIT(dev))
+		intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
+	else
+		intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
  
 	/* Preserve the current hw state. */
 	intel_dp->DP = I915_READ(intel_dp->output_reg);
@@ -493,6 +493,8 @@
 	bool psr_setup_done;
 	bool use_tps3;
 	struct intel_connector *attached_connector;
+
+	uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 };
  
 struct intel_digital_port {
...	...	@@ -358,31 +358,46 @@
358	358	return status;
359	359	}
360	360
361		-static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
362		- int index)
	361	+static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
363	362	{
364	363	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
365	364	struct drm_device *dev = intel_dig_port->base.base.dev;
366		- struct drm_i915_private *dev_priv = dev->dev_private;
367	365
368		- /* The clock divider is based off the hrawclk,
369		- * and would like to run at 2MHz. So, take the
370		- * hrawclk value and divide by 2 and use that
371		- *
372		- * Note that PCH attached eDP panels should use a 125MHz input
373		- * clock divider.
	366	+ /*
	367	+ * The clock divider is based off the hrawclk, and would like to run at
	368	+ * 2MHz. So, take the hrawclk value and divide by 2 and use that
374	369	*/
375		- if (IS_VALLEYVIEW(dev)) {
376		- return index ? 0 : 100;
377		- } else if (intel_dig_port->port == PORT_A) {
378		- if (index)
379		- return 0;
380		- if (HAS_DDI(dev))
381		- return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
382		- else if (IS_GEN6(dev) \|\| IS_GEN7(dev))
	370	+ return index ? 0 : intel_hrawclk(dev) / 2;
	371	+}
	372	+
	373	+static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
	374	+{
	375	+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	376	+ struct drm_device *dev = intel_dig_port->base.base.dev;
	377	+
	378	+ if (index)
	379	+ return 0;
	380	+
	381	+ if (intel_dig_port->port == PORT_A) {
	382	+ if (IS_GEN6(dev) \|\| IS_GEN7(dev))
383	383	return 200; /* SNB & IVB eDP input clock at 400Mhz */
384	384	else
385	385	return 225; /* eDP input clock at 450Mhz */
	386	+ } else {
	387	+ return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
	388	+ }
	389	+}
	390	+
	391	+static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
	392	+{
	393	+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	394	+ struct drm_device *dev = intel_dig_port->base.base.dev;
	395	+ struct drm_i915_private *dev_priv = dev->dev_private;
	396	+
	397	+ if (intel_dig_port->port == PORT_A) {
	398	+ if (index)
	399	+ return 0;
	400	+ return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
386	401	} else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
387	402	/* Workaround for non-ULT HSW */
388	403	switch (index) {
389	404
390	405
...	...	@@ -390,13 +405,16 @@
390	405	case 1: return 72;
391	406	default: return 0;
392	407	}
393		- } else if (HAS_PCH_SPLIT(dev)) {
	408	+ } else {
394	409	return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
395		- } else {
396		- return index ? 0 :intel_hrawclk(dev) / 2;
397	410	}
398	411	}
399	412
	413	+static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
	414	+{
	415	+ return index ? 0 : 100;
	416	+}
	417	+
400	418	static int
401	419	intel_dp_aux_ch(struct intel_dp *intel_dp,
402	420	uint8_t *send, int send_bytes,
...	...	@@ -455,7 +473,7 @@
455	473	goto out;
456	474	}
457	475
458		- while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
	476	+ while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
459	477	/* Must try at least 3 times according to DP spec */
460	478	for (try = 0; try < 5; try++) {
461	479	/* Load the send data into the aux channel data registers */
462	480
...	...	@@ -1619,10 +1637,12 @@
1619	1637	{
1620	1638	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1621	1639	struct drm_i915_private *dev_priv = dev->dev_private;
1622		- uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
	1640	+ uint32_t aux_clock_divider;
1623	1641	int precharge = 0x3;
1624	1642	int msg_size = 5; /* Header(4) + Message(1) */
1625	1643
	1644	+ aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
	1645	+
1626	1646	/* Enable PSR in sink */
1627	1647	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1628	1648	intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
...	...	@@ -3678,6 +3698,16 @@
3678	3698	struct edp_power_seq power_seq = { 0 };
3679	3699	const char *name = NULL;
3680	3700	int type, error;
	3701	+
	3702	+ /* intel_dp vfuncs */
	3703	+ if (IS_VALLEYVIEW(dev))
	3704	+ intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
	3705	+ else if (IS_HASWELL(dev) \|\| IS_BROADWELL(dev))
	3706	+ intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
	3707	+ else if (HAS_PCH_SPLIT(dev))
	3708	+ intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
	3709	+ else
	3710	+ intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
3681	3711
3682	3712	/* Preserve the current hw state. */
3683	3713	intel_dp->DP = I915_READ(intel_dp->output_reg);
...	...	@@ -493,6 +493,8 @@
493	493	bool psr_setup_done;
494	494	bool use_tps3;
495	495	struct intel_connector *attached_connector;
	496	+
	497	+ uint32_t (get_aux_clock_divider)(struct intel_dp dp, int index);
496	498	};
497	499
498	500	struct intel_digital_port {