Commit ec987a13d5ec90d690a52304224d731881544f86
Committed by
Greg Kroah-Hartman
1 parent
89a2e6efe2
clocksource: exynos_mct: Fix bitmask regression for exynos4_mct_write
commit 8c38d28ba8da98f7102c31d35359b4dbe9d1f329 upstream. EXYNOS4_MCT_L_MASK is defined as 0xffffff00, so applying this bitmask produces a number outside the range 0x00 to 0xff, which always results in execution of the default switch statement. Obviously this is wrong and git history shows that the bitmask inversion was incorrectly set during a refactoring of the MCT code. Fix this by putting the inversion at the correct position again. Acked-by: Kukjin Kim <kgene.kim@samsung.com> Reported-by: GP Orcullo <kinsamanka@gmail.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Showing 1 changed file with 2 additions and 2 deletions Side-by-side Diff
drivers/clocksource/exynos_mct.c
... | ... | @@ -97,8 +97,8 @@ |
97 | 97 | writel_relaxed(value, reg_base + offset); |
98 | 98 | |
99 | 99 | if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) { |
100 | - stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET; | |
101 | - switch (offset & EXYNOS4_MCT_L_MASK) { | |
100 | + stat_addr = (offset & EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET; | |
101 | + switch (offset & ~EXYNOS4_MCT_L_MASK) { | |
102 | 102 | case MCT_L_TCON_OFFSET: |
103 | 103 | mask = 1 << 3; /* L_TCON write status */ |
104 | 104 | break; |