powerpc/powernv: Update OPAL interfaces

This adds some more interfaces for OPAL v2 Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

powerpc/powernv: Update OPAL interfaces
This adds some more interfaces for OPAL v2 Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt
1 parent fa8cbaaf5a
Showing 3 changed files with 137 additions and 6 deletions Side-by-side Diff
arch/powerpc/include/asm/opal.h
arch/powerpc/platforms/powernv/opal-wrappers.S
arch/powerpc/platforms/powernv/pci-ioda.c
@@ -109,6 +109,14 @@
 #define OPAL_PCI_MAP_PE_DMA_WINDOW		44
 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL		45
 #define OPAL_PCI_RESET				49
+#define OPAL_PCI_GET_HUB_DIAG_DATA		50
+#define OPAL_PCI_GET_PHB_DIAG_DATA		51
+#define OPAL_PCI_FENCE_PHB			52
+#define OPAL_PCI_REINIT				53
+#define OPAL_PCI_MASK_PE_ERROR			54
+#define OPAL_SET_SLOT_LED_STATUS		55
+#define OPAL_GET_EPOW_STATUS			56
+#define OPAL_SET_SYSTEM_ATTENTION_LED		57
  
 #ifndef __ASSEMBLY__
  
@@ -169,7 +177,11 @@
 	OPAL_EVENT_NVRAM = 0x2,
 	OPAL_EVENT_RTC = 0x4,
 	OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
-	OPAL_EVENT_CONSOLE_INPUT = 0x10
+	OPAL_EVENT_CONSOLE_INPUT = 0x10,
+	OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
+	OPAL_EVENT_ERROR_LOG = 0x40,
+	OPAL_EVENT_EPOW = 0x80,
+	OPAL_EVENT_LED_STATUS = 0x100
 };
  
 /* Machine check related definitions */
  
  
  
@@ -258,14 +270,50 @@
 	OPAL_MAP_PE = 1
 };
  
+enum OpalPeltvAction {
+	OPAL_REMOVE_PE_FROM_DOMAIN = 0,
+	OPAL_ADD_PE_TO_DOMAIN = 1
+};
+
+enum OpalMveEnableAction {
+	OPAL_DISABLE_MVE = 0,
+	OPAL_ENABLE_MVE = 1
+};
+
 enum OpalPciResetAndReinitScope {
 	OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
 	OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
-	OPAL_PCI_IODA_RESET = 6,
+	OPAL_PCI_IODA_TABLE_RESET = 6,
 };
  
-enum OpalPciResetState { OPAL_DEASSERT_RESET = 0, OPAL_ASSERT_RESET = 1 };
+enum OpalPciResetState {
+	OPAL_DEASSERT_RESET = 0,
+	OPAL_ASSERT_RESET = 1
+};
  
+enum OpalPciMaskAction {
+	OPAL_UNMASK_ERROR_TYPE = 0,
+	OPAL_MASK_ERROR_TYPE = 1
+};
+
+enum OpalSlotLedType {
+	OPAL_SLOT_LED_ID_TYPE = 0,
+	OPAL_SLOT_LED_FAULT_TYPE = 1
+};
+
+enum OpalLedAction {
+	OPAL_TURN_OFF_LED = 0,
+	OPAL_TURN_ON_LED = 1,
+	OPAL_QUERY_LED_STATE_AFTER_BUSY = 2
+};
+
+enum OpalEpowStatus {
+	OPAL_EPOW_NONE = 0,
+	OPAL_EPOW_UPS = 1,
+	OPAL_EPOW_OVER_AMBIENT_TEMP = 2,
+	OPAL_EPOW_OVER_INTERNAL_TEMP = 3
+};
+
 struct opal_machine_check_event {
 	enum OpalMCE_Version	version:8;	/* 0x00 */
 	uint8_t			in_use;		/* 0x01 */
  
@@ -314,8 +362,74 @@
 	} u;
 };
  
+/**
+ * This structure defines the overlay which will be used to store PHB error
+ * data upon request.
+ */
+enum {
+	OPAL_P7IOC_NUM_PEST_REGS = 128,
+};
+
+struct OpalIoP7IOCPhbErrorData {
+	uint32_t brdgCtl;
+
+	// P7IOC utl regs
+	uint32_t portStatusReg;
+	uint32_t rootCmplxStatus;
+	uint32_t busAgentStatus;
+
+	// P7IOC cfg regs
+	uint32_t deviceStatus;
+	uint32_t slotStatus;
+	uint32_t linkStatus;
+	uint32_t devCmdStatus;
+	uint32_t devSecStatus;
+
+	// cfg AER regs
+	uint32_t rootErrorStatus;
+	uint32_t uncorrErrorStatus;
+	uint32_t corrErrorStatus;
+	uint32_t tlpHdr1;
+	uint32_t tlpHdr2;
+	uint32_t tlpHdr3;
+	uint32_t tlpHdr4;
+	uint32_t sourceId;
+
+	uint32_t rsv3;
+
+	// Record data about the call to allocate a buffer.
+	uint64_t errorClass;
+	uint64_t correlator;
+
+	//P7IOC MMIO Error Regs
+	uint64_t p7iocPlssr;                // n120
+	uint64_t p7iocCsr;                  // n110
+	uint64_t lemFir;                    // nC00
+	uint64_t lemErrorMask;              // nC18
+	uint64_t lemWOF;                    // nC40
+	uint64_t phbErrorStatus;            // nC80
+	uint64_t phbFirstErrorStatus;       // nC88
+	uint64_t phbErrorLog0;              // nCC0
+	uint64_t phbErrorLog1;              // nCC8
+	uint64_t mmioErrorStatus;           // nD00
+	uint64_t mmioFirstErrorStatus;      // nD08
+	uint64_t mmioErrorLog0;             // nD40
+	uint64_t mmioErrorLog1;             // nD48
+	uint64_t dma0ErrorStatus;           // nD80
+	uint64_t dma0FirstErrorStatus;      // nD88
+	uint64_t dma0ErrorLog0;             // nDC0
+	uint64_t dma0ErrorLog1;             // nDC8
+	uint64_t dma1ErrorStatus;           // nE00
+	uint64_t dma1FirstErrorStatus;      // nE08
+	uint64_t dma1ErrorLog0;             // nE40
+	uint64_t dma1ErrorLog1;             // nE48
+	uint64_t pestA[OPAL_P7IOC_NUM_PEST_REGS];
+	uint64_t pestB[OPAL_P7IOC_NUM_PEST_REGS];
+};
+
 typedef struct oppanel_line {
-	/* XXX */
+	const char * 	line;
+	uint64_t 	line_len;
 } oppanel_line_t;
  
 /* API functions */
@@ -412,6 +526,15 @@
 					uint16_t dma_window_number, uint64_t pci_start_addr,
 					uint64_t pci_mem_size);
 int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
+
+int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer, uint64_t diag_buffer_len);
+int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer, uint64_t diag_buffer_len);
+int64_t opal_pci_fence_phb(uint64_t phb_id);
+int64_t opal_pci_reinit(uint64_t phb_id, uint8_t reinit_scope);
+int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
+int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
+int64_t opal_get_epow_status(uint64_t *status);
+int64_t opal_set_system_attention_led(uint8_t led_action);
  
 /* Internal functions */
 extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data);
@@ -99,4 +99,12 @@
 OPAL_CALL(opal_pci_map_pe_dma_window,		OPAL_PCI_MAP_PE_DMA_WINDOW);
 OPAL_CALL(opal_pci_map_pe_dma_window_real,	OPAL_PCI_MAP_PE_DMA_WINDOW_REAL);
 OPAL_CALL(opal_pci_reset,			OPAL_PCI_RESET);
+OPAL_CALL(opal_pci_get_hub_diag_data,		OPAL_PCI_GET_HUB_DIAG_DATA);
+OPAL_CALL(opal_pci_get_phb_diag_data,		OPAL_PCI_GET_PHB_DIAG_DATA);
+OPAL_CALL(opal_pci_fence_phb,			OPAL_PCI_FENCE_PHB);
+OPAL_CALL(opal_pci_reinit,			OPAL_PCI_REINIT);
+OPAL_CALL(opal_pci_mask_pe_error,		OPAL_PCI_MASK_PE_ERROR);
+OPAL_CALL(opal_set_slot_led_status,		OPAL_SET_SLOT_LED_STATUS);
+OPAL_CALL(opal_get_epow_status,			OPAL_GET_EPOW_STATUS);
+OPAL_CALL(opal_set_system_attention_led,	OPAL_SET_SYSTEM_ATTENTION_LED);
@@ -1294,9 +1294,9 @@
 	pci_add_flags(PCI_REASSIGN_ALL_RSRC);
  
 	/* Reset IODA tables to a clean state */
-	rc = opal_pci_reset(phb_id, OPAL_PCI_IODA_RESET, OPAL_ASSERT_RESET);
+	rc = opal_pci_reset(phb_id, OPAL_PCI_IODA_TABLE_RESET, OPAL_ASSERT_RESET);
 	if (rc)
-		pr_warning("  OPAL Error %ld performing IODA reset !\n", rc);
+		pr_warning("  OPAL Error %ld performing IODA table reset !\n", rc);
 	opal_pci_set_pe(phb_id, 0, 0, 7, 1, 1 , OPAL_MAP_PE);
 }
...	...	@@ -109,6 +109,14 @@
109	109	#define OPAL_PCI_MAP_PE_DMA_WINDOW 44
110	110	#define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
111	111	#define OPAL_PCI_RESET 49
	112	+#define OPAL_PCI_GET_HUB_DIAG_DATA 50
	113	+#define OPAL_PCI_GET_PHB_DIAG_DATA 51
	114	+#define OPAL_PCI_FENCE_PHB 52
	115	+#define OPAL_PCI_REINIT 53
	116	+#define OPAL_PCI_MASK_PE_ERROR 54
	117	+#define OPAL_SET_SLOT_LED_STATUS 55
	118	+#define OPAL_GET_EPOW_STATUS 56
	119	+#define OPAL_SET_SYSTEM_ATTENTION_LED 57
112	120
113	121	#ifndef __ASSEMBLY__
114	122
...	...	@@ -169,7 +177,11 @@
169	177	OPAL_EVENT_NVRAM = 0x2,
170	178	OPAL_EVENT_RTC = 0x4,
171	179	OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
172		- OPAL_EVENT_CONSOLE_INPUT = 0x10
	180	+ OPAL_EVENT_CONSOLE_INPUT = 0x10,
	181	+ OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
	182	+ OPAL_EVENT_ERROR_LOG = 0x40,
	183	+ OPAL_EVENT_EPOW = 0x80,
	184	+ OPAL_EVENT_LED_STATUS = 0x100
173	185	};
174	186
175	187	/* Machine check related definitions */
176	188
177	189
178	190
...	...	@@ -258,14 +270,50 @@
258	270	OPAL_MAP_PE = 1
259	271	};
260	272
	273	+enum OpalPeltvAction {
	274	+ OPAL_REMOVE_PE_FROM_DOMAIN = 0,
	275	+ OPAL_ADD_PE_TO_DOMAIN = 1
	276	+};
	277	+
	278	+enum OpalMveEnableAction {
	279	+ OPAL_DISABLE_MVE = 0,
	280	+ OPAL_ENABLE_MVE = 1
	281	+};
	282	+
261	283	enum OpalPciResetAndReinitScope {
262	284	OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
263	285	OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
264		- OPAL_PCI_IODA_RESET = 6,
	286	+ OPAL_PCI_IODA_TABLE_RESET = 6,
265	287	};
266	288
267		-enum OpalPciResetState { OPAL_DEASSERT_RESET = 0, OPAL_ASSERT_RESET = 1 };
	289	+enum OpalPciResetState {
	290	+ OPAL_DEASSERT_RESET = 0,
	291	+ OPAL_ASSERT_RESET = 1
	292	+};
268	293
	294	+enum OpalPciMaskAction {
	295	+ OPAL_UNMASK_ERROR_TYPE = 0,
	296	+ OPAL_MASK_ERROR_TYPE = 1
	297	+};
	298	+
	299	+enum OpalSlotLedType {
	300	+ OPAL_SLOT_LED_ID_TYPE = 0,
	301	+ OPAL_SLOT_LED_FAULT_TYPE = 1
	302	+};
	303	+
	304	+enum OpalLedAction {
	305	+ OPAL_TURN_OFF_LED = 0,
	306	+ OPAL_TURN_ON_LED = 1,
	307	+ OPAL_QUERY_LED_STATE_AFTER_BUSY = 2
	308	+};
	309	+
	310	+enum OpalEpowStatus {
	311	+ OPAL_EPOW_NONE = 0,
	312	+ OPAL_EPOW_UPS = 1,
	313	+ OPAL_EPOW_OVER_AMBIENT_TEMP = 2,
	314	+ OPAL_EPOW_OVER_INTERNAL_TEMP = 3
	315	+};
	316	+
269	317	struct opal_machine_check_event {
270	318	enum OpalMCE_Version version:8; /* 0x00 */
271	319	uint8_t in_use; /* 0x01 */
272	320
...	...	@@ -314,8 +362,74 @@
314	362	} u;
315	363	};
316	364
	365	+/**
	366	+ * This structure defines the overlay which will be used to store PHB error
	367	+ * data upon request.
	368	+ */
	369	+enum {
	370	+ OPAL_P7IOC_NUM_PEST_REGS = 128,
	371	+};
	372	+
	373	+struct OpalIoP7IOCPhbErrorData {
	374	+ uint32_t brdgCtl;
	375	+
	376	+ // P7IOC utl regs
	377	+ uint32_t portStatusReg;
	378	+ uint32_t rootCmplxStatus;
	379	+ uint32_t busAgentStatus;
	380	+
	381	+ // P7IOC cfg regs
	382	+ uint32_t deviceStatus;
	383	+ uint32_t slotStatus;
	384	+ uint32_t linkStatus;
	385	+ uint32_t devCmdStatus;
	386	+ uint32_t devSecStatus;
	387	+
	388	+ // cfg AER regs
	389	+ uint32_t rootErrorStatus;
	390	+ uint32_t uncorrErrorStatus;
	391	+ uint32_t corrErrorStatus;
	392	+ uint32_t tlpHdr1;
	393	+ uint32_t tlpHdr2;
	394	+ uint32_t tlpHdr3;
	395	+ uint32_t tlpHdr4;
	396	+ uint32_t sourceId;
	397	+
	398	+ uint32_t rsv3;
	399	+
	400	+ // Record data about the call to allocate a buffer.
	401	+ uint64_t errorClass;
	402	+ uint64_t correlator;
	403	+
	404	+ //P7IOC MMIO Error Regs
	405	+ uint64_t p7iocPlssr; // n120
	406	+ uint64_t p7iocCsr; // n110
	407	+ uint64_t lemFir; // nC00
	408	+ uint64_t lemErrorMask; // nC18
	409	+ uint64_t lemWOF; // nC40
	410	+ uint64_t phbErrorStatus; // nC80
	411	+ uint64_t phbFirstErrorStatus; // nC88
	412	+ uint64_t phbErrorLog0; // nCC0
	413	+ uint64_t phbErrorLog1; // nCC8
	414	+ uint64_t mmioErrorStatus; // nD00
	415	+ uint64_t mmioFirstErrorStatus; // nD08
	416	+ uint64_t mmioErrorLog0; // nD40
	417	+ uint64_t mmioErrorLog1; // nD48
	418	+ uint64_t dma0ErrorStatus; // nD80
	419	+ uint64_t dma0FirstErrorStatus; // nD88
	420	+ uint64_t dma0ErrorLog0; // nDC0
	421	+ uint64_t dma0ErrorLog1; // nDC8
	422	+ uint64_t dma1ErrorStatus; // nE00
	423	+ uint64_t dma1FirstErrorStatus; // nE08
	424	+ uint64_t dma1ErrorLog0; // nE40
	425	+ uint64_t dma1ErrorLog1; // nE48
	426	+ uint64_t pestA[OPAL_P7IOC_NUM_PEST_REGS];
	427	+ uint64_t pestB[OPAL_P7IOC_NUM_PEST_REGS];
	428	+};
	429	+
317	430	typedef struct oppanel_line {
318		- /* XXX */
	431	+ const char * line;
	432	+ uint64_t line_len;
319	433	} oppanel_line_t;
320	434
321	435	/* API functions */
...	...	@@ -412,6 +526,15 @@
412	526	uint16_t dma_window_number, uint64_t pci_start_addr,
413	527	uint64_t pci_mem_size);
414	528	int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
	529	+
	530	+int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer, uint64_t diag_buffer_len);
	531	+int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer, uint64_t diag_buffer_len);
	532	+int64_t opal_pci_fence_phb(uint64_t phb_id);
	533	+int64_t opal_pci_reinit(uint64_t phb_id, uint8_t reinit_scope);
	534	+int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
	535	+int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
	536	+int64_t opal_get_epow_status(uint64_t *status);
	537	+int64_t opal_set_system_attention_led(uint8_t led_action);
415	538
416	539	/* Internal functions */
417	540	extern int early_init_dt_scan_opal(unsigned long node, const char uname, int depth, void data);
...	...	@@ -99,4 +99,12 @@
99	99	OPAL_CALL(opal_pci_map_pe_dma_window, OPAL_PCI_MAP_PE_DMA_WINDOW);
100	100	OPAL_CALL(opal_pci_map_pe_dma_window_real, OPAL_PCI_MAP_PE_DMA_WINDOW_REAL);
101	101	OPAL_CALL(opal_pci_reset, OPAL_PCI_RESET);
	102	+OPAL_CALL(opal_pci_get_hub_diag_data, OPAL_PCI_GET_HUB_DIAG_DATA);
	103	+OPAL_CALL(opal_pci_get_phb_diag_data, OPAL_PCI_GET_PHB_DIAG_DATA);
	104	+OPAL_CALL(opal_pci_fence_phb, OPAL_PCI_FENCE_PHB);
	105	+OPAL_CALL(opal_pci_reinit, OPAL_PCI_REINIT);
	106	+OPAL_CALL(opal_pci_mask_pe_error, OPAL_PCI_MASK_PE_ERROR);
	107	+OPAL_CALL(opal_set_slot_led_status, OPAL_SET_SLOT_LED_STATUS);
	108	+OPAL_CALL(opal_get_epow_status, OPAL_GET_EPOW_STATUS);
	109	+OPAL_CALL(opal_set_system_attention_led, OPAL_SET_SYSTEM_ATTENTION_LED);
...	...	@@ -1294,9 +1294,9 @@
1294	1294	pci_add_flags(PCI_REASSIGN_ALL_RSRC);
1295	1295
1296	1296	/* Reset IODA tables to a clean state */
1297		- rc = opal_pci_reset(phb_id, OPAL_PCI_IODA_RESET, OPAL_ASSERT_RESET);
	1297	+ rc = opal_pci_reset(phb_id, OPAL_PCI_IODA_TABLE_RESET, OPAL_ASSERT_RESET);
1298	1298	if (rc)
1299		- pr_warning(" OPAL Error %ld performing IODA reset !\n", rc);
	1299	+ pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc);
1300	1300	opal_pci_set_pe(phb_id, 0, 0, 7, 1, 1 , OPAL_MAP_PE);
1301	1301	}
1302	1302