ARM: Add 799270 erratum workaround

799270: Writing ACTLR.SMP when the L2 cache has been idle for an extended
	period may not work correctly.

Description:
If the L2 cache logic clock is stopped because of L2 inactivity, setting or
clearing the ACTLR.SMP bit might not be effective. The bit is modified in the
ACTLR, meaning a read of the register returns the updated value. However the
logic that uses that bit retains the previous value.

1) The L2 cache block has been idle for 256 or more cycles with no memory requests
   from any core, no external snoops, and no ACP requests.

2) A CPU executes an “MCR p15,0,r0,c1,c0,1” instruction (write the ACTLR register)
   that modifies ACTLR[6].

Implications:
If the errata conditions occur when the ACTLR.SMP bit is being set at boot, the
instruction cache or TLB could become incoherent, as that CPU would not receive
necessary DVM requests.

Workaround:
The following code must be executed with all interrupts disabled
r1 must contain the value of an Non-cacheable, SO, or Dev memory location
or register

(typically a memory mapped register with no read side effects would be used)
mrc p15,0,r0,c1,c0,1 ; read current value of ACTLR
orr r0,r0,#0x40 ; set/clear SMP bit (ACTLR[6])
ldr r1, [r1] ; read a device register (location guaranteed not to hit the L1 cache)
and r1,r1,#0 ;
orr r0,r0,r1 ; create dummy dependency between dummy load and MCR to write SMP
MCR p15,0,r0,c1,c0,1
; Write CP15 ACTLR
ISB
DSB

Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>