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Commit fda9203b924a8b4caa68fb4a2df5c954f9eb846a

Authored by Florian Fainelli
Committed by Jason Cooper
1 parent a5042de268
Exists in ti-lsk-linux-4.1.y and in 10 other branches dlt-processor-sdk-linux-03.00.00.04, processor-sdk-linux-02.00.01, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04

Documentation: bcm7120-l2: Add Broadcom BCM7120-style L2 binding 

This patch adds the Device Tree binding document for the Broadcom
BCM7120-style Set-top-box Level 2 interrupt controller hardware.

We provide some ascii art explaining the different roles and reasons why
some properties are introduced to represent that interrupt controller.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Link: https://lkml.kernel.org/r/1410309862-27784-3-git-send-email-f.fainelli@gmail.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

Showing 1 changed file with 86 additions and 0 deletions Side-by-side Diff

Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
Diff comments   View file @ fda9203
  1 +Broadcom BCM7120-style Level 2 interrupt controller
  2 +
  3 +This interrupt controller hardware is a second level interrupt controller that
  4 +is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
  5 +platforms. It can be found on BCM7xxx products starting with BCM7120.
  6 +
  7 +Such an interrupt controller has the following hardware design:
  8 +
  9 +- outputs multiple interrupts signals towards its interrupt controller parent
  10 +
  11 +- controls how some of the interrupts will be flowing, whether they will
  12 + directly output an interrupt signal towards the interrupt controller parent,
  13 + or if they will output an interrupt signal at this 2nd level interrupt
  14 + controller, in particular for UARTs
  15 +
  16 +- not all 32-bits within the interrupt controller actually map to an interrupt
  17 +
  18 +The typical hardware layout for this controller is represented below:
  19 +
  20 +2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
  21 +
  22 +0 -----[ MUX ] ------------|==========> GIC interrupt 75
  23 + \-----------\
  24 + |
  25 +1 -----[ MUX ] --------)---|==========> GIC interrupt 76
  26 + \------------|
  27 + |
  28 +2 -----[ MUX ] --------)---|==========> GIC interrupt 77
  29 + \------------|
  30 + |
  31 +3 ---------------------|
  32 +4 ---------------------|
  33 +5 ---------------------|
  34 +7 ---------------------|---|===========> GIC interrupt 66
  35 +9 ---------------------|
  36 +10 --------------------|
  37 +11 --------------------/
  38 +
  39 +6 ------------------------\
  40 + |===========> GIC interrupt 64
  41 +8 ------------------------/
  42 +
  43 +12 ........................ X
  44 +13 ........................ X (not connected)
  45 +..
  46 +31 ........................ X
  47 +
  48 +Required properties:
  49 +
  50 +- compatible: should be "brcm,bcm7120-l2-intc"
  51 +- reg: specifies the base physical address and size of the registers
  52 +- interrupt-controller: identifies the node as an interrupt controller
  53 +- #interrupt-cells: specifies the number of cells needed to encode an interrupt
  54 + source, should be 1.
  55 +- interrupt-parent: specifies the phandle to the parent interrupt controller
  56 + this one is cascaded from
  57 +- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
  58 + node, valid values depend on the type of parent interrupt controller
  59 +- brcm,int-map-mask: 32-bits bit mask describing how many and which interrupts
  60 + are wired to this 2nd level interrupt controller, and how they match their
  61 + respective interrupt parents. Should match exactly the number of interrupts
  62 + specified in the 'interrupts' property.
  63 +
  64 +Optional properties:
  65 +
  66 +- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
  67 + wakeup source for system suspend/resume.
  68 +
  69 +- brcm,int-fwd-mask: if present, a 32-bits bit mask to configure for the
  70 + interrupts which have a mux gate, typically UARTs. Setting these bits will
  71 + make their respective interrupts outputs bypass this 2nd level interrupt
  72 + controller completely, it completely transparent for the interrupt controller
  73 + parent
  74 +
  75 +Example:
  76 +
  77 +irq0_intc: interrupt-controller@f0406800 {
  78 + compatible = "brcm,bcm7120-l2-intc";
  79 + interrupt-parent = <&intc>;
  80 + #interrupt-cells = <1>;
  81 + reg = <0xf0406800 0x8>;
  82 + interrupt-controller;
  83 + interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
  84 + brcm,int-map-mask = <0xeb8>, <0x140>;
  85 + brcm,int-fwd-mask = <0x7>;
  86 +};