29 Dec, 2014
1 commit
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Commit 0e5bdb3f9fa5 (clk: rockchip: switch to using the new cpuclk type
for armclk) didn't take into account that the divider used on rk3288
are of the (n+1) type.The rk3066 and rk3188 socs use more complex divider types making it
necessary for the list-elements to be the real register-values to write.Therefore reduce divider values in the table accordingly so that they
really are the values that should be written to the registers and match
the dividers actually specified for the rk3288.Reported-by: Sonny Rao
Fixes: 0e5bdb3f9fa5 ("clk: rockchip: switch to using the new cpuclk type for armclk")
Signed-off-by: Heiko Stuebner
Reviewed-by: Doug Anderson
Cc: stable@vger.kernel.org
28 Nov, 2014
2 commits
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This patch adds the 2 physical clocks for the mmc (drive and sample). They're
mostly there for the phase properties, but they also show the true clock
(by dividing by RK3288_MMC_CLKGEN_DIV).The drive and sample phases are generated by dividing an upstream parent clock
by 2, this allows us to adjust the phase by 90 deg.There's also an option to have up to 255 delay elements (40-80 picoseconds long).
This driver uses those elements (under the assumption that they're 60 ps long)
to generate approximate 22.5 degrees options. 67.5 (22.5*3) might be as high as
90 deg if the delay elements are as big as 80 ps, so a finer division (smaller
than 22.5) was not picked because the phase might not be monotonic anymore.Suggested-by: Heiko Stuebner
Signed-off-by: Alexandru M Stan
Signed-off-by: Heiko Stuebner -
This exposes the clock that comes out of the i2s block which generally
goes to the audio codec.Signed-off-by: Sonny Rao
[removed CLK_SET_RATE_PARENT from original patch]
Signed-off-by: Heiko Stuebner
27 Nov, 2014
1 commit
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The DMC clocks need to be turned off at runtime. Use the newly
assigned clock IDs to export them.Signed-off-by: Jeff Chen
[dianders: split into two patches; adjusted commit msg]
Signed-off-by: Doug Anderson
Signed-off-by: Heiko Stuebner
25 Nov, 2014
2 commits
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Add the new flag to gpll and cpll on rk3188 and similar and to
gpll, cpll and npll on rk3288.Signed-off-by: Heiko Stuebner
Reviewed-by: Kever Yang
Tested-by: Kever Yang -
This adds a flag parameter to plls that allows us to create
special flags to tweak the behaviour of the plls if necessary.Signed-off-by: Heiko Stuebner
Reviewed-by: Kever Yang
Tested-by: Kever Yang
16 Nov, 2014
2 commits
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According to rk3288 trm, the mux selector locate at bit[12:11]
of CRU_CLKSEL13_CON shows:
2'b00: select HOST0 USB pll clock (clk_otgphy1)
2'b01: select HOST1 USB pll clock (clk_otgphy2)
2'b10: select OTG USB pll clock (clk_otgphy0)The clock map is in Fig. 3-4 CRU Clock Architecture Diagram 3
- clk_otgphy0 -> USB PHY OTG
- clk_otgphy1 -> USB PHY host0
- clk_otgphy2 -> USB PHY host1Signed-off-by: Kever Yang
Signed-off-by: Heiko Stuebner -
According to rk3288 trm, the clk_usbphy480m_gate is located at
bit 14 of CRU_CLKGATE5_CON register.Signed-off-by: Kever Yang
Signed-off-by: Heiko Stuebner
13 Nov, 2014
1 commit
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Currently there is no driver owning these clocks and they have to stay
up for the system to function properly, so let's mark them as
CLK_IGNORE_UNUSED.Without this patch we have trouble with suspend/resume and we have
trouble turning the eDP back on if it ever idles off.Signed-off-by: Dmitry Torokhov
Reviewed-by: Doug Anderson
Tested-by: Doug Anderson
Reviewed-by: Kever Yang
Signed-off-by: Heiko Stuebner
11 Nov, 2014
1 commit
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save and restore some clks, which might be changed in suspend.
Signed-off-by: Tony Xie
Signed-off-by: Chris Zhong
Reviewed-by: Doug Anderson
Tested-by: Doug Anderson
Signed-off-by: Heiko Stuebner
05 Nov, 2014
1 commit
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The rockchip clock driver use CLK_IGNORE_UNUSED flag to make sure
all the clocks are available like default power on state.
We have implement the clock manage in most of rockchip drivers,
it is time to remove it for power save.
Instead we add CLK_IGNORE_UNUSED for some clock nodes which should
be on during boot or no module driver in kernel will initialize it.Signed-off-by: Kever Yang
Reviewed-by: Doug Anderson
Tested-by: Doug Anderson
Signed-off-by: Heiko Stuebner
30 Oct, 2014
1 commit
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dclk_vop0/1 is the source of HDMI TMDS clock in rk3288, usually we
use 594MHz for clock source of dclk_vop0/1.HDMI CTS 7-9 require TMDS Clock jitter is lower than 0.25*Tbit:
TMDS clock(MHz) CTS require jitter (ps)
297 84.2
148.5 168
74.25 336
27 1247PLL BW and VCO frequency effects the jitter of PLL output clock,
clock jitter is better if BW is lower or VCO frequency is higher.If PLL use default setting of RK3066_PLL_RATE( 594000000, 2, 198, 4),
the TMDS Clock jitter is higher than 250ps, which means we can't
pass the test when TMDS clock is 297MHz or 148.5MHz.If we use RK3066_PLL_RATE_BWADJ(594000000, 1, 198, 8, 1),
the TMDS Clock jitter is about 60ps and we can pass all test case.So we need this patch to make hdmi si test pass.
Signed-off-by: Kever Yang
Reviewed-by: Doug Anderson
Signed-off-by: Heiko Stuebner
20 Oct, 2014
5 commits
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The possible sources for the rk3288-gpu-clock also include the npll,
making it the same list of sources as for uart0.This patch make a common source for uart0 pll src and sclk_gpu,
so that gpu can get its clock from npll.Signed-off-by: Kever Yang
Signed-off-by: Heiko Stuebner -
Removing the CLK_SET_RATE_PARENT from i2s_clkout, to limit i2s0_clkout
to select between its two parent without being able influence the core
i2s clock.Tested on rk3288 board, suggested by Heiko.
Signed-off-by: Jianqun
Signed-off-by: Heiko Stuebner -
This patch add 400MHz and 500MHz to clock rate table for rk3288.
Signed-off-by: Kever Yang
Reviewed-by: Doug Anderson
Tested-by: Doug Anderson
Signed-off-by: Heiko Stuebner -
We'd like to be able to call clk_set_rate() on aclk_cpu (a gate) at
bootup. In order for this to have any effect we need its parent
(aclk_cpu_pre) to percolate the rate change to _its_ parent
(aclk_cpu_src). Add CLK_SET_RATE_PARENT to make this happen.Signed-off-by: Doug Anderson
Signed-off-by: Heiko Stuebner -
The parent should be spdif_8ch_pre not spdif_8ch_src, which doesn't
exist and looks to be a typo. The TRM also confirms this.Signed-off-by: Sonny Rao
Signed-off-by: Heiko Stuebner
01 Oct, 2014
2 commits
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Add infrastructure to write the correct value to the restart register and
register the restart notifier for both rk3188 (including rk3066) and rk3288.Signed-off-by: Heiko Stuebner
Signed-off-by: Guenter Roeck -
The relation of i2s nodes as follows:
i2s_src 0 0 594000000 0
i2s_frac 0 0 11289600 0
i2s_pre 0 0 11289600 0
sclk_i2s0 0 0 11289600 0
i2s0_clkout 0 0 11289600 0
hclk_i2s0 1 1 99000000 0sclk_i2s0 is the master clock, when to set rate of sclk_i2s0, should
allow to set its parent's rate, by add flag CLK_SET_RATE_PARENT for
"i2s_frac", "i2s_pre", "i2s0_clkout" and "sclk_i2s0".Tested on rk3288 board using max98090, with command "aplay "
Change-Id: I12faad082566532b65a7de8c0a6845e1c17870e6
Signed-off-by: Jianqun
Signed-off-by: Heiko Stuebner
27 Sep, 2014
3 commits
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This adds the necessary soc-specific divider values and switches the armclk
to use the newly introduced cpuclk type.Signed-off-by: Heiko Stuebner
Reviewed-by: Doug Anderson
Tested-by: Doug Anderson -
Rockchip SoCs contain clocks tightly bound to the armclk, where the best
rate / divider is supplied by the vendor after careful measuring.
Often this ideal rate may be greater than the current rate.Therefore prevent the ccf from trying to set these dividers itself by
setting them to read-only.In the case of the rk3066, this also includes the aclk_cpu, which makes it
necessary to also split its direct child-clocks (pclk_cpu, hclk_cpu, ...)
into individual definitions for rk3066 and rk3188.Signed-off-by: Heiko Stuebner
Reviewed-by: Doug Anderson
Tested-by: Doug Anderson -
In RK3288, APLL lock status bit is in GRF_SOC_STATUS1,
but in RK3188, is GRFSOC_STATUS0.Signed-off-by: Jianqun
Also name the constant accordingly as GRF_SOC_STATUS1
to prevent confusion.
Signed-off-by: Heiko Stuebner
Reviewed-by: Doug Anderson
Tested-by: Doug Anderson
26 Sep, 2014
5 commits
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This patch add the clock node in PD_VIDEO
Signed-off-by: Kever Yang
Reviewed-by: Heiko Stuebner
Reviewed-by: Doug Anderson
Tested-by: Doug Anderson
Signed-off-by: Mike Turquette -
This patch use the new defined clock ID to initial the clock nodes.
Signed-off-by: Kever Yang
Reviewed-by: Doug Anderson
Reviewed-by: Heiko Stuebner
Signed-off-by: Mike Turquette -
The npll on rk3288 is exactly the same pll type as the other 4. Yet it
was missing the link to the rate table, making rate changes impossible.
Change that by setting the table.Signed-off-by: Heiko Stuebner
Reviewed-by: Doug Anderson
Tested-by: Doug Anderson
Tested-by: Kever Yang
Signed-off-by: Mike Turquette -
The rk3288 actually has 12 softresets, so fix the register count.
Signed-off-by: Mark yao
Reviewed-by: Heiko Stuebner
Reviewed-by: Doug Anderson
Signed-off-by: Mike Turquette
18 Sep, 2014
1 commit
11 Sep, 2014
1 commit
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The dwc2 usb controller also uses agressive clock gating, which in this
case leads to hclk_peri getting disabled and hanging the system.
Therefore move it to the critical clocks until we also control that
part of the system.Signed-off-by: Heiko Stuebner
Signed-off-by: Mike Turquette
04 Sep, 2014
1 commit
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The clocks for i2c1 and i2c2 are flipped. The clock tree matched the
Technical Reference Manual (TRM) but the TRM was wrong. Swap them in
the clock tree. This was determined experimentally (by Addy) and
confirmed by the Rockchip IC team.Signed-off-by: Doug Anderson
Reported-by: Addy Ke
Reviewed-by: Heiko Stuebner
Signed-off-by: Mike Turquette
03 Sep, 2014
1 commit
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The clock-tree contains clocks that should never get disabled automatically.
One example are the base ACLKs, the base supplies for all peripherals.Therefore add a structure similar to the sunxi clock-tree to protect these
special clocks from being disabled.Signed-off-by: Heiko Stuebner
Tested-by: Doug Anderson
Tested-by: Kever Yang
Signed-off-by: Mike Turquette
14 Jul, 2014
1 commit
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Add the clock tree definition for the new rk3288 SoC.
Signed-off-by: Heiko Stuebner
Acked-By: Max Schwarz
Tested-By: Max Schwarz
Signed-off-by: Mike Turquette