03 Jun, 2009
1 commit
-
Currently, whenever an erratum workaround is enabled, it will be
applied whether or not the erratum is relevent for the CPU. This
patch changes this - we check the variant and revision fields in the
main ID register to determine which errata to apply.We also avoid re-applying erratum 460075 if it has already been applied.
Applying this fix in non-secure mode results in the kernel failing to
boot (or even do anything.)This fixes booting on some ARMv7 based platforms which otherwise
silently fail.Acked-by: Catalin Marinas
Signed-off-by: Russell King
03 May, 2009
1 commit
-
* master.kernel.org:/home/rmk/linux-2.6-arm: (45 commits)
[ARM] 5489/1: ARM errata: Data written to the L2 cache can be overwritten with stale data
[ARM] 5490/1: ARM errata: Processor deadlock when a false hazard is created
[ARM] 5487/1: ARM errata: Stale prediction on replaced interworking branch
[ARM] 5488/1: ARM errata: Invalidation of the Instruction Cache operation can fail
davinci: DM644x: NAND: update partitioning
davinci: update DM644x support in preparation for more SoCs
davinci: DM644x: rename board file
davinci: update pin-multiplexing support
davinci: serial: generalize for more SoCs
davinci: DM355 IRQ Definitions
davinci: DM646x: add interrupt number and priorities
davinci: PSC: Clear bits in MDCTL reg before setting new bits
davinci: gpio bugfixes
davinci: add EDMA driver
davinci: timers: use clk_get_rate()
[ARM] pxa/littleton: add missing da9034 touchscreen support
[ARM] pxa/zylonite: configure GPIO18/19 correctly, used by 2 GPIO expanders
[ARM] pxa/zylonite: fix the issue of unused SDATA_IN_1 pin get AC97 not working
[ARM] pxa: make ads7846 on corgi and spitz to sync on HSYNC
[ARM] pxa: remove unused CPU_FREQ_PXA Kconfig symbol
...
01 May, 2009
3 commits
-
This patch is a workaround for the 460075 Cortex-A8 (r2p0) erratum. It
configures the L2 cache auxiliary control register so that the Write
Allocate mode for the L2 cache is disabled.Signed-off-by: Catalin Marinas
Signed-off-by: Russell King -
This patch adds a workaround for the 458693 Cortex-A8 (r2p0)
erratum. It sets the corresponding bits in the auxiliary control
register so that the PLD instruction becomes a NOP.Signed-off-by: Catalin Marinas
Signed-off-by: Russell King -
This patch adds the workaround for the 430973 Cortex-A8 (r1p0..r1p2)
erratum. The BTAC/BTB is now flushed at every context switch.Signed-off-by: Catalin Marinas
Signed-off-by: Russell King
28 Apr, 2009
1 commit
-
arm is placing some code in the .text.init section, but it does not
reference that section in its linker scripts.This change moves this code from the .text.init section to the
.init.text section, which is presumably where it belongs.Signed-off-by: Tim Abbott
Acked-by: Russell King
Acked-by: Sam Ravnborg
Signed-off-by: Linus Torvalds
27 Nov, 2008
1 commit
10 Nov, 2008
1 commit
-
Since WFI may cause the processor to enter a low-power mode, data may
still be in the write buffer. This patch adds a DSB (or DWB) to the
cpu_(v6|v7)_do_idle functions before the WFI.Signed-off-by: Catalin Marinas
07 Nov, 2008
1 commit
-
As a result of the ptebits changes, we ended up marking device mappings
as normal memory on ARMv7 CPUs, resulting in undesirable behaviour with
serial ports and the like. While reviewing the section mapping table
entries, other errors in the memory type settings for devices were
detected and confirmed to prevent Xscale3 platforms booting.Tested on:
OMAP34xx (ARMv7),
OMAP24xx (ARMv6),
OMAP16xx (ARM926T, ARMv5),
PXA311 (Xscale3),
PXA272 (Xscale),
PXA255 (Xscale),
IXP42x (Xscale),
S3C2410 (ARM920T, ARMv4T),
ARM720T (ARMv4T)
StrongARM-110 (ARMv4)Acked-by: Tony Lindgren
Tested-by: Robert Jarzmik
Tested-by: Mike Rapoport
Tested-by: Ben Dooks
Tested-by: Anders Grafström
Signed-off-by: Russell King
06 Nov, 2008
2 commits
-
This patch adds the SMP/nAMP mode setting to __v7_setup and also sets
TTBR to shared page table walks if SMP is enabled. The PTWs are also
marked inner cacheable for both SMP and UP modes (setting this is fine
even if the CPU doesn't support the feature).Signed-off-by: Jon Callan
Signed-off-by: Catalin Marinas -
This register is set in __enable_mmu in the head.S file.
Signed-off-by: Catalin Marinas
23 Oct, 2008
1 commit
-
A typo caused these values to be swapped leading to incorrect memory
type attributes.Signed-off-by: Catalin Marinas
Signed-off-by: Russell King
10 Oct, 2008
1 commit
-
Conflicts:
arch/arm/Kconfig
03 Oct, 2008
1 commit
-
These instructions were placed in the code directly as opcodes because
early compilers didn't support them. Toolchains supporting ARMv7
understand these instructions and the patch puts the mnemonics back.Signed-off-by: Catalin Marinas
Signed-off-by: Russell King
01 Oct, 2008
4 commits
-
asm code really wants asm/hwcap.h, so include that instead.
Signed-off-by: Russell King
-
Signed-off-by: Russell King
-
Signed-off-by: Russell King
-
There are actually only four separate implementations of set_pte_ext.
Use assembler macros to insert code for these into the proc-*.S files.Signed-off-by: Russell King
01 Sep, 2008
1 commit
-
This declaration specifies the "function" type and size for various
assembly functions, mainly needed for generating the correct branch
instructions in Thumb-2.Signed-off-by: Catalin Marinas
Signed-off-by: Russell King
24 Apr, 2008
1 commit
-
The proc-*.S files have the _prefetch_abort pointer placed at the end
of the processor structure but the cpu-multi32.h defines it in the
second position. The patch also fixes the support for XSC3 and the
MMU-less CPUs (740, 7tdmi, 940, 946 and 9tdmi).Signed-off-by: Catalin Marinas
Signed-off-by: Russell King
19 Apr, 2008
1 commit
-
This patch adds a prefetch abort handler similar to the data abort one
and renames the latter for consistency. Initial implementation by Paul
Brook with some renaming by Catalin Marinas.Signed-off-by: Paul Brook
Signed-off-by: Catalin Marinas
21 Jul, 2007
2 commits
-
This patch adds the necessary ifdef's to the proc-v7.S code and
defines the v7wbi_tlb_fns macro in pgtable-nommu.hSigned-off-by: Catalin Marinas
Signed-off-by: Russell King -
The auxiliary control and the L2 auxiliary control registers are
Cortex-A8 specific. They need to be removed from the generic ARMv7
support code.Signed-off-by: Catalin Marinas
Signed-off-by: Russell King
30 May, 2007
1 commit
-
We are currently using the ARMv6 operations but need to duplicate some
of the code because of the introduction of the new CPU barrier
instructions in ARMv7.Signed-off-by: Catalin Marinas
Signed-off-by: Russell King
09 May, 2007
1 commit
-
This patch adds support for the ARMv7 cores.
Signed-off-by: Catalin Marinas
Signed-off-by: Russell King