19 Apr, 2014
1 commit
-
shiraz.hashim@st.com email-id doesn't exist anymore as he has left the
company. Replace ST's id with shiraz.linux.kernel@gmail.com.It also updates .mailmap file to fix address for 'git shortlog'.
Signed-off-by: Viresh Kumar
Cc: Shiraz Hashim
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
16 Apr, 2014
1 commit
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We are flagging the parent IRQ as chained, then we must also
make sure to call the chained_irq_[enter|exit] functions for
things to work smoothly.Signed-off-by: Linus Walleij
Link: http://lkml.kernel.org/r/1397550484-7119-1-git-send-email-linus.walleij@linaro.org
Signed-off-by: Thomas Gleixner
06 Apr, 2014
4 commits
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Pull ARM SoC driver changes from Arnd Bergmann:
"These changes are mostly for ARM specific device drivers that either
don't have an upstream maintainer, or that had the maintainer ask us
to pick up the changes to avoid conflicts.A large chunk of this are clock drivers (bcm281xx, exynos, versatile,
shmobile), aside from that, reset controllers for STi as well as a
large rework of the Marvell Orion/EBU watchdog driver are notable"* tag 'drivers-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (99 commits)
Revert "dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac."
Revert "net: stmmac: Add SOCFPGA glue driver"
ARM: shmobile: r8a7791: Fix SCIFA3-5 clocks
ARM: STi: Add reset controller support to mach-sti Kconfig
drivers: reset: stih416: add softreset controller
drivers: reset: stih415: add softreset controller
drivers: reset: Reset controller driver for STiH416
drivers: reset: Reset controller driver for STiH415
drivers: reset: STi SoC system configuration reset controller support
dts: socfpga: Add sysmgr node so the gmac can use to reference
dts: socfpga: Add support for SD/MMC on the SOCFPGA platform
reset: Add optional resets and stubs
ARM: shmobile: r7s72100: fix bus clock calculation
Power: Reset: Generalize qnap-poweroff to work on Synology devices.
dts: socfpga: Update clock entry to support multiple parents
ARM: socfpga: Update socfpga_defconfig
dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac.
net: stmmac: Add SOCFPGA glue driver
watchdog: orion_wdt: Use %pa to print 'phys_addr_t'
drivers: cci: Export CCI PMU revision
... -
Pull ARM SoC specific changes from Arnd Bergmann:
"Lots of changes specific to one of the SoC families. Some that stick
out are:- mach-qcom gains new features, most importantly SMP support for the
newer chips (Stephen Boyd, Rohit Vaswani)
- mvebu gains support for three new SoCs: Armada 375, 380 and 385
(Thomas Petazzoni and Free-electrons team)
- SMP support for Rockchips (Heiko Stübner)
- Lots of i.MX changes (Shawn Guo)
- Added support for BCM5301x SoC (Hauke Mehrtens)
- Multiplatform support for Marvell Kirkwood and Dove (Andrew Lunn
and Sebastian Hesselbarth doing the final part of a long journey)
- Unify davinci platforms and remove obsolete ones (Sekhar Nori, Arnd
Bergmann)"* tag 'soc-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (126 commits)
ARM: sunxi: Select HAVE_ARM_ARCH_TIMER
ARM: cache-tauros2: remove ARMv6 code
ARM: mvebu: don't select CONFIG_NEON
ARM: davinci: fix DT booting with default defconfig
ARM: configs: bcm_defconfig: enable bcm590xx regulator support
ARM: davinci: remove tnetv107x support
MAINTAINERS: Update ARM STi maintainers
ARM: restrict BCM_KONA_UART to ARCH_BCM_MOBILE
ARM: bcm21664: Add board support.
ARM: sunxi: Add the new watchog compatibles to the reboot code
ARM: enable ARM_HAS_SG_CHAIN for multiplatform
ARM: davinci: remove da8xx_omapl_defconfig
ARM: davinci: da8xx: fix multiple watchdog device registration
ARM: davinci: add da8xx specific configs to davinci_all_defconfig
ARM: davinci: enable da8xx build concurrently with older devices
ARM: BCM5301X: workaround suppress fault
ARM: BCM5301X: add early debugging support
ARM: BCM5301X: initial support for the BCM5301X/BCM470X SoCs with ARM CPU
ARM: mach-bcm: Remove GENERIC_TIME
ARM: shmobile: APMU: Fix warnings due to improper printk formats
... -
Pull ARM SoC cleanups from Arnd Bergmann:
"These cleanup patches are mainly move stuff around and should all be
harmless. They are mainly split out so that other branches can be
based on top to avoid conflicts.Notable changes are:
- We finally remove all mach/timex.h, after CLOCK_TICK_RATE is no
longer used (Uwe Kleine-König)
- The Qualcomm MSM platform is split out into legacy mach-msm and
new-style mach-qcom, to allow easier maintainance of the new
hardware support without regressions (Kumar Gala)
- A rework of some of the Kconfig logic to simplify multiplatform
support (Rob Herring)
- Samsung Exynos gets closer to supporting multiplatform (Sachin
Kamat and others)
- mach-bcm3528 gets merged into mach-bcm (Stephen Warren)
- at91 gains some common clock framework support (Alexandre Belloni,
Jean-Jacques Hiblot and other French people)"* tag 'cleanup-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (89 commits)
ARM: hisi: select HAVE_ARM_SCU only for SMP
ARM: efm32: allow uncompress debug output
ARM: prima2: build reset code standalone
ARM: at91: add PWM clock
ARM: at91: move sam9261 SoC to common clk
ARM: at91: prepare common clk transition for sam9261 SoC
ARM: at91: updated the at91_dt_defconfig with support for the ADS7846
ARM: at91: dt: sam9261: Device Tree support for the at91sam9261ek
ARM: at91: dt: defconfig: Added the sam9261 to the list of DT-enabled SOCs
ARM: at91: dt: Add at91sam9261 dt SoC support
ARM: at91: switch sam9rl to common clock framework
ARM: at91/dt: define main clk frequency of at91sam9rlek
ARM: at91/dt: define at91sam9rl clocks
ARM: at91: prepare common clk transition for sam9rl SoCs
ARM: at91: prepare sam9 dt boards transition to common clk
ARM: at91: dt: sam9rl: Device Tree for the at91sam9rlek
ARM: at91/defconfig: Add the sam9rl to the list of DT-enabled SOCs
ARM: at91: Add at91sam9rl DT SoC support
ARM: at91: prepare at91sam9rl DT transition
ARM: at91/defconfig: refresh at91sam9260_9g20_defconfig
... -
Pull ARM SoC non-critical bug fixes from Arnd Bergmann:
"Lots of isolated bug fixes that were not found to be important enough
to be submitted before the merge window or backported into stable
kernels.The vast majority of these came out of Arnd's randconfig testing and
just prevents running into build-time bugs in configurations that we
do not care about in practice"* tag 'fixes-non-critical-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (75 commits)
ARM: at91: fix a typo
ARM: moxart: fix CPU selection
ARM: tegra: fix board DT pinmux setup
ARM: nspire: Fix compiler warning
IXP4xx: Fix DMA masks.
Revert "ARM: ixp4xx: Make dma_set_coherent_mask common, correct implementation"
IXP4xx: Fix Goramo Multilink GPIO conversion.
Revert "ARM: ixp4xx: fix gpio rework"
ARM: tegra: make debug_ll code build for ARMv6
ARM: sunxi: fix build for THUMB2_KERNEL
ARM: exynos: add missing include of linux/module.h
ARM: exynos: fix l2x0 saved regs handling
ARM: samsung: select CRC32 for SAMSUNG_PM_CHECK
ARM: samsung: select ATAGS where necessary
ARM: samsung: fix SAMSUNG_PM_DEBUG Kconfig logic
ARM: samsung: allow serial driver to be disabled
ARM: s5pv210: enable IDE support in MACH_TORBRECK
ARM: s5p64x0: fix building with only one soc type
ARM: s3c64xx: select power domains only when used
ARM: s3c64xx: MACH_SMDK6400 needs HSMMC1
...
31 Mar, 2014
1 commit
-
It is advisable to disable the NMI before registering the IRQ handler as
registering the IRQ handler unmasks the IRQ on the GIC, so if U-Boot has
left the NMI enabled and the NMI pin is active we will immediately get
an interrupt before any driver has claimed the downstream interrupt of
the NMI.Signed-off-by: Hans de Goede
Signed-off-by: Carlo Caione
Cc: maxime.ripard@free-electrons.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-sunxi@googlegroups.com
Link: http://lkml.kernel.org/r/1395939759-11135-3-git-send-email-carlo@caione.org
Signed-off-by: Thomas Gleixner
26 Mar, 2014
1 commit
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Allwinner A20/A31 SoCs have special registers to control / (un)mask /
acknowledge NMI. This NMI controller is separated and independent from GIC.
This patch adds a new irqchip to manage NMI.Signed-off-by: Carlo Caione
Acked-by: Maxime Ripard
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-sunxi@googlegroups.com
Cc: mark.rutland@arm.com
Cc: hdegoede@redhat.com
Link: http://lkml.kernel.org/r/1395256879-8475-2-git-send-email-carlo@caione.org
Signed-off-by: Thomas Gleixner
19 Mar, 2014
2 commits
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Now that we only ack irq 0 the code can be simplified a lot.
Also switch from read / modify / write to a simple write clear:
1) This is what the android code does (it has a hack for acking irq 0
in its unmask code doing this)2) read / modify / write simply does not make sense for an irq status
register like this, if the other bits are writeable (and the data sheet says
they are not) they should be write 1 to clear, since otherwise a read /
modify / write can race with a device raising an interrupt and then clear
the pending bit unintentionallySigned-off-by: Hans de Goede
Acked-by: Maxime Ripard
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-sunxi@googlegroups.com
Link: http://lkml.kernel.org/r/1394895894-8891-3-git-send-email-hdegoede@redhat.com
Signed-off-by: Thomas Gleixner -
Since the sun4i irq chip does not require any action and clears the interrupt
when the level goes back to inactive, we don't need to mask / unmask for
non oneshot IRQs, to achieve this we make sun4i_irq_ack a nop for all irqs
except irq 0 and use handle_fasteoi_irq for all interrupts.Now there might be a case when the device reactivates the interrupt
before the RETI. But that does not matter as we run the primary
interrupt handlers with interrupts disabled.This also allows us to get rid of needing to use 2 irq_chip structs, this
means that the IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED will now influence
all interrupts rather then just irq 0, but that does not matter as the eoi
is now a nop anyways for all interrupts but irq 0.Signed-off-by: Hans de Goede
Acked-by: Maxime Ripard
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-sunxi@googlegroups.com
Link: http://lkml.kernel.org/r/1394895894-8891-2-git-send-email-hdegoede@redhat.com
Signed-off-by: Thomas Gleixner
17 Mar, 2014
1 commit
-
…m/linux/kernel/git/tmlind/linux-omap into next/fixes-non-critical
Merge "omap fixes for v3.15 merge window" from Tony Lindgren:
Fixes for omaps that would be good to get in before v3.15-rc1.
* tag 'omap-for-v3.15/fixes-for-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP4: hwmod data: correct the idlemodes for spinlock
ARM: dts: am33xx: correcting dt node unit address for usb
ARM: dts: omap4/5: Use l3_ick for the gpmc node
CLK: TI: OMAP4/5/DRA7: Remove gpmc_fck from dummy clocks
ARM: OMAP4: Fix definition of IS_PM44XX_ERRATUM
ARM: OMAP2+: INTC: Acknowledge stuck active interruptsSigned-off-by: Arnd Bergmann <arnd@arndb.de>
14 Mar, 2014
4 commits
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All IRQs except for IRQ 0 seem to not need acking, so drop acking for them.
The ENMI needs to have the ack done *after* clearing the interrupt source,
otherwise we will get a spurious interrupt for each real interrupt.So use the new IRQCHIP_EOI_THREADED flag for this in combination with
handle_fasteoi_irq. This uses a separate irq_chip struct for IRQ 0,
since we only want this behavior for IRQ 0.Signed-off-by: Hans de Goede
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-sunxi@googlegroups.com
Cc: Maxime Ripard
Link: http://lkml.kernel.org/r/1394733834-26839-5-git-send-email-hdegoede@redhat.com
Signed-off-by: Thomas Gleixner -
The comment was claiming that we were masking all irqs, while the code actually
*un*masks all of them.Signed-off-by: Hans de Goede
Acked-by: Maxime Ripard
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-sunxi@googlegroups.com
Link: http://lkml.kernel.org/r/1394733834-26839-4-git-send-email-hdegoede@redhat.com
Signed-off-by: Thomas Gleixner -
SUN4I_IRQ_VECTOR_REG containing 0 can mean one of 3 things:
1) no more irqs pending
2) irq 0 pending
3) spurious irqSo if we immediately get a reading of 0, check the irq-pending reg
to differentiate between 2 and 3. We only do this once to avoid
the extra check in the common case of 1) hapening after having
read the vector-reg once.Signed-off-by: Hans de Goede
Acked-by: Maxime Ripard
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-sunxi@googlegroups.com
Link: http://lkml.kernel.org/r/1394733834-26839-3-git-send-email-hdegoede@redhat.com
Signed-off-by: Thomas Gleixner -
The Allwinner A10 compatibles were following a slightly different compatible
patterns than the rest of the SoCs for historical reasons. Change the compatibles
to match the other pattern in the irq controller driver for consistency.Signed-off-by: Maxime Ripard
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Thomas Gleixner
12 Mar, 2014
3 commits
-
Merge the request/release callbacks which are in a separate branch for
consumption by the gpio folks.Signed-off-by: Thomas Gleixner
-
The "irqchip.h" include here is not needed as the only thing in
irqchip.h is IRQCHIP_DECLARE which this file doesn't use. Drop
it.Reported-by: Jiri Kosina
Signed-off-by: Stephen Boyd
Link: http://lkml.kernel.org/r/531F7765.40207@codeaurora.org
Signed-off-by: Thomas Gleixner -
LTO patches add __visible to the asmlinkage define, causing
compilation warnings like:drivers/irqchip/irq-gic.c:283:1: warning: 'externally_visible'
attribute have effect only on public objects [-Wattributes]Drop asmlinkage here to avoid such warnings.
Reported-by: Olof's autobuilder
Signed-off-by: Stephen Boyd
Cc: linux-arm-kernel@lists.infradead.org
Cc: khilman@linaro.org
Cc: Russell King
Cc: Josh Cartwright
Cc: Andi Kleen
Link: http://lkml.kernel.org/r/1393980030-17770-1-git-send-email-sboyd@codeaurora.org
Signed-off-by: Thomas Gleixner
10 Mar, 2014
3 commits
-
i.MX SoC changes for 3.15 from Shawn Guo:
- Support suspend from ocram (DDR IO floating) for imx6 platforms
- Add cpuidle support for imx6sl
- Sparse warning fixes for imx6sl and vf610 clock code
- Remove PWM platform code
- Support ptp and rmii clock from pad
- Support WEIM CS GPR configuration
- Random cleanups and defconfig updates* tag 'imx-soc-3.15' of git://git.linaro.org/people/shawnguo/linux-2.6: (373 commits)
ARM: imx6: drop .text.head section annotation from headsmp.S
ARM: imx6: build suspend-imx6.o with CONFIG_SOC_IMX6
ARM: imx6: rename pm-imx6q.c to pm-imx6.c
ARM: imx6: introduce CONFIG_SOC_IMX6 for i.MX6 common stuff
ARM: imx6: do not call imx6q_suspend_init() with !CONFIG_SUSPEND
ARM: imx6: call suspend_set_ops() from suspend routine
ARM: imx6: build headsmp.o only on CONFIG_SMP
ARM: imx6: move v7_cpu_resume() into suspend-imx6.S
ARM i.MX6q: Mark VPU and IPU AXI transfers as cacheable, increase IPU priority
ARM: imx6q: Add GPR6 and GPR7 register definitions for iomuxc gpr
bus: imx-weim: support CS GPR configuration
ARM: mach-imx: Kconfig: Remove IMX_HAVE_PLATFORM_IMX2_WDT from SOC_IMX53
ARM: imx_v6_v7_defconfig: Select CONFIG_DEBUG_FS
ARM: mach-imx: Select CONFIG_SRAM at ARCH_MXC level
ARM: imx: add speed grading check for i.mx6 soc
ARM: imx: avoid calling clk APIs in idle thread which may cause schedule
ARM: imx6q: support ptp and rmii clock from pad
ARM: imx6q: remove unneeded clk lookups
ARM: imx_v6_v7_defconfig: Select CONFIG_MMC_UNSAFE_RESUME
ARM: imx_v4_v5_defconfig: Select CONFIG_MMC_UNSAFE_RESUME
... -
…linux into next/cleanup
Merge a mach header include removal from Haojian Zhuang.
* tag 'irq-mmp' of https://git.kernel.org/pub/scm/linux/kernel/git/hzhuang1/linux:
irqchip: mmp: avoid use head file in a specific archSigned-off-by: Olof Johansson <olof@lixom.net>
-
…ene/linux-samsung into next/cleanup
Samsung drivers update for v3.15 from Kukjin Kim:
- remove inclusion <asm/mach/time.h> from exynos_mct.c
- remove inclusion <asm/mach/irq.h> from exynos-combiner.c
and use calling handle_bad_irq() instead of do_bad_IRQ()* tag 'samsung-drivers' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
irqchip: exynos-combiner: call handle_bad_irq directly
clocksource: exynos_mct: remove unwanted header file inclusionSigned-off-by: Olof Johansson <olof@lixom.net>
09 Mar, 2014
1 commit
-
…/kernel/git/tmlind/linux-omap into next/drivers
Merge OMAP crossbar support from Tony Lindgren:
Add support for GIC crossbar that routes interrupts on newer omaps.
Looks like people wanted these merged via the omap tree as it's
the only user for the GIC crossbar.* tag 'omap-for-v3.15/crossbar-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: DRA: Enable Crossbar IP support for DRA7XX
ARM: OMAP4+: Correct Wakeup-gen code to use physical irq number
DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP
DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqsSigned-off-by: Olof Johansson <olof@lixom.net>
06 Mar, 2014
2 commits
-
drivers/irqchip/irq-gic.c:53:23: warning: duplicate [noderef]
drivers/irqchip/irq-gic.c:651:6: warning: symbol 'gic_raise_softirq' was not declared. Should it be static?
drivers/irqchip/irq-gic.c:872:29: warning: symbol 'gic_irq_domain_ops' was not declared. Should it be static?
drivers/irqchip/irq-gic.c:977:12: warning: symbol 'gic_of_init' was not declared. Should it be static?Signed-off-by: Stephen Boyd
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1393981321-25721-1-git-send-email-sboyd@codeaurora.org
Signed-off-by: Thomas Gleixner -
drivers/irqchip/irqchip.c:27:13: warning: symbol 'irqchip_init'
was not declared. Should it be static?Signed-off-by: Stephen Boyd
Cc: trivial@kernel.org
Link: http://lkml.kernel.org/r/1393981281-25553-1-git-send-email-sboyd@codeaurora.org
Signed-off-by: Thomas Gleixner
05 Mar, 2014
1 commit
-
The user space interface does not filter out offline cpus. It merily
verifies that the mask contains at least one online cpu. So the
selector in the irq chip implementation needs to make sure to pick
only an online cpu because otherwise:Offline Core 1
Set affinity to 0xe
Selector will pick first set bit, i.e. core 1Signed-off-by: Thomas Gleixner
Cc: Chris Zankel
Cc: xtensa
04 Mar, 2014
2 commits
-
This reverts commit 40b367d95fb3d60fc1edb9ba8f6ef52272e48936.
Russell King has raised the idea of creating a proper PMU driver for
this SoC that would incorporate the functionality currently in this
driver. It would also cover the use case for the graphics subsystem on
this SoC.To prevent having to maintain the devicetree ABI for this limited
interrupt-handler driver, we revert the driver before it hits a mainline
tagged release (eg v3.15).Signed-off-by: Jason Cooper
Cc: linux-arm-kernel@lists.infradead.org
Cc: Andrew Lunn
Cc: Sebastian Hesselbarth
Cc: Gregory CLEMENT
Cc: Russell King - ARM Linux
Link: http://lkml.kernel.org/r/1393911160-7688-1-git-send-email-jason@lakedaemon.net
Signed-off-by: Thomas Gleixner -
For example, arm64 doesn't have mach/irq.h.
Signed-off-by: Neil Zhang
Acked-by: Haojian Zhuang
Acked-by: Thomas Gleixner
Signed-off-by: Haojian Zhuang
01 Mar, 2014
1 commit
-
This adds the irqchip driver for Cirrus Logic CLPS711X series SoCs.
Signed-off-by: Alexander Shiyan
Signed-off-by: Arnd Bergmann
26 Feb, 2014
4 commits
-
Fix irq_set_affinity callbacks in the Meta IRQ chip drivers to AND
cpu_online_mask into the cpumask when picking a CPU to vector the
interrupt to.As Thomas pointed out, the /proc/irq/$N/smp_affinity interface doesn't
filter out offline CPUs, so without this patch if you offline CPU0 and
set an IRQ affinity to 0x3 it vectors the interrupt onto CPU0 even
though it is offline.Reported-by: Thomas Gleixner
Signed-off-by: James Hogan
Cc: Thomas Gleixner
Cc: linux-metag@vger.kernel.org
Cc: stable@vger.kernel.org -
When sending an SGI to another CPU, we require a barrier to ensure that
any pending stores to normal memory are made visible to the recipient
before the interrupt arrives.Rather than use a vanilla dsb() (which will soon cause an assembly error
on arm64) before the writel_relaxed, we can instead use dsb(ishst),
since we just need to ensure that any pending normal writes are visible
within the inner-shareable domain before we poke the GIC.With this observation, we can then further weaken the barrier to a
dmb(ishst), since other CPUs in the inner-shareable domain must observe
the write to the distributor before the SGI is generated.Cc: Thomas Gleixner
Acked-by: Marc Zyngier
Acked-by: Catalin Marinas
Signed-off-by: Will Deacon
Signed-off-by: Arnd Bergmann -
vic_init_cascaded is called by integrator impd1 code that can
be a loadable module, so the function has to be exported.Signed-off-by: Arnd Bergmann
Acked-by: Linus Walleij -
irqchip mvebu fixes for v3.14
- orion:
- fixes for clearing bridge cause register, and clearing stale interrupts* tag 'irqchip-mvebu-fixes-3.14' of git://git.infradead.org/linux-mvebu:
irqchip: orion: Fix getting generic chip pointer.
irqchip: orion: clear stale interrupts in irq_startup
irqchip: orion: use handle_edge_irq on bridge irqs
irqchip: orion: clear bridge cause register on initThis is a dependency for the mvebu watchdog changes.
Signed-off-by: Arnd Bergmann
22 Feb, 2014
6 commits
-
irqchip mvebu changes for v3.15
- armada-370-xp
- add MSI helper
- MPIC chained handlerSigned-off-by: Thomas Gleixner
-
The new Armada 375 and Armada 38x Marvell SoCs are based on Cortex-A9
CPU cores and use the ARM GIC as their main interrupt controller.
However, for various purposes (wake-up from suspend, MSI interrupts),
they have kept a separate MPIC interrupt controller, acting as a slave
to the GIC. This MPIC was already used as the primary controller on
previous Marvell SoCs, so this commit extends the existing driver to
allow the MPIC to be used as a GIC slave.Reviewed-by: Gregory CLEMENT
Signed-off-by: Ezequiel Garcia
Signed-off-by: Jason Cooper -
Introduce a helper function to handle the MSI interrupts. This makes
the code more readable. In addition, this will allow to introduce a
chained IRQ handler mechanism, which is needed in situations where the
MPIC is used as a slave to another interrupt controller.Reviewed-by: Gregory CLEMENT
Signed-off-by: Ezequiel Garcia
Signed-off-by: Jason Cooper -
mvebu irqchip fixes for v3.13
- armada-370-xp
- fix races is MSI and IPI -
irqchip mvebu fixes for v3.14
- orion:
- fixes for clearing bridge cause register, and clearing stale interruptsSigned-off-by: Thomas Gleixner
-
Enabling SPARSE_IRQ shows up a bug in the irq-orion bridge interrupt
handler. The bridge interrupt is implemented using a single generic
chip. Thus the parameter passed to irq_get_domain_generic_chip()
should always be zero.Signed-off-by: Andrew Lunn
Acked-by: Sebastian Hesselbarth
Fixes: 9dbd90f17e4f ("irqchip: Add support for Marvell Orion SoCs")
Cc: # v3.11+
Signed-off-by: Jason Cooper
19 Feb, 2014
1 commit
-
mvebu irqchip changes for v3.14
- add Dove PMU interrupt controller
Duh. I completely forgot about that one...
Signed-off-by: Thomas Gleixner
14 Feb, 2014
1 commit
-
This patch is inspired from following commit aec00956
(irqchip: gic: Call handle_bad_irq() directly)Also this will help in removing unwanted inclusion
of header file "asm/mach/irq.h"Signed-off-by: Pankaj Dubey
Reviewed-by: Tomasz Figa
Signed-off-by: Kukjin Kim
